CN107960019A - A PCB manufacturing method and PCB for realizing zero residual piles - Google Patents

Abstract

The invention relates to the technical field of PCBs (printed circuit boards), and discloses a PCB manufacturing method for realizing zero stub and a PCB, wherein the method comprises the following steps: stacking N core boards, and stacking an electrical isolation layer between the K-th core board and the K + 1-th core board; n and K are integers, N is more than or equal to 3, and K is more than or equal to 2 and less than N; pressing the stacked N core boards and the electrical isolation layer to form a multilayer board; forming a through hole in the multilayer board, wherein the through hole comprises a first hole section penetrating through the first layer of core board to the K layer of core board, a second hole section penetrating through the electrical isolation layer and a third hole section penetrating through the K +1 layer of core board to the N layer of core board along the axial direction of the through hole; electroplating the through hole with deposited copper to form copper layers on the inner walls of the first hole section and the third hole section, wherein the copper layer cannot be formed on the inner wall of the second hole section; and removing the copper layer on the inner wall of the third hole section. The embodiment of the invention can completely remove the invalid hole copper and realize zero stub while realizing the electric conduction between partial core boards.

Description

A PCB manufacturing method and PCB for realizing zero residual piles

technical field

The invention relates to the technical field of PCB (Printed Circuit Board, printed circuit board), in particular to a PCB manufacturing method and a PCB for realizing zero stubs.

Background technique

PCB boards in the prior art are generally composed of multi-layer boards. In order to realize the electrical connection between multi-layer boards, people usually open a through hole on the PCB board, and then electroplate a layer of copper plating on the inner wall of the through hole. In this way, the electrical conduction between the multilayer boards is realized.

In the production of multi-layer boards, it is often necessary to divide the multi-layer boards into segment A and segment B along the stacking direction. The multi-layer boards in segment A are electrically connected, and the multi-layer boards in segment B do not need Electrical continuity. When making a PCB, in order to ensure the uniformity of the electrical connection between the multilayer boards in the A section, a through hole is usually opened on the PCB board through the A section and the B section at the same time, and copper is plated on the inner wall of the through hole. Then use back drilling to remove the copper in the invalid holes in section B. When back-drilling, in order to avoid damage to the copper plating in section A due to excessive back-drilling, a section of copper plating as short as possible is usually reserved at the bottom of section B, that is, a stub.

Back-drilling is the current depth-controlled drilling technology. Due to the limitation of medium thickness change and drilling depth accuracy control ability during the pressing process, the stub length control ability is poor. If the stub is too long, it will affect the electrical conduction and signal integrity, and the ideal condition of zero stub cannot be achieved.

Contents of the invention

The object of the present invention is to provide a PCB manufacturing method and PCB that realize zero stubs, and overcome the defect that the stub cannot be completely removed in the traditional back-drilling process.

For reaching this purpose, the present invention adopts following technical scheme:

A PCB manufacturing method for realizing zero stumps, comprising:

Stack the N core boards sequentially according to the preset order, and at the same time stack an electrical isolation layer between the Kth core board and the K+1th layer core board to realize the electrical isolation of two adjacent core boards ; Both N and K are integers, and N≥3, 2≤K<N;

Laminating the stacked N core boards and electrical isolation layers to form a multilayer board;

A through hole is set on the multi-layer board, and the through hole includes a first hole section passing through the first layer core board to the Kth layer core board, a second hole section passing through the electrical isolation layer and a second hole section passing through the The third hole section from the K+1 layer core board to the Nth layer core board;

Immersion copper electroplating on the through hole, so that the inner wall of the first hole section and the third hole section forms a copper layer, and the inner wall of the second hole section cannot form a copper layer;

removing the copper layer on the inner wall of the third hole section.

Optionally, the electrical isolation layer is made of a material that cannot be electroplated with copper.

Optionally, the electrical isolation layer is made of a material that can be dissolved in copper plating solution.

Optionally, the area of the electrical isolation layer is greater than the cross-sectional area of the through hole; and after the through hole is opened, the electrical isolation layer has an edge with a preset width around the through hole .

Optionally, the area of the electrical isolation layer is smaller than the surface area of the K+1th layer core board.

Optionally, the center point of the electrical isolation layer is located on the axis of the through hole.

Optionally, chemical etching is used to remove the copper layer on the inner wall of the third hole segment.

Optionally, the PCB manufacturing method also includes:

Before chemical etching is used to remove the copper layer on the inner wall of the third hole section, a tin layer is plated on the outer surface of the first core board and the inner wall of the first hole section;

After the copper layer on the inner wall of the third hole section is removed by chemical etching, the tin layer is removed.

Optionally, the PCB manufacturing method also includes:

After sinking copper to the through hole and electroplating, at the through hole position on the outer surface of the Nth layer core board, etching the invalid hole copper on the edge of the hole to form an isolated hole ring;

While removing the copper layer on the inner wall of the third hole section, the copper layer on the annular ring is removed.

A PCB, which is manufactured according to any one of the manufacturing methods described above.

Compared with prior art, the beneficial effect of the present invention is:

In the embodiment of the present invention, according to the electrical design requirements, an electrical isolation layer can be added between the two adjacent core boards that are not conducting, so that the two parts of the core boards after copper plating are isolated from each other, and then the copper part of the invalid hole is removed in a conventional way. The method can completely remove copper in invalid holes and realize zero stub while realizing electrical conduction between partial layer core boards.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings on the premise of not paying creative efforts.

Fig. 1 is the flow chart of the PCB manufacturing method for realizing zero stump provided by the embodiment of the present invention;

Fig. 2 is a cross-sectional view of a multilayer board formed by pressing four core boards and an electrical isolation layer;

Fig. 3 is a cross-sectional view of the multilayer board shown in Fig. 2 after opening through holes;

Fig. 4 is the cross-sectional view of the multilayer board shown in Fig. 3 after copper plating;

Fig. 5 is a cross-sectional view of the multilayer board shown in Fig. 4 after an independent annular ring is formed on the surface of the fourth core board;

Fig. 6 is the cross-sectional view of the multilayer board shown in Fig. 5 after the copper surface of the effective hole is tin-plated;

Fig. 7 is a cross-sectional view of the multilayer board shown in Fig. 6 after etching away the copper in the invalid holes;

Fig. 8 is a cross-sectional view of the multilayer board shown in Fig. 7 after stripping tin;

Detailed ways

In order to make the purpose, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the following The described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Please refer to Fig. 1, the PCB manufacturing method for realizing zero stumps in this embodiment specifically includes the following steps:

S101. Stack the N core boards sequentially according to the preset order, including the first layer of core boards, the second layer of core boards, ..., the N-1th layer of core boards, and the Nth layer of core boards along the stacking direction, wherein N is an integer not less than 3.

In the process of stacking, according to the preset electrical design requirements, an electrical isolation layer is stacked between the Kth layer core board and the K+1th layer core board, where K is an integer and 2≤K< N.

In this embodiment, the preset electrical design requirement is: the multi-layer core boards from the first layer core board to the Kth layer core board are electrically connected to each other, and are connected to the K+1th layer core board to the Nth layer core board There is no electrical continuity between the boards.

According to the preset electrical design requirements, the stacked N core boards can be divided into the first part of the core board and the second part of the core board along the stacking direction; the first part of the core board is from the first layer of core boards to the Kth layer of core boards The second part of the core board is composed of the K+1th layer core board to the Nth layer core board.

The electrical isolation layer will be used to realize the electrical isolation between the first part of the core board and the second part of the core board in subsequent processing procedures. For this reason, the electrical isolation layer can be made of materials that cannot be electroplated by copper deposition, or can be made of materials that can be dissolved in the electroplating solution of copper deposition. In the subsequent copper deposition electroplating process, the electrical isolation layer plays a role, making The first part of the core board is electrically isolated from the second part of the core board.

It should also be noted that the projection area of the electrical isolation layer on the board surface of the K+1 layer core board must cover the projection area of the through hole to be opened on the board surface of the K+1 layer core board. It will be used to realize the electrical conduction between the multi-layer core boards of the first part of the core board after copper sinking electroplating. In addition, the area of the electrical isolation layer is greater than the cross-sectional area of the through hole by a predetermined value, so that the electrical isolation layer still has a certain width of edge around the hole after drilling the through hole, and it is not necessary to completely cover the Kth hole. +1 the entire surface of the core board.

S102 , press the N sheets of core boards and electrical isolation layers stacked in step S101 to form a multi-layer board, as shown in FIG. 2 .

In this step, a conventional hot pressing method can be used to bond the adjacent two layers of core boards through the prepreg.

S103. Open a through hole at a preset position on the multilayer board, and the through hole penetrates each core board and the electrical isolation layer of the multilayer board, as shown in FIG. 3 .

In this step, the opened through hole includes three hole sections along its axial direction, the first hole section is the through hole part that passes through the first part of the core board (that is, the first layer of core board to the Kth layer of core board), and the second hole The segment is a through hole part penetrating through the electrical isolation layer, and the third hole segment is a through hole part penetrating through the second part of the core board (that is, the K+1th layer core board to the Nth layer core board).

S104 , performing immersion copper electroplating on the entire board surface and through holes of the multilayer board, as shown in FIG. 4 .

Since the electrical isolation layer between the first part of the core board and the second part of the core board is also drilled after the through hole is opened, the inner wall of the second hole section of the above-mentioned through hole is an electrical isolation layer before the copper sinking electroplating. The materials used are non-copper-plating materials or materials that can be dissolved in copper-plating chemicals.

If the electrical isolation layer is a non-copper plating material, then after the copper plating, the inner wall of the second hole section of the above-mentioned through hole will not be able to form a copper layer, and it is still a non-copper plating material, while the first hole section and the third hole section The inner wall of the hole section will form a copper layer, thereby enabling the electrical isolation of the first part of the core board from the second part of the core board.

If the electrical isolation layer is a material that can be dissolved in the copper plating solution, then after the copper plating, the electrical isolation layer will be partially dissolved in the copper plating solution, and the dissolved area will form a void, resulting in a larger aperture of the second hole section , and the inner wall of the first hole section and the third hole section will form a copper layer, so that the inner wall of the first hole section and the third hole section will form a copper layer, so that the first part of the core board and the second part of the core board electrical isolation. S105 , at the position of the through hole on the outer surface of the core board of the second part, etch the copper of the invalid hole around the hole to form an isolated hole ring, as shown in FIG. 5 .

S106 , removing the copper layer on the inner wall of the annular ring and the third hole segment by conventional chemical etching.

In this step, the specific method for removing the copper layer on the inner wall of the annular ring and the third hole section is as follows:

First, the outer surface of the first part of the core board and the inner wall of the first hole section are plated with a layer of tin as a protective layer for subsequent etching; at this time, due to the barrier of the electrical isolation layer, the surface of the second part and the inner wall of the third hole section will not be able to Tin plating;

Etching and removing the annular ring on the surface of the second part of the core board and the invalid copper layer on the inner wall of the third hole section;

Then, remove the tin from the outer surface of the first part of the core board and the inner wall of the first hole section.

So far, the first layer core board to the Kth layer core board of the first part of the core board are electrically connected to each other, and are not electrically connected to the second part of the core board.

An example will be provided below.

1) Stack 4 core boards, and add an electrical isolation layer 10 between the second layer core board and the third layer core board. The electrical isolation layer 10 is made of a material that cannot be plated with copper.

2) As shown in Figure 2, press the 4 core boards and electrical isolation layers stacked in a preset order to make a multi-layer board.

3) As shown in FIG. 3 , drill a through hole 20 on the multi-layer board, the through hole sequentially includes a first hole segment, a second hole segment and a third hole segment along its axial direction.

4) As shown in Figure 4, copper plating is performed on the multi-layer board, and a copper layer is formed on the inner walls of the first hole section and the third hole section, and a copper layer cannot be formed on the inner wall of the second hole section due to material reasons.

5) As shown in FIG. 5 , an independent annular ring 30 is formed at the position of the through hole on the outer surface of the fourth-layer core board through operations such as film attachment, exposure, and etching.

6) As shown in FIG. 6 , tin-plate the outer surface of the first core board and the inner wall of the first hole section with tin 40 to form a protective layer.

7) As shown in FIG. 7 , etching removes the annular ring 30 on the outer surface of the fourth core board and the copper layer on the inner wall of the third hole section.

8) As shown in Figure 8, remove the tin 40 on the outer surface of the first core board and the inner wall of the first hole section.

So far, the first-layer core board will be electrically connected to the second-layer core board, and will not be electrically connected to the third-layer core board and the fourth-layer core board. While realizing the preset electrical design requirements, it will also completely remove the Ineffective hole copper is eliminated, and zero stub is realized.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still understand the foregoing The technical solutions recorded in each embodiment are modified, or some of the technical features are replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. A PCB manufacturing method that realizes zero stump, is characterized in that, described PCB manufacturing method comprises: Stack the N core boards sequentially according to the preset order, and at the same time stack an electrical isolation layer between the Kth core board and the K+1th layer core board to realize the electrical isolation of two adjacent core boards ; Both N and K are integers, and N≥3, 2≤K<N; Laminating the stacked N core boards and electrical isolation layers to form a multilayer board; A through hole is set on the multi-layer board, and the through hole includes a first hole section passing through the first layer core board to the Kth layer core board, a second hole section passing through the electrical isolation layer and a second hole section passing through the The third hole section from the K+1 layer core board to the Nth layer core board; Immersion copper electroplating on the through hole, so that the inner wall of the first hole section and the third hole section forms a copper layer, and the inner wall of the second hole section cannot form a copper layer; removing the copper layer on the inner wall of the third hole section. 2 . The PCB manufacturing method for realizing zero stubs according to claim 1 , wherein the electrical isolation layer is made of a material that cannot be electroplated with copper. 3 . 3. The PCB manufacturing method for achieving zero stubs according to claim 1, wherein the electrical isolation layer is made of a material that can be dissolved in copper sinking electroplating solution. 4. The PCB manufacturing method realizing zero stumps according to claim 1, wherein the area of the electrical isolation layer is greater than the cross-sectional area of the through hole; and after the through hole is opened, the The electrical isolation layer leaves an edge with a predetermined width around the through hole. 5 . The PCB manufacturing method for achieving zero stubs according to claim 4 , wherein the area of the electrical isolation layer is smaller than the surface area of the K+1th layer core board. 5 . 6 . The PCB manufacturing method for achieving zero stubs according to claim 4 , wherein the central point of the electrical isolation layer is located on the axis of the through hole. 7 . 7 . The PCB manufacturing method for realizing zero residual piles according to claim 1 , wherein the copper layer on the inner wall of the third hole section is removed by chemical etching. 7 . 8. The PCB manufacturing method realizing zero residual piles according to claim 7, characterized in that, the PCB manufacturing method further comprises: Before chemical etching is used to remove the copper layer on the inner wall of the third hole section, a tin layer is plated on the outer surface of the first core board and the inner wall of the first hole section; After the copper layer on the inner wall of the third hole section is removed by chemical etching, the tin layer is removed. 9. The PCB manufacturing method realizing zero stumps according to claim 7, characterized in that, the PCB manufacturing method further comprises: After sinking copper to the through hole and electroplating, at the through hole position on the outer surface of the Nth layer core board, etching the invalid hole copper on the edge of the hole to form an isolated hole ring; While removing the copper layer on the inner wall of the third hole section, the copper layer on the annular ring is removed. 10. A PCB, characterized in that the PCB is manufactured according to any one of the manufacturing methods of claims 1-9.