CN107959649B - Symbol timing synchronization simplification method in OFDM system receiver - Google Patents

Abstract

The invention discloses a simplified method for symbol timing synchronization in an OFDM system receiver. The _simplified method is a symbol timing synchronization method based on a special training sequence. After the absolute value, carry out the accumulation operation to obtain the first operation result; the value T _k of each symbol bit of the local special sequence of length 1 does the sign optimization operation, and each signal value R _n+k of the received signal is equal to sign(T _k ) value is multiplied, and then accumulated and taken as an absolute value to obtain a second operation result; the second operation result is divided with the first operation result, and peak detection is performed on the division result Q′ _n Then the symbol timing signal is obtained. The symbol timing synchronization simplification method in the OFDM system receiver simplifies the symbol timing synchronization algorithm based on the training sequence and its hardware implementation structure.

Description

A Simplified Method for Symbol Timing Synchronization in OFDM System Receivers

technical field

The present invention relates to the field of communications, in particular to a simplified method for symbol timing synchronization in an OFDM system receiver.

Background technique

Orthogonal Frequency Division Multiplexing (OFDM) is a high-speed transmission technology in a wireless environment. The core of the technology is to divide the channel into several orthogonal sub-channels, convert high-speed data signals into parallel low-speed sub-data streams, and modulate them for transmission on each sub-channel. Orthogonal signals can be separated by adopting correlation technology at the receiving end, which can reduce the mutual interference between sub-channels. The signal bandwidth on each sub-channel is smaller than the relevant bandwidth of the channel, so each sub-channel can be regarded as flat fading, so that the inter-symbol crosstalk can be eliminated, and since the bandwidth of each sub-channel is only a small part of the original channel bandwidth, channel equalization becomes relatively easy. Because of these characteristics, this technology is especially suitable for wireless mobile channel communication with multipath propagation and Doppler frequency shift, and is the core technology of the fourth generation mobile communication technology.

In the OFDM system, since the orthogonality between the sub-channel signals needs to be maintained, the receiving end needs high synchronization during signal demodulation. Deviations in symbol timing synchronization can lead to inter-symbol interference, and in severe cases, inter-sub-carrier interference, resulting in system performance degradation.

The existing OFDM system symbol timing synchronization methods are all training sequence-based symbol timing synchronization algorithms, which are algorithms in which the transmitter sends a special training sequence whose data is known, and receives complete training symbols to perform symbol timing synchronization. The existing symbol timing synchronization algorithms based on special training sequences have relatively high accuracy, but the computational complexity is too high when implemented in hardware.

Each signal of the received signal takes the absolute value and then performs the accumulation operation to obtain an operation result. Each signal of the received signal is multiplied by each signal of the local special training sequence, and then accumulates and takes the absolute value to obtain an operation result. The two operation results are divided, and the symbol timing signal is obtained after peak detection.

The symbol timing signal algorithm is as follows:

where Qn is the symbol timing signal, R( _{n +k) is} the received signal, Tk is the local special training sequence, l is the length of the local special training sequence, the received signal R _{(n+k) and} the local training sequence Tk are both is a real signal.

Taking an OFDM system with 1024 subcarriers as an example, when standard symbol timing synchronization is adopted, 1024 multiplications are required for each successful symbol timing detection. 4 times, and 1024 accumulation and absolute value operations in the back end. When a multiplier is generally implemented digitally, both the multiplier and the multiplicand are quantized into signed or unsigned numbers with a width of n bits. In this way, the wider the quantization bit width, the higher the complexity of the multiplication operation.

Although there are various simplified algorithms, they are basically aimed at the simplification of back-end peak detection and detection methods, and the real operations of front-end multiplication and accumulation are difficult to bypass. The hardware implementation of this symbol timing synchronization algorithm is very complicated.

The information disclosed in this Background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for simplifying symbol timing synchronization in an OFDM system receiver, which simplifies a symbol timing synchronization algorithm based on a training sequence and its hardware implementation structure.

To achieve the above object, the present invention provides a simplified method for symbol timing synchronization, which is a method for symbol timing synchronization based on a special training sequence, comprising the following steps:

After each signal value R _n+k of the received signal takes an absolute value, an accumulation operation is performed to obtain a first operation result;

The value T _k of each sign bit of the local special sequence of length l is used for sign optimization. The algorithm is as follows;

Each bit of the signal value R _n+k of the received signal and the sign(T _k ) value do a multiplication operation, and then do an accumulation operation to obtain a second operation result; And

Divide the second operation result and the first operation result, and perform peak detection on the division result _Q'n to obtain a symbol timing signal. The formula of _Q'n is as follows:

Preferably, in the above technical solution, when each signal of the received signal is multiplied by sign(T _k ), a multiplier is not required, and only an if statement is needed: when sign(T _k ) is 1 , the result of the multiplication operation is obtained by taking the original value of the bit signal value R _n+k of the received signal; when sign(T _k ) is -1, the bit signal value R of the received signal The result of the multiplication operation is obtained by negating _n+k ; when sign(T _k ) is 2, the bit signal value R _n+k of the received signal is shifted to obtain the result of the multiplication operation. As a result, when sign(T _k ) is -2, the result of the multiplication operation is obtained by shifting and negating the bit signal value R _n+k of the received signal.

Compared with the prior art, the present invention has the following beneficial effects:

No multiplier is needed, which greatly simplifies the algorithm and hardware implementation structure of the symbol timing synchronization based on the training sequence.

Description of drawings

FIG. 1 is a hardware schematic diagram of a training sequence-based symbol timing synchronization method according to an embodiment of the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

Unless expressly stated otherwise, throughout the specification and claims, the term "comprising" or its conjugations such as "comprising" or "comprising" and the like will be understood to include the stated elements or components, and Other elements or other components are not excluded.

The invention proposes a method for calculating the symbol timing, which simplifies the operation and discards the multiplier in principle, which can greatly simplify the hardware implementation complexity.

FIG. 1 is a hardware schematic diagram of a simplified algorithm for symbol timing synchronization based on a training sequence according to an embodiment of the present invention.

The ingeniousness of the algorithm lies in the fact that the local special training sequence T _k is a carefully designed special symbol sequence, which is generally composed of sequences with very good autocorrelation performance and poor cross-correlation performance. The received signal R _n is the sampled value, and this signal cannot be simplified. However, the local training sequence T _k can be optimized in advance so that after it is multiplied by R _n , the result of the symbol timing signal is not affected, so that the multiplier can be simplified.

The symbol timing synchronization algorithm based on a special training sequence is as follows:

1. After each signal value R _n+k of the received signal takes the absolute value, the accumulation operation is performed to obtain the first operation result;

2. The value T _k of each sign bit of the local special sequence of length l is used for sign optimization. The algorithm is as follows;

If the value of each sign bit of the local special sequence T _k is greater than or equal to 0 and less than 1, it is directly quantized to 1. If the value of each sign bit of T _k is greater than 1, it is directly quantized to 2. If the value of each sign bit of the local special sequence T _k is greater than or equal to -1 and less than 0, it is directly quantized to -1. If the value of each sign bit of T _k is less than -1, it is directly quantized to -2. After this processing, both the sign bit attribute and the magnitude attribute are preserved.

3. Multiply each signal value R _n+k of the received signal with the sign(T _k ) value, and then perform an accumulation operation to obtain a second operation result; and

4. Divide the second operation result and the first operation result, and perform peak detection on the division result _Q'n to obtain a symbol timing signal. The formula of _Q'n is as follows.

According to the formula analysis, the algorithm does not need multipliers. The original n-bit multiplier can be replaced by an if statement to take the original value or invert or shift, which simplifies the amount of operations fundamentally.

After the above simplification, the peak detection has been greatly simplified, and the two peak intervals are one FFT/IFFT as the judgment condition during the judgment.

The method for simplifying the symbol timing synchronization in the OFDM system receiver does not need a multiplier, which greatly simplifies the algorithm and hardware structure of the symbol timing synchronization based on the training sequence.

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise form disclosed, and obviously many changes and modifications are possible in light of the above teachings. The exemplary embodiments were chosen and described for the purpose of explaining certain principles of the invention and their practical applications, to thereby enable one skilled in the art to make and utilize various exemplary embodiments and various different aspects of the invention. Choose and change. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims (2)

1. A simplified method for symbol timing synchronization in an OFDM system receiver, which is a symbol timing synchronization method based on a special training sequence, characterized in that it comprises the following steps: After each signal value R _n+k of the received signal takes an absolute value, an accumulation operation is performed to obtain a first operation result; The value T _k of each sign bit of the local special sequence of length l is used for sign optimization. The algorithm is as follows;

Each bit of the signal value R _n+k of the received signal and the sign(T _k ) value do a multiplication operation, and then do an accumulation operation to obtain a second operation result; And Divide the second operation result and the first operation result, and perform peak detection on the division result _Q'n to obtain a symbol timing signal. The formula of _Q'n is as follows:

2. the symbol timing synchronization method based on special training sequence according to claim 1, is characterized in that, when each signal of described received signal and sign (T _k ) do multiplication operation, do not need multiplier, only need If statement can be achieved: When sign(T _k ) is 1, the result of the multiplication operation is obtained by taking the original value of the bit signal value R _n+k of the received signal; When sign(T _k ) is -1, the result of the multiplication operation is obtained by inverting the bit signal value R _n+k of the received signal; When sign(T _k ) is 2, the result of the multiplication operation is obtained by shifting the bit signal value R _n+k of the received signal; When sign(T _k ) is -2, the result of the multiplication operation is obtained by shifting and negating the bit signal value R _n+k of the received signal.

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