CN107947781A - A kind of active diode of adaptive conducting resistance - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit design and relates to an active diode with self-adaptive on-resistance. The active diode of the adaptive on-resistance includes a switching tube module, a comparator module and a logic and control unit module; the output terminal of the switching tube module is electrically connected to the input terminal of the comparator module; the comparator module The output end of the logic and control unit module is electrically connected to the input end of the logic and control unit module; the output end of the logic and control unit module is electrically connected to the input end of the switch tube module. The adaptive change of the on-resistance of the active diode can improve the detection accuracy of the zero-crossing point of the active diode current, broaden the input range of the active diode, and realize a low-on-state voltage drop, high-precision current zero-crossing detection, and a wide input range. active diodes.

Description

An Active Diode with Adaptive On-Resistance

technical field

The invention belongs to the technical field of integrated circuit design and relates to an active diode with self-adaptive on-resistance.

Background technique

In recent years, wireless sensor network nodes and biomedical electronic devices have become popular research topics. The traditional battery power supply is limited by battery volume and battery life, which restricts the miniaturization of electronic devices and limits the battery life of electronic devices. Self-powering of electronic devices, that is, capturing the energy in the environment and converting it into electrical energy for power supply is almost the best choice for future sustainable power supply technology. There are abundant energy sources in nature, such as thermal power sources, radio frequency sources, photovoltaic sources, piezoelectric sources, etc. Among them, piezoelectric sources are less restricted by natural conditions than other forms of energy sources, and have higher energy density, It is easy to expand, so the energy harvesting technology solution based on the piezoelectric source is favored.

Usually piezoelectric sensors capture the vibration energy of the surrounding environment and convert the vibration energy into electrical energy, but the output electrical energy of piezoelectric sensors is usually an AC source, which cannot directly supply power to electronic equipment, so a rectifier interface is required before powering electronic equipment circuit. The rectification interface circuit mainly utilizes the unidirectional conductivity of the diode, so the performance of the diode used has an important influence on the performance of the rectifier. The conduction voltage drop of traditional Schottky diodes is high, and the conduction loss of the diode is large, so the rectification efficiency is seriously affected, and the large diode conduction voltage drop also limits the input range of the rectification interface circuit.

For this reason, an active diode based on a comparator is proposed. The conduction voltage drop of the active diode is reduced, and the rectification efficiency is improved. However, limited by the input accuracy of the comparator, the zero-crossing detection of the active diode current The accuracy is low, so the input range of the rectification interface circuit based on the active diode is still limited.

Contents of the invention

In order to solve the problems in the prior art, the present invention proposes an active diode with adaptive on-resistance.

Specifically, an embodiment of the present invention provides an active diode with adaptive on-resistance, including:

Switch tube module 101, comparator module 102 and logic and control unit module 103; Wherein,

The output terminal of the switch tube module 101 is electrically connected to the input terminal of the comparator module 102;

The output end of the comparator module 102 is electrically connected to the input end of the logic and control unit module 103;

The output terminal of the logic and control unit module 103 is electrically connected to the input terminal of the switch tube module 101 .

In one embodiment of the present invention, the switching tube module 101 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6 and the seventh PMOS transistor MP7; wherein,

The source of the first PMOS transistor MP1 is electrically connected to the source of the second PMOS transistor MP2, the source of the third PMOS transistor MP3, the source of the fourth PMOS transistor MP4, the fifth the source of the PMOS transistor MP5, the source of the sixth PMOS transistor MP6, and the gate of the seventh PMOS transistor MP7;

The drain of the first PMOS transistor MP1 is electrically connected to the drain of the second PMOS transistor MP2, the drain of the third PMOS transistor MP3, the drain of the fourth PMOS transistor MP4, the fifth the drain of the PMOS transistor MP5, the drain of the seventh PMOS transistor MP7, and the gate of the sixth PMOS transistor MP6;

The substrate of the first PMOS transistor MP1 is electrically connected to the substrate of the second PMOS transistor MP2, the substrate of the third PMOS transistor MP3, the substrate of the fourth PMOS transistor MP4, the substrate of the fifth a substrate of the PMOS transistor MP5, a drain and a substrate of the sixth PMOS transistor MP6, and a source and a substrate of the seventh PMOS transistor MP7;

The gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, the gate of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4, the gate of the fifth PMOS transistor The gate of MP5 is electrically connected to the output end of the logic and control unit module 103 respectively;

The source of the first PMOS transistor MP1 is used as the anode terminal ANODE of the switch tube module 101 and is electrically connected to the positive input terminal of the comparator module 102, and the drain of the first PMOS transistor MP1 is used as the switch tube module The cathode terminal CATHODE of 101 is electrically connected to the negative input terminal of the comparator module 102 .

In one embodiment of the present invention, the comparator module 102 includes a first comparator COMP1 and a second comparator COMP2; wherein,

The positive input terminal of the first comparator COMP1 is electrically connected to the anode terminal ANODE of the switching tube module 101, the negative input terminal is electrically connected to the cathode terminal CATHODE of the switching tube module 101, and the output terminal is electrically connected to the logic and control unit a first input of the module 103;

The positive input terminal of the second comparator COMP2 is electrically connected to the anode terminal ANODE of the switching tube module 101, its negative input terminal is electrically connected to the cathode terminal CATHODE of the switching tube module 101, and its output terminal is electrically connected to the logic AND The second input terminal of the control unit module 103 .

In one embodiment of the present invention, the logic and control unit module 103 includes a clock signal logic circuit I1, a counter I2, a decoder I3, and a driving circuit module I4; wherein,

The input end of the clock signal logic circuit I1 is electrically connected to the output end of the comparator module 102; the input end of the counter I2 is electrically connected to the output end of the clock signal logic circuit I1; the input of the decoder I3 terminal is electrically connected to the output terminal of the counter I2; the input terminal of the drive circuit module I4 is electrically connected to the output terminal of the decoder I3, and the output terminal of the drive circuit module I4 is electrically connected to the switching tube module 101 input terminal.

In an embodiment of the present invention, the first input terminal VO1 of the clock signal logic circuit I1 is electrically connected to the first output terminal of the comparator module 102, and the second input terminal VO2 is electrically connected to the first output terminal of the comparator module 102. the second output.

In one embodiment of the present invention, the clock signal input terminal CLK2 of the counter I2 is electrically connected to the clock signal output terminal CLK1 of the clock signal logic circuit I1, and the addition and subtraction counting control terminal V _ADDSUB2 of the counter I2 is electrically connected to the The addition and subtraction counting control output terminal V _ADDSUB1 of the clock signal logic circuit I1, the reset input terminal RST2 of the counter I2 is electrically connected to the reset output terminal RST1 of the clock signal logic circuit I1.

In one embodiment of the present invention, the counter I2 is a 3-bit counter and the decoder I3 is a 3_5 decoder; wherein, the first output terminal QA1 of the 3-bit counter is electrically connected to the 3_5 decoder The first input terminal QA2 of the device; the second output terminal QB1 of the 3-bit counter is electrically connected to the second input terminal QB2 of the 3-5 decoder; the third output terminal QC1 of the 3-bit counter is electrically connected to the The third input terminal QC2 of the 3_5 decoder.

In one embodiment of the present invention, the driving circuit module I4 includes a first driving circuit D1, a second driving circuit D2, a third driving circuit D3, a fourth driving circuit D4, and a fifth driving circuit D5; wherein, the The input terminals of the first drive circuit D1, the second drive circuit D2, the third drive circuit D3, the fourth drive circuit D4, and the fifth drive circuit D5 are electrically connected to the 3-5 decoder respectively. 5 output terminals, the output terminals of the first drive circuit D1, the second drive circuit D2, the third drive circuit D3, the fourth drive circuit D4, and the fifth drive circuit D5 are electrically connected respectively The input end of the switch tube module 101 .

Compared with prior art, the beneficial effect of the present invention is:

1. Under a wide input current range, using the comparator module and the logic and control unit module, the dynamic change of the on-resistance of the active diode can be realized, which can effectively control and reduce the on-voltage drop of the active diode , thereby reducing the conduction loss of the active diode.

2. The active diode with adaptive on-resistance of the present invention can effectively improve the zero-crossing detection accuracy of the active diode current without increasing the input accuracy of the comparator.

3. The improvement of the current zero-crossing detection accuracy of the active diode of the adaptive on-resistance of the present invention effectively widens the input range of the active diode.

Description of drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without making creative efforts.

FIG. 1 is a logical schematic diagram of an active diode with adaptive on-resistance provided by an embodiment of the present invention;

Fig. 2 is a schematic structural diagram of a switch tube module provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a comparator module provided by an embodiment of the present invention;

Fig. 4 is a schematic structural diagram of a logic and control unit module provided by an embodiment of the present invention;

5 is a schematic circuit diagram of an active diode with adaptive on-resistance provided by an embodiment of the present invention;

Fig. 6 is a working principle diagram of an active diode with adaptive on-resistance provided by an embodiment of the present invention within a wide input current variation range;

FIG. 7 is an explanatory diagram of the working states of the switching tubes corresponding to each stage of an active diode with adaptive on-resistance provided by an embodiment of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

Embodiment one:

Referring to FIG. 1 , FIG. 1 is a logical schematic diagram of an active diode with adaptive on-resistance provided by an embodiment of the present invention. The active diode of the adaptive on-resistance includes: a switching tube module 101, a comparator module 102 and a logic and control unit module 103; wherein,

The output terminal of the switch tube module 101 is electrically connected to the input terminal of the comparator module 102, which is used to change the conduction path and limit the current flow direction according to the output signal of the logic and control unit module 103;

The output end of the comparator module 102 is electrically connected to the input end of the logic and control unit module 103 for generating a driving signal acting on the logic and control unit module 103;

The output terminal of the logic and control unit module 103 is electrically connected to the switching tube module 101 for controlling the working state of each transistor in the switching tube module 101 through its output signal.

Further, please refer to FIG. 2 , which is a schematic circuit diagram of a switching tube module provided by an embodiment of the present invention. The switching tube module 101 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6 and a seventh PMOS transistor MP7; wherein,

The source of the first PMOS transistor MP1 is electrically connected to the source of the second PMOS transistor MP2, the source of the third PMOS transistor MP3, the source of the fourth PMOS transistor MP4, the source of the fifth PMOS transistor MP5, and the source of the sixth PMOS transistor MP5. the source of the transistor MP6 and the gate of the seventh PMOS transistor MP7;

The drain of the first PMOS transistor MP1 is electrically connected to the drain of the second PMOS transistor MP2, the drain of the third PMOS transistor MP3, the drain of the fourth PMOS transistor MP4, the drain of the fifth PMOS transistor MP5, and the drain of the seventh PMOS transistor MP5. the drain of the transistor MP7 and the gate of the sixth PMOS transistor MP6;

The substrate of the first PMOS transistor MP1 is electrically connected to the substrate of the second PMOS transistor MP2, the substrate of the third PMOS transistor MP3, the substrate of the fourth PMOS transistor MP4, the substrate of the fifth PMOS transistor MP5, and the substrate of the sixth PMOS transistor MP5. the drain and substrate of transistor MP6 and the source and substrate of seventh PMOS transistor MP7;

The gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, the gate of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4, and the gate of the fifth PMOS transistor MP5 are respectively electrically connected to logic and control The output terminal of the unit module 103;

The source of the first PMOS transistor MP1 serves as the anode terminal ANODE of the switch tube module 101 and is electrically connected to the positive input terminal of the comparator module 102, and the drain of the first PMOS transistor MP1 serves as the cathode terminal CATHODE of the switch tube module 101 and is electrically connected to the comparator module 102's negative input.

In this embodiment, the comparator module 102 is used to detect the voltage drop across the switch tube module 101, and the logic and control unit module 103 is used to dynamically adjust the number of switch tubes in the access current path, thereby realizing the dynamic dynamics of the on-resistance of the active diode. regulation, thereby ensuring that the conduction voltage drop of the active diode is limited within a relatively small range within a wide input current range, effectively controlling the conduction voltage drop of the active diode.

Embodiment two:

In order to facilitate the understanding of the working principle of the present invention, this embodiment describes in detail the circuit structures of the comparator module 102 and the logic and control unit module 103 on the basis of the above embodiments.

Please refer to FIG. 3 . FIG. 3 is a schematic structural diagram of a comparator module provided by an embodiment of the present invention. The comparator module 102 includes a first comparator COMP1 and a second comparator COMP2, wherein,

The positive input terminal of the first comparator COMP1 is electrically connected to the anode terminal ANODE of the switching tube module 101, the negative input terminal is electrically connected to the cathode terminal CATHODE of the switching tube module 101, and its output terminal is electrically connected to the first input terminal of the logic and control unit module 103. ;

The positive input terminal of the second comparator COMP2 is electrically connected to the anode terminal ANODE of the switch tube module 101, its negative input terminal is electrically connected to the cathode terminal CATHODE of the switch tube module 101, and its output terminal is electrically connected to the second input of the logic and control unit module 103 end.

Please refer to FIG. 4 . FIG. 4 is a schematic structural diagram of a logic and control unit module provided by an embodiment of the present invention. The logic and control unit module 103 includes a clock signal logic circuit I1, a counter I2, a decoder I3, and a drive circuit module I4; wherein:

The input end of the clock signal logic circuit I1 is electrically connected to the output end of the comparator module 102; the input end of the counter I2 is electrically connected to the output end of the clock signal logic circuit I1; the input end of the decoder I3 is electrically connected to the output end of the counter I2; The input end of the circuit module I4 is electrically connected to the output end of the decoder I3 , and the output end thereof is electrically connected to the switching tube module 101 .

Further, the first input terminal VO1 of the clock signal logic circuit I1 is electrically connected to the first output terminal of the comparator module 102 , and the second input terminal VO2 is electrically connected to the second output terminal of the comparator module 102 .

In this embodiment, two comparators 102 are used to detect the voltage drop across the switch tube module 101, and the number of switch tubes in the access current path dynamically adjusted by the logic and control unit module 103 is used to realize active diode conduction The dynamic adjustment of the resistance effectively improves the detection accuracy of the zero-crossing point of the active diode current and widens the input range of the active diode.

Embodiment three:

Please refer to FIG. 5 . FIG. 5 is a schematic circuit diagram of an active diode with adaptive on-resistance provided by an embodiment of the present invention. As shown in the figure, the clock signal input terminal CLK2 of the counter I2 is electrically connected to the clock signal output terminal CLK1 of the clock signal logic circuit I1, and its addition and subtraction counting control terminal V _ADDSUB2 is electrically connected to the addition and subtraction counting control output terminal V of the clock signal logic circuit I1. _ADDSUB1 , its reset input terminal RST2 is electrically connected to the reset output terminal RST1 of the clock signal logic circuit I1.

Further, the counter I2 is a 3-bit counter and the decoder I3 is a 3-5 decoder, wherein the first output terminal QA1 of the 3-bit counter is electrically connected to the first input terminal QA2 of the 3-5 decoder; The output terminal QB1 is electrically connected to the second input terminal QB2 of the 3_5 decoder; the third output terminal QC1 of the 3-bit counter is electrically connected to the third input terminal QC2 of the 3_5 decoder.

Further, the drive circuit module I4 includes a first drive circuit D1, a second drive circuit D2, a third drive circuit D3, a fourth drive circuit D4, and a fifth drive circuit D5, wherein the first drive circuit D1, the second drive circuit The input terminals of D2, the third drive circuit D3, the fourth drive circuit D4, and the fifth drive circuit D5 are electrically connected to 5 output terminals of the 3-5 decoder respectively, the first drive circuit D1, the second drive circuit D2, the third drive circuit The output ends of the circuit D3, the fourth drive circuit D4, and the fifth drive circuit D5 are respectively electrically connected to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the gate of the third PMOS transistor MP3 of the switching tube module 101. pole, the gate of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP5.

Referring now to FIG. 6 , FIG. 6 is a working principle diagram of an active diode with adaptive on-resistance provided by an embodiment of the present invention within a wide range of input current variation. When the current flowing through the active diode changes, the voltage drop across the active diode is detected by two comparators COMP1 and COMP2. When the voltage drop across the active diode exceeds the set voltage drop range, the two comparators COMP1 and COMP2 output signals VO1 and VO2, and these two output signals drive the logic and control unit module to dynamically change the conduction state of the transistor in the switch tube module, thereby realizing the dynamic change of the on-resistance of the active diode.

Specifically, in the stage of increasing the input current ip, the active diode of the adaptive on-resistance is initially in the off state, that is, the first stage Φ1, at this time, the five PMOS transistors of the switching tube module 101 are all in the off state; As the input current ip increases, the voltage drop across the switch tube module 101 increases, and when the voltage drop across the switch tube module 101 is greater than the upper limit of the set voltage drop range, the output signal of the comparator module 102 drives the logic and control unit Module 103, the logic and control module 103 generates a control signal and drives the first PMOS transistor MP1 of the switch tube module 101 to conduct, that is, enters the second stage Φ2; with the increase of the input current ip, the voltage drop across the switch tube module 101 When it is greater than the upper limit of the set voltage drop range again, the output signal of the comparator module 102 drives the logic and control unit module 103, and the logic and control module 103 generates a control signal and drives the second PMOS transistor MP2 of the switch tube module 101 to conduct , that is to enter the third stage Φ3; the conduction of the second PMOS transistor MP2 reduces the on-resistance of the switch tube module 101, so the voltage drop of the active diode drops to the limited voltage drop range; as the input current signal ip continues Increase, when the voltage drop across the switch tube module 101 is greater than the upper limit of the set voltage drop range again, the third PMOS transistor MP3 is turned on and works immediately, that is, enters the fourth stage Φ4, and the voltage drop across the switch tube module 101 is again drop to a limited voltage drop range; as the input current ip increases, the fourth PMOS transistor MP4 is turned on, that is, enters the fifth stage Φ5, and the fifth PMOS transistor MP5 is turned on, that is, enters the sixth stage Φ6; thereafter, The input current ip begins to decrease, and the voltage drop across the switch tube module 101 also drops thereupon. When the voltage drop across the switch tube module 101 drops to the lower limit of the set voltage drop range, the comparator module 102 generates an output signal to drive the logic And control circuit module 103 produces control signal, and this control signal will make the 5th PMOS transistor MP5 of active diode return to off state, promptly returns to the fifth stage Φ5, the turning off of the 5th PMOS transistor MP5 can increase active The on-resistance of the diode, so the voltage drop across the switch tube module 101 immediately rises within the set voltage drop range; the input current ip decreases again, and the voltage drop across the switch tube module 101 decreases as the input current decreases, When the voltage drop across the switching tube module 101 drops to the lower limit of the set voltage drop range again, the comparator module 102 will output a signal again and drive the logic and control unit module 103, and the control signal will make the fourth PMOS transistor MP4 return to In the off state, that is, returning to the fourth stage Φ4, the on-resistance of the switch tube module 101 increases immediately, and the voltage drop across the switch tube module 101 immediately rises to within the set voltage drop range; as the input current continues to decrease , the third PMOS transistor MP3 of the switch tube module 101 returns to the off state, that is, returns to the third stage Φ3, and the switch tube module The second PMOS transistor MP2 of 101 returns to the off state, that is, returns to the second stage Φ2, until all the PMOS transistors of the switching tube module 101 are turned off and returns to the off state of the active diodes, that is, the first stage Φ1. As the input current changes, the on-resistance of the active diode changes dynamically, that is, an active diode with adaptive on-resistance is formed.

In this embodiment, the first stage Φ1 corresponds to the input current range: 0-0.05*ip; the second stage Φ2 corresponds to the input current range: 0.05*ip-0.3*ip; the third stage Φ3 corresponds to the input current range: 0.3*ip -0.5*ip; the fourth stage Φ4 corresponds to the input current range: 0.5*ip-0.7*ip; the fifth stage Φ5 corresponds to the input current range: 0.7*ip-0.9*ip; the sixth stage Φ6 corresponds to the input current range: 0.9* ip-1*ip, where ip represents the maximum value of the input current range. Different input current ranges correspond to different working stages.

Referring to FIG. 7 , FIG. 7 is an explanatory diagram of the working states of the switching tubes corresponding to each stage of an active diode with adaptive on-resistance provided by an embodiment of the present invention. As shown in the figure, the first stage Φ1: the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are all off; the second stage Φ2: The first PMOS transistor MP1 is in the on state, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are all in the off state; the third stage Φ3: the first PMOS transistor MP1 and The second PMOS transistor MP2 is in the on state, the third PMOS transistor MP3, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are in the off state; the fourth stage Φ4: the first PMOS transistor MP1, the second PMOS transistor MP2 and the first PMOS transistor MP2 The three PMOS transistors MP3 are in the on state, the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are in the off state; the fifth stage Φ5: the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth The PMOS transistors MP4 are all in the on state, and the fifth PMOS transistor MP5 is in the off state; the sixth stage Φ6: the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS Transistors MP5 are all in the conduction state; in the stage of increasing input current, the voltage drop of the active diode rises with the increase of input current, once the voltage drop increases to the limited voltage drop upper limit, the first PMOS transistor MP1, the second The second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 will sequentially change from the off state to the on state, thereby reducing the on-resistance of the active diode and effectively reducing the active diode. The conduction voltage drop of the source diode; in the stage of reducing the input current, the voltage drop of the active diode decreases with the decrease of the input current, once the voltage drop drops to the lower limit value of the defined voltage drop, the first PMOS transistor MP1, the second The PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 will turn from the on state to the off state in turn, thereby increasing the on-resistance of the active diode and effectively improving the active diode. The detection accuracy of the zero-crossing point of the diode current increases the conduction resistance of the active diode, so that the conduction voltage drop of the active diode is maintained within a limited voltage drop range, which can ensure the conduction loss of the adaptive conduction resistance active diode Compared with the traditional active diode, the conduction loss is smaller, which indirectly broadens the input range of the rectification interface circuit, and helps to improve the rectification efficiency of the piezoelectric energy acquisition rectification interface circuit.

The above content is a further detailed description of the present invention in conjunction with preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (8)

1. An adaptive on-resistance active diode, comprising:

the device comprises a switch tube module (101), a comparator module (102) and a logic and control unit module (103); wherein,

the output end of the switch tube module (101) is electrically connected with the input end of the comparator module (102);

the output end of the comparator module (102) is electrically connected with the input end of the logic and control unit module (103);

the output end of the logic and control unit module (103) is electrically connected with the input end of the switch tube module (101).

2. The adaptive on-resistance active diode according to claim 1, wherein the switching transistor module (101) comprises a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), a fourth PMOS transistor (MP4), a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6), and a seventh PMOS transistor (MP 7); wherein,

a source of the first PMOS transistor (MP1) is electrically connected to a source of the second PMOS transistor (MP2), a source of the third PMOS transistor (MP3), a source of the fourth PMOS transistor (MP4), a source of the fifth PMOS transistor (MP5), a source of the sixth PMOS transistor (MP6), and a gate of the seventh PMOS transistor (MP7), respectively;

the drain of the first PMOS transistor (MP1) is electrically connected to the drain of the second PMOS transistor (MP2), the drain of the third PMOS transistor (MP3), the drain of the fourth PMOS transistor (MP4), the drain of the fifth PMOS transistor (MP5), the drain of the seventh PMOS transistor (MP7), and the gate of the sixth PMOS transistor (MP6), respectively;

the substrate of the first PMOS transistor (MP1) is electrically connected to the substrate of the second PMOS transistor (MP2), the substrate of the third PMOS transistor (MP3), the substrate of the fourth PMOS transistor (MP4), the substrate of the fifth PMOS transistor (MP5), the drain and substrate of the sixth PMOS transistor (MP6), and the source and substrate of the seventh PMOS transistor (MP7), respectively;

the gate of the first PMOS transistor (MP1), the gate of the second PMOS transistor (MP2), the gate of the third PMOS transistor (MP3), the gate of the fourth PMOS transistor (MP4) and the gate of the fifth PMOS transistor (MP5) are respectively and electrically connected with the output end of the logic and control unit module (103);

the source of the first PMOS transistor (MP1) is electrically connected to the positive input terminal of the comparator module (102) as the ANODE terminal (ANODE) of the switch tube module (101), and the drain of the first PMOS transistor (MP1) is electrically connected to the negative input terminal of the comparator module (102) as the CATHODE terminal (CATHODE) of the switch tube module (101).

3. The adaptive on-resistance active diode of claim 1, wherein the comparator module (102) comprises a first comparator (COMP1) and a second comparator (COMP 2); wherein,

a positive input end of the first comparator (COMP1) is electrically connected with an ANODE end (ANODE) of the switch tube module (101), a negative input end of the first comparator is electrically connected with a CATHODE end (CATHODE) of the switch tube module (101), and an output end of the first comparator is electrically connected with a first input end of the logic and control unit module (103);

the positive input end of the second comparator (COMP2) is electrically connected with the ANODE end (ANODE) of the switch tube module (101), the negative input end of the second comparator is electrically connected with the CATHODE end (CATHODE) of the switch tube module (101), and the output end of the second comparator is electrically connected with the second input end of the logic and control unit module (103).

4. The adaptive on-resistance active diode according to claim 1, wherein the logic and control unit module (103) comprises a clock signal logic circuit (I1), a counter (I2), a decoder (I3), a driving circuit module (I4); wherein:

the input end of the clock signal logic circuit (I1) is electrically connected with the output end of the comparator module (102); the input end of the counter (I2) is electrically connected with the output end of the clock signal logic circuit (I1); the input end of the decoder (I3) is electrically connected with the output end of the counter (I2); the input end of the driving circuit module (I4) is electrically connected with the output end of the decoder (I3), and the output end of the driving circuit module (I4) is electrically connected with the input end of the switch tube module (101).

5. The adaptive on-resistance active diode according to claim 4, wherein the clock signal logic circuit (I1) has a first input terminal (VO1) electrically connected to the first output terminal of the comparator block (102) and a second input terminal (VO2) electrically connected to the second output terminal of the comparator block (102).

6. The adaptive on-resistance active diode according to claim 4, wherein the clock signal input terminal (CLK2) of the counter (I2) is electrically connected to the clock signal output terminal (CLK1) of the clock signal logic circuit (I1), and the up-down count control terminal (V) of the counter (I2)_ADDSUB2) An up-down counting control output end (V) electrically connected with the clock signal logic circuit (I1)_ADDSUB1) The clear input end (RST2) of the counter (I2) is electrically connected with the clear output end (RST1) of the clock signal logic circuit (I1).

7. The adaptive on-resistance active diode of claim 4, wherein the counter (I2) is a 3-bit counter and the decoder (I3) is a 3_5 decoder; wherein a first output terminal (QA1) of the 3-bit counter is electrically connected to a first input terminal (QA2) of the 3_5 decoder; a second output end (QB1) of the 3-bit counter is electrically connected with a second input end (QB2) of the 3_5 decoder; and a third output end (QC1) of the 3-bit counter is electrically connected with a third input end (QC2) of the 3_5 decoder.

8. The adaptive on-resistance active diode according to claim 4, wherein the driving circuit module (I4) comprises a first driving circuit (D1), a second driving circuit (D2), a third driving circuit (D3), a fourth driving circuit (D4), a fifth driving circuit (D5); wherein, the input terminals of the first driving circuit (D1), the second driving circuit (D2), the third driving circuit (D3), the fourth driving circuit (D4) and the fifth driving circuit (D5) are electrically connected to 5 output terminals of the 3_5 decoder, respectively; the output ends of the first driving circuit (D1), the second driving circuit (D2), the third driving circuit (D3), the fourth driving circuit (D4) and the fifth driving circuit (D5) are respectively electrically connected with the input end of the switch tube module (101).