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CN107946288A - 具有静电放电防护的感测芯片封装及其制造方法 - Google Patents

具有静电放电防护的感测芯片封装及其制造方法 Download PDF

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CN107946288A
CN107946288A CN201710054721.4A CN201710054721A CN107946288A CN 107946288 A CN107946288 A CN 107946288A CN 201710054721 A CN201710054721 A CN 201710054721A CN 107946288 A CN107946288 A CN 107946288A
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chip
height
electrostatic discharge
input
package
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谢忠澔
林继周
和正平
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Sunasic Technologies Inc
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Sunasic Technologies Inc
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Abstract

本案涉及一种具有静电放电防护的感测芯片封装及其制造方法。该芯片封装包括一芯片与一基板。该芯片包括多个输入╱输出焊垫与多个静电放电保护焊垫，该基板包括多个输入╱输出接点与多个静电放电接点。每一输入╱输出焊垫经由一第一结合线连接到一对应的输入╱输出接点。每一静电放电保护焊垫经由一第二结合线连接到一对应的静电放电接点。连接静电放电保护焊垫与静电放电接点的结合线的顶点较连接输入╱输出焊垫与输入╱输出接点的结合线的顶点，更接近该芯片封装的上表面。因此，一种完美的静电放电防护效应可通过导引静电放电经由结合线到静电放电接点，而不是经由输入╱输出接点而达成。

Description

具有静电放电防护的感测芯片封装及其制造方法
技术领域
本发明关于一种芯片封装及制造该芯片封装的方法，特别是关于一种感测芯片封装，其具有强化静电放电(Electro-Static Discharge，ESD)防护能力，以及制造该感测芯片封装的方法。
背景技术
集成电路很容易受到静电放电损害，这种损害可能于制造过程中、运输中或不可操控的情况或使用环境下发生。许多静电放电标准，如人体放电模式(Human Body Model，HBM)、机器放电模式(Machine Model，MM)，及充电组件模式(Charged Device Model，CDM)，已被建立用来确认电子设备于制造过程中的性能与强健性。遵从上述静电放电标准的程序，如封装、运输、放置及焊接，都在该设备暴露于静电放电状况受到限制的环境中执行。这些标准确保了集成电路能于制成过程中免于静电放电损伤，并接着组装为一个系统。然而，现今系统中某些重要的改变增加了其中静电放电损害的可能性。制程的小型化与相应几何结构改变导致提供充足的在芯片防护非常困难，改变应用环境造成对更高的静电放电防护需求。举例来说，笔记本电脑、智能型手机、USB随身碟，以及其它的手持设备都使用于不可控制的环境中，而人们在该环境接触输入╱输出接脚及╱或感测组件(某些感测集成电路)。这些原因导致了额外系统层级的静电放电保护设计对裸露组件来说越来越重要。
一种用于裸露的感测集成电路(如指纹感测芯片)的常见应用技术说明于第1图中。一指纹感测芯片10设计上具有一静电放电保护结构接近上表面(如一静电放电格网)。至少一静电放电保护焊垫11连接到该静电放电保护结构且用于导通由静电放电来源，如手指，诱发的静电放电电流。静电放电保护焊垫将不会用来传输讯号以操作指纹感测芯片10。当指纹感测芯片10装设到一印刷电路板12上时，印刷电路板12上必须有一个对应的静电放电释放接点13。静电放电保护焊垫11由一结合线14连接到静电放电释放接点13。在所有焊垫都连接到对应的接点后，其间连接的所有的焊垫、接点与结合线都被一模制化合物15(封装到一系统中)所密封。这种技术很容易实现。如果一静电放电源(如人体手指)放置于指纹感测芯片10的表面，累积的电荷将经由静电放电保护结构被释放到印刷电路板12，进一步到外部环境、静电放电保护焊垫11、结合线14及静电放电释放接点13中。如果该静电放电源接触到大部分的密封区域，因不导电材料很厚，可以抵御导致绝缘击穿的电应力，封装的指纹感测芯片可免于静电放电危害。如果静电放电源接近输入╱输出结合线16弯弧的最高点，在该处模制化合物很薄，静电放电应力很高以致模制化合物中的电击穿可能会发生(类似避雷针的情况)，进一步让静电放电电流有机会经由输入╱输出焊垫17攻击指纹感测芯片。从而，输入╱输出结合线16弯弧最高点的四周区域易伤及封装指纹感测芯片静电放电的防护能力。
为了解决上述问题，已有多篇前案提出相关的解决之道。请参阅第2图。一种指纹传感器的封装及其方法揭露于美国专利第8,736,001号中。一指纹传感器30包括一基板35、安装于基板35上的一指纹感测芯片34，及耦接该基板35与指纹感测芯片34的结合线32。指纹感测芯片34包括一指纹感测区于上表面。指纹传感器30包括一封装层33封装该指纹感测芯片34并覆盖该指纹感测区。封装层33包括一凹陷部37，用于接收使用者的手指。封装层33也包括一周边凸缘部38于基板35之上并环绕该指纹感测芯片34与结合线32。指纹传感器30包括一表框31于封装层上。该表框31可耦接到电路以作为一驱动电极，提供驱动电压到用户的手指。指纹传感器30包括导电线路36于基板35之上，用以耦接该表框31。表框31可包括一金属或另一导电材料。在某些例子中，静电放电防护电路可耦接到表框31。表框31被固定在封装材料的最上表面(比结合线最高点的高度还高)，而该封装材料意味感测区域表面与表框的上表面间的高差受限于结合线32的环高，而结合线32在正常情形下约100μm。使用表框31可保护指纹感测芯片34，免于机械性及╱或电子性的破坏。然而，表框31造成指纹传感器30一个额外的厚度，从而不适合需要扁及╱或薄外观的产品，如芯片卡或智能型手机。指纹感测芯片34必须包括表框31，因而增加了成本且限制了指纹感测芯片34的外观。
另一个提供静电放电防护解决方案的前案显示于第3图，由美国专利公开号第2006/0071320号所揭露。一半导体设备50包括多个封装接脚51、一芯片52、多个第一结合焊垫53、多个第二结合焊垫54、多个第一结合线55，及多个第二结合线56。封装接脚51由一种导电材料所制造，进一步连接到外部电路。一半导体集成电路包括于芯片52中。该半导体集成电路最好包括一静电放电防护电路57与一输入╱输出电路58。该第一焊垫53与第二结合焊垫54两者皆为具有相同外观╱尺寸的电导通薄膜，且进一步为金属所制造。第一结合焊垫53与第二结合焊垫54形成于芯片52上，沿着芯片52周长具有固定间距。第一结合焊垫53形成于芯片52的周边部分，而第二结合焊垫54形成于周边部分之内。每一个第一结合焊垫53和某个第二结合焊垫54结成一对，保持着一个预订的距离。
第一结合线55直接连接第一结合焊垫53与封装接脚51，用来当作两者间的讯号线。第二结合线56直接连接第二结合焊垫54与封装接脚51，用来当作两者间的讯号线。第二结合线56具有较第一结合线55足够长的长度。较长的结合线通常具有较高的寄生电感。因此，第二结合线56能提供比第一结合线55足够高的寄生电感。因而，例如当一静电放电造成一超额浪涌电压于封装接脚51时，全部的浪涌电流主要经第一结合焊垫53流向静电放电防护电路57。从而，连接到第二结合焊垫54的输入╱输出电路58能可靠地受保护，免于静电放电所导致的故障与毁坏。虽然该美国专利公开号第2006/0071320号提供一种精巧的技术来利用结合线不同的寄生电感旁通静电放电，然而，该方法不适用于封装具有主动区及结合焊垫于同(上)侧的传感器。关于芯片52的上表面，第一结合线55相对低于第二结合线56。因此，第二结合线56表现像避雷针，而一静电放电源接近芯片52的上表面。静电放电具有较高的机会打击第二结合线56，输入╱输出电路58可能会受损。
目前仍没有合适的解决方案以解决上述静电放电防护问题。因此，亟待一种具有静电放电防护的芯片封装的创新设计。
发明内容
本段文字提取和编译本发明的某些特点。其它特点将被揭露于后续段落中。其目的在涵盖附加的权利要求之精神和范围中，各式的修改和类似的排列。
为了解决上述问题，本发明提出种具有静电放电防护的芯片封装。该芯片封装包括：一芯片，包括：一功能操作单元；多个输入╱输出焊垫，连接到该功能操作单元；及多个静电放电保护焊垫，连接到该功能操作单元，用以导引累积于该芯片的电荷到该芯片的外部环境；一基板，用以承载该芯片，该基板的一上侧包括：多个输入╱输出接点，每一输入╱输出接点经由一第一结合线连接到一对应的输入╱输出焊垫，其中第一结合线到该芯片的上表面的环高小于一第一高度；及多个静电放电保护接点，每一静电放电保护接点经由一第二结合线连接到一对应的静电放电保护焊垫，其中第二结合线到该芯片的上表面的环高小于一第二高度。该第一结合线的环高小于该第二结合线的环高。
该芯片封装最好进一步包括：一封装体，由一封装材料所制，覆盖至少一部分芯片、所述多个焊垫、所述多个结合线及一部分基板。该封装体的上表面到该芯片的上表面的一封装高度小于一第三高度。
依照本发明，该静电放电保护接点可进一步连接到一静电放电保护装置。该静电放电保护装置可为静电放电主动网或瞬时电压抑制器(Transient Voltage Suppressor，TVS)。该封装材料可为模制化合物。所有或部分的输入╱输出焊垫及静电放电保护焊垫可沿该芯片周边的一直线实质交错排列。所有或部分的输入╱输出焊垫亦可沿该芯片周边的一直线实质排列，且所述多个静电放电保护焊垫排列于所述多个输入╱输出焊垫四周。该芯片可为指纹感测芯片。该第一高度可介于30μm到60μm之间，该第二高度可介于第一高度与第三高度之间，该第三高度可介于70μm到110μm之间。
本发明还提供制造前述芯片封装的方法。该方法包括步骤：提供该基板；放置该芯片到该基板的上侧，将所述多个输入╱输出焊垫与静电放电保护焊垫面朝上；以打线接合连接方式连接每一输入╱输出焊垫到一对应的输入╱输出接点，其中该第一结合线到该芯片的上表面的环高小于该第一高度；及以打线接合连接方式连接每一静电放电保护焊垫到一对应的静电放电保护接点，其中该第二结合线到该芯片的上表面的环高小于该第二高度。该第一结合线的环高小于该第二结合线的环高。
该方法最好进一步包括步骤：以一模制化合物密封一部分芯片与结合线于该基板上以形成一封装体，及维持该封装体的上表面到该芯片的上表面的封装高度小于一第三高度。
由以上可以很明显看出连接静电放电保护焊垫与静电放电接点的结合线的顶点较连接输入╱输出焊垫与输入╱输出接点的结合线的顶点，更接近该芯片封装(作业区)的上表面。因此，一种完美的静电放电防护效应可通过导引静电放电经由结合线到静电放电接点，而不是经由输入╱输出接点而达成。
附图说明
第1图为用于指纹感测芯片静电放电防护的一种设计的示意图。
第2图显示用于指纹感测芯片静电放电防护的一种设计。
第3图显示用于芯片静电放电防护的另一种设计。
第4图为依照本发明的一种具有静电放电防护的芯片封装的示意图。
第5图为一指纹感测芯片的一上视图，包括一功能操作单元、输入╱输出焊垫与静电放电保护焊垫。
第6图为一种制造该芯片封装方法的流程图。
第7图为该指纹感测芯片的另一上视图，包括一功能操作单元、输入╱输出焊垫与静电放电保护焊垫。
第8图为本发明实施例提供的另一种具有静电放电防护的芯片封装的示意图。
主要组件符号说明
10 指纹感测芯片
11 静电放电保护焊垫
12 印刷电路板
13 静电放电释放接点
14 结合线
15 模制化合物
16 输入╱输出结合线
17 输入╱输出焊垫
30 指纹传感器
31 表框
32 结合线
33 封装层
34 指纹感测芯片
35 基板
36 导电线路
37 凹陷部
38 周边凸缘部
50 半导体设备
51 封装接脚
52 芯片
53 第一结合焊垫
54 第二结合焊垫
55 第一结合线
56 第二结合线
57 静电放电防护电路
58 输入╱输出电路
100 芯片
102 输入╱输出焊垫
104 静电放电保护焊垫
106 功能操作单元
110 第一结合线
120 基板
130 第二结合线
140 封装体
202 输入╱输出接点
204 静电放电保护接点
300 芯片
302 输入╱输出焊垫
304 静电放电保护焊垫
306 功能操作单元
h1 第一高度
h2 第二高度
h3 第三高度
具体实施方式
本发明将通过参照下列的实施方式而更具体地描述。
请参阅第4图到第6图，揭露依照本发明的一种具有静电放电防护的芯片封装的实施例。第4图为该芯片封装的示意图，第5图为一芯片100的一上视图，包括一功能操作单元106、输入╱输出焊垫102与静电放电保护焊垫104，第6图为制造该芯片封装方法的流程图。第4图与第5图相互对应。为了说明的目的，第4图与第5图中的每一组件的比例可能未如它们真实的状况。芯片封装主要包括一芯片100、一基板120及一封装体140。以上每一组件具有某些与现今使用的情形相异的特定设计特点。这些组件的功能及特点将说明如下。
本发明使用的芯片100具有一感测功能，一部分芯片100裸露到外部环境或具有非常薄的保护膜(其厚度小于20um)于前述裸露的部分。在本实施例中，芯片100是一个指纹感测芯片。在其它实施例中，它可能是个CMOS影像芯片。芯片100具有三种主要的子组件：一功能操作单元106、多个输入╱输出焊垫102及多个静电放电保护焊垫104。请同时参见第4图与第5图。第4图是第5图沿直线AA’的剖面。为了说明起见，输入╱输出焊垫102绘示成圆形而静电放电保护焊垫104绘示成长方形以资区别，虽然它们的真实外观可能既不是圆形也非长方形。功能操作单元106是芯片100提供其功能的主要部分。在本实施例中，它是个指纹感测区，由一数组的感测组件所组成。输入╱输出焊垫102连接到功能操作单元106，它们被用来从芯片100发出讯号到一外部电路中、接收来自该连接的外部电路之讯号，及提供来自一外部电源的电力给芯片100。静电放电保护焊垫104连接到功能操作单元106中的某些静电放电保护结构(未绘示)，如于芯片100的最上方金属层的一金属格网。它们用于导引累积于芯片100的电荷到芯片10的外部环境中，例如利用印刷电路板上的导线可进一步连接地。事实上，一般芯片的输入╱输出焊垫已设计有静电放电防护能力，能抵御2～4KV，这通常通过芯片内部的pMOS与nMOS及╱或连接某些二极管到输入╱输出焊垫而达成。此处所谓的静电放电保护焊垫104是另一种不用于讯号传输的型态。相反地，静电放电保护焊垫104仅用于保护芯片100以抵御静电放电损害。它可承受15KV或更高的静电放电电压。特别是该静电放电保护焊垫104可在芯片100运作时，而非在制造时执行功能，保护芯片100免于静电放电源由芯片100上侧进入输入╱输出焊垫102。静电放电脉冲将不会经由输入╱输出焊垫102伤害芯片100，但可经由连接到静电放电保护焊垫104的结合线排出芯片100。
基板120可承载芯片100。在一个实施例中，它可以是一个印刷电路板。基板120的一上侧具有多个输入╱输出接点202与多个静电放电保护接点204，每一输入╱输出接点202经由一第一结合线110连接到一对应的输入╱输出焊垫102，且每一静电放电保护接点204经由一第二结合线130连接到一对应的静电放电保护焊垫104。第一结合线110与第二结合线130两者都使用打线接合连接方式达成结合。一条结合线基本形成一个曲线状的侧视图，由一条结合线的最高点到芯片上表面的高度称为“环高”。第一结合线110的环高应受限而小于一第一高度。如第4图所示，对每一第一结合线110来说，环高显示为h1。从实验得知，第一高度最好介于30μm到60μm之间。相似地，第二结合线130的环高应该也受限且低于一第二高度但比第一高度高得多。如第4图所示，对每一第二结合线130来说，环高显示为h2。第二高度最好为65μm。静电放电保护接点204可进一步连接到装设于基板120上的一静电放电保护装置(未绘示)以有效旁通静电放电电流到基板120的一静电放电路径(未绘示)。一静电放电路径为用于导出静电放电电流以避免一基板上任何组件受静电放电电流损害而设计的一个电路。在一个实施例中，静电放电保护装置可以是一个静电放电主动网或一个瞬时电压抑制器(Transient Voltage Suppressor，TVS)。
封装体140由一种封装材料所制成，覆盖至少一部分芯片100(裸露功能操作单元106)、焊垫(输入╱输出焊垫102与静电放电保护焊垫104)、结合线(第一结合线110与第二结合线130)及至少一部分基板120。封装体140用来密封芯片100(除了本实施例中的功能操作单元106外；但于其它的实施例中，功能操作单元106也可密封到封装体140中)、基板120及所有的焊垫与结合线，以免于物理性的伤害或侵蚀。一封装高度，h3，从封装体140的上表面到芯片100的上表面应低于一第三高度，但比第二高度得多，用以提供足够厚度来保护结合线。第三高度应介于70μm到110μm之间。很清楚地，第二高度介于第一高度与第三高度之间。在一个实施例中，第二高度最好设为第一高度与第三高度的平均值。关于材料方面，封装材料最好是模制化合物。
依照本发明，输入╱输出焊垫102与静电放电保护焊垫104的排列是很重要的。一个输入╱输出焊垫102应邻近至少一个静电放电保护焊垫104。因此，任何遭遇的静电放电能由邻近的静电放电保护焊垫104，经由较高的第二结合线130而引导排出。排列的一种例子显示于第5图中。在芯片100的两侧(周边)，所有的输入╱输出焊垫102与静电放电保护焊垫104都沿一直线实质交错排列。如果芯片100的焊垫必须位于非常拥挤的空间内，输入╱输出焊垫102与静电放电保护焊垫104可能就不会有一对一的关系存在，部分输入╱输出焊垫102与静电放电保护焊垫104应如上所述地排列，越多越好。
请参阅第6图，第6图为一种制造该芯片封装方法的流程图，该方法具有以下的步骤。首先，提供基板120(S01)。接着放置该芯片100到基板120的上侧，将所述多个输入╱输出焊垫102与静电放电保护焊垫104面朝上(S02)。以打线接合连接方式连接每一输入╱输出焊垫102到一对应的输入╱输出接点202，第一结合线110到芯片100的上表面的环高小于该第一高度(S03)。接着，以打线接合连接方式连接每一静电放电保护焊垫104到一对应的静电放电保护接点204，第二结合线130到芯片100的上表面的环高小于该第二高度(S04)。然而，在一个实施例中，步骤S03与步骤S04的顺序是可以交换的，或可能，步骤S03与步骤S04同时进行，本发明并未限定。最后，以一模制化合物密封一部分芯片100与结合线于基板上120以形成一封装体140，及维持封装体140的上表面到芯片100的上表面的封装高度小于一第三高度(S05)。
在其它的实施例中，输入╱输出焊垫与静电放电保护焊垫的排列可能不同于前一实施例。请参阅第7图与第8图。另一个芯片300具有一功能操作单元306、输入╱输出焊垫302与静电放电保护焊垫304。很明显地，所有输入╱输出焊垫302实质沿芯片300底侧(周边)的一直线排列。同侧的静电放电保护焊垫304排列于输入╱输出焊垫302(并非所有输入╱输出焊垫302与静电放电保护焊垫304都沿相同的直线排列)四周。部分于上侧的输入╱输出焊垫302实质沿一直线排列，而其它的不是。静电放电保护焊垫304仍设计为于输入╱输出焊垫302四周排列。无论两侧使用哪一种排列方式，它们的应用都依照本发明。由第8图也很明显看出静电放电保护焊垫304结合线的环高比输入╱输出焊垫302结合线的环高来的高。这意味静电放电保护焊垫304的结合线能由排放任何静电放电脉冲而保护输入╱输出焊垫302，因为它更接近靠近芯片300表面的静电放电源。
虽然本发明已以实施方式揭露如上，然其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明之精神和范围内，当可作些许之更动与润饰，因此本发明之保护范围当视后附之申请专利范围所界定者为准。

Claims (16)

1.一种具有静电放电防护的芯片封装，包括：
一芯片，包括：
一功能操作单元；
多个输入╱输出焊垫，连接到该功能操作单元；及
多个静电放电保护焊垫，连接到该功能操作单元，用以导引累积于该芯片的电荷到该芯片的外部环境；
一基板，用以承载该芯片，该基板的一上侧包括：
多个输入╱输出接点，每一输入╱输出接点经由一第一结合线连接到一对应的输入╱输出焊垫，其中第一结合线到该芯片的上表面的环高小于一第一高度；及
多个静电放电保护接点，每一静电放电保护接点经由一第二结合线连接到一对应的静电放电保护焊垫，其中第二结合线到该芯片的上表面的环高小于一第二高度，
其中该第一结合线的环高小于该第二结合线的环高。
2.如权利要求1所述的芯片封装，进一步包括：
一封装体，由一封装材料所制，覆盖至少一部分芯片、所述多个焊垫、所述多个结合线及一部分基板，其中该封装体的上表面到该芯片的上表面的一封装高度小于一第三高度。
3.如权利要求1所述的芯片封装，其中该静电放电保护接点进一步连接到一静电放电保护装置。
4.如权利要求3所述的芯片封装，其中该静电放电保护装置为静电放电主动网或瞬时电压抑制器(Transient Voltage Suppressor，TVS)。
5.如权利要求2所述的芯片封装，其中该封装材料为模制化合物。
6.如权利要求1所述的芯片封装，其中所有或部分的输入╱输出焊垫及静电放电保护焊垫沿该芯片周边的一直线实质交错排列。
7.如权利要求1所述的芯片封装，其中所有或部分的输入╱输出焊垫沿该芯片周边的一直线实质排列，且所述多个静电放电保护焊垫排列于所述多个输入╱输出焊垫四周。
8.如权利要求1所述的芯片封装，其中该芯片为指纹感测芯片。
9.如权利要求1所述的芯片封装，其中该第一高度介于30μm到60μm之间。
10.如权利要求2所述的芯片封装，其中该第二高度介于第一高度与第三高度之间。
11.如权利要求2所述的芯片封装，其中该第三高度介于70μm到110μm之间。
12.一种用于制造如权利要求1所述的芯片封装的方法，包括步骤：
提供该基板；
放置该芯片到该基板的上侧，将所述多个输入╱输出焊垫与静电放电保护焊垫面朝上；
以打线接合连接方式连接每一输入╱输出焊垫到一对应的输入╱输出接点，其中该第一结合线到该芯片的上表面的环高小于该第一高度；及
以打线接合连接方式连接每一静电放电保护焊垫到一对应的静电放电保护接点，其中该第二结合线到该芯片的上表面的环高小于该第二高度，
其中该第一结合线的环高小于该第二结合线的环高。
13.如权利要求12所述的方法，进一步包括步骤：以一模制化合物密封一部分芯片与结合线于该基板上以形成一封装体，及维持该封装体的上表面到该芯片的上表面的封装高度小于一第三高度。
14.如权利要求12所述的方法，其中该第一高度介于30μm到60μm之间。
15.如权利要求13所述的方法，其中该第二高度介于第一高度与第三高度之间。
16.如权利要求13所述的方法，其中该第三高度介于70μm到110μm之间。
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