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CN107946256A - 半导体装置封装和其形成方法 - Google Patents

半导体装置封装和其形成方法 Download PDF

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Publication number
CN107946256A
CN107946256A CN201710325468.1A CN201710325468A CN107946256A CN 107946256 A CN107946256 A CN 107946256A CN 201710325468 A CN201710325468 A CN 201710325468A CN 107946256 A CN107946256 A CN 107946256A
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CN
China
Prior art keywords
conductive
conductive column
solder
pillar
semiconductor substrate
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Granted
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CN201710325468.1A
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CN107946256B (zh
Inventor
黄俊钦
叶勇谊
许哲铭
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN107946256A publication Critical patent/CN107946256A/zh
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Abstract

本发明提供一种准备好装配的半导体装置封装，所述半导体装置封装包含：半导体衬底；第一凸块下金属层，其安置于所述半导体衬底上；第一导电柱，其安置于所述第一凸块下金属层上；以及第二导电柱，其安置于所述第一导电柱上。所述第一导电柱的材料不同于所述第二导电柱的材料，且所述第二导电柱的所述材料包含抗氧化剂。

Description

半导体装置封装和其形成方法
技术领域
背景技术
为了允许更多组件集成到半导体芯片或半导体装置封装中，一个方法是采用倒装芯片结构。对于倒装芯片结构，第一晶圆经倒装，且借由导电凸块附接到第二晶圆上。焊料通常用以装配半导体装置封装。安置于第一晶圆的衬垫或铜柱上的焊料在附接到第二晶圆的另一衬垫或铜柱之前经回焊。衬底和组件可在回焊操作期间经受翘曲，这样可能损坏焊接点。此外，半球面状焊料凸块(其借由回焊操作得以形成)还可促成完整半导体装置封装的翘曲。此类现象可在封装的边缘处特别明显，其中翘曲更加强烈。翘曲可致使衬底弯曲、翘曲或开裂。因此，需要提供改善型半导体装置封装以解决上述问题。
发明内容
在一些实施例中，揭示一种准备好装配的半导体装置封装。所述半导体装置封装包括半导体衬底、第一凸块下金属(UBM)层、第一导电柱和第二导电柱。所述第一凸块下金属层安置于所述半导体衬底上。所述第一导电柱安置于所述第一凸块下金属层上。所述第二导电柱安置于所述第一导电柱上。所述第一导电柱的材料不同于所述第二导电柱的材料，且所述第二导电柱准备好被装配到外部装置。在一些实施例中，所述第二导电柱的所述材料包含抗氧化剂。
在一些实施例中，揭示一种半导体封装组合件。所述半导体封装组合件包括：第一半导体衬底、第一凸块下金属层、第一导电柱、第二导电柱、第二凸块下金属层、第三导电柱、第四导电柱、第二半导体衬底、第一导电垫和第二导电垫。所述第一凸块下金属层安置于所述第一半导体衬底上。所述第一导电柱安置于所述第一凸块下金属层上。所述第二导电柱安置于所述第一导电柱上，其中所述第一导电柱的材料不同于所述第二导电柱的材料。所述第二凸块下金属层安置于所述第一半导体衬底上。所述第三导电柱安置于所述第二凸块下金属层上。所述第四导电柱安置于所述第三导电柱上，其中所述第三导电柱的材料不同于所述第四导电柱的材料。所述第一导电垫安置于所述第二半导体衬底上，且所述第二导电柱接合到所述第一导电垫。所述第二导电垫安置于所述第二半导体衬底上，且所述第四导电柱接合到所述第二导电垫。所述第二导电柱的所述材料的体积不同于所述第四导电柱的所述材料的体积。
在一些实施例中，揭示一种形成准备好装配的半导体装置封装的方法。所述方法包括：在半导体衬底上形成第一凸块下金属凸块下金属层；在所述第一凸块下金属层上形成第一导电柱；以及在所述第一导电柱上形成第二导电柱。所述第一导电柱的材料不同于所述第二导电柱的材料，且所述第二导电柱准备好以第一导电垫进行装配。
附图说明
当结合附图阅读时，从以下具体实施方式最好地理解本发明的一些实施例的方面。应注意，各种特征可能未按比例绘制,且各种特征的尺寸可出于论述的清楚起见任意增大或减小。
图1是说明半导体封装组合件的横截面图。
图2是说明根据一些实施例的半导体装置封装的横截面图。
图3是说明根据一些实施例的半导体装置封装的一部分的横截面图。
图4是说明根据一些实施例的半导体封装组合件的横截面图。
图5是说明根据一些实施例的半导体封装组合件的一部分的装配工艺的横截面图。
图6是说明根据一些实施例的半导体封装组合件的一部分的装配工艺的横截面图。
图7A、图7B、图7C、图7D、图7E、图7F、图7G和图7H是根据本发明的一些实施例的在各阶段处所制造的半导体装置封装的一部分的横截面图。
具体实施方式
以下揭示内容提供用于实施所提供标的物的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例来阐释本发明的某些方面。当然，这些仅是实例且并不希望是限制性的。举例来说，在以下描述中，第一特征在第二特征的上方或上的形成可包含第一特征与第二特征直接接触地形成的实施例，且还可包含额外特征可形成于第一特征与第二特征之间使得第一特征与第二特征可以不直接接触的实施例。此外，本发明可在各种实例中重复参考数字和/或字母。此重复是出于简单和清楚的目的，且本身并不指示所论述的各种实施例和/或配置之间的关系。
下文详细论述本发明的一些实施例。然而，应了解，本发明提供可在广泛多种特定内容脉络中体现的许多适用的发明性概念。所论述的具体实施例仅仅是说明性的，且并不限制本发明的范围。
此外，例如“底下”、“下方”、“更低”、“上方”、“上部”、“更高”、“左”、“右”等空间相对术语可为易于描述而在本文中用以描述如图中所说明的一个元件或特征与另一元件或特征的关系。除图中所描绘的定向以外，与空间相关的术语意图涵盖在使用中的装置或操作的不同定向。装置可以其它方式定向(旋转90度或呈其它定向)，且本文中所使用的空间相对描述词同样地可相应地进行解释。将理解，当元件被称作“连接到”或“耦合到”到另一元件时，其可直接连接到或耦合到另一元件，或可存在介入元件。
图1是说明半导体封装组合件10的横截面图。半导体封装组合件10包括半导体装置封装12和半导体衬底14。半导体装置封装12经布置以经由多个导电凸块16和多个焊料18接合到半导体衬底14。在封装期间，回焊并翻转半导体装置封装12来将焊料18附接到半导体衬底14的导电垫20上。然而，在回焊操作期间，高温可引发半导体装置封装12的翘曲。半导体装置封装12的翘曲可在半导体装置封装12的边缘22处引起焊接点损坏的相对高风险。如图1中所展示，借由翘曲的半导体装置封装12的力拉动半导体装置封装12的边缘22处的焊料18。因此，半导体装置封装12的边缘22处的焊料18的形状变形成细长形状。细长形状在中间部分中具有相对小周界，且可具有凹面轮廓。此焊料18可具有接点故障的相对高风险，此係因为焊料18的中间部分可能是脆弱的。此外，焊料18的细长形状还可具有相对高阻抗，相对高阻抗可影响形成于半导体装置封装12中的集成电路的可靠性或信号完整性。焊料18的结合问题在半导体装置封装12相对大时恶化。在图1中，可在两个操作中执行半导体封装组合件10的形成。第一操作是回焊操作且第二操作是附接操作。在回焊操作期间，加热半导体装置封装12以熔化待附接到半导体衬底14的导电垫20的焊料18。高温引发半导体装置封装12的翘曲。在附接操作期间，焊料18对准并接着附接到半导体衬底14的导电垫20。当半导体装置封装12被装配到半导体衬底14时，半导体装置封装12的中间部分中且围绕所述中间部分的焊料18附接到对应导电垫20。然而，半导体装置封装12的边缘22处的焊料18可悬置于对应导电垫20上。可通过朝向半导体衬底14推动半导体装置封装12来将半导体装置封装12的边缘22处的焊料18附接到对应导电垫20。当焊料18附接到对应导电垫20时，焊料18可进一步影响半导体装置封装12的翘曲，这是因为焊料18的力可能不同。举例来说，半导体装置封装12的边缘22处的焊料18可借由拉力结合到对应导电垫20。围绕半导体装置封装12的中间的焊料18可在平衡力下结合到对应导电垫20。在半导体装置封装12的中间的焊料18可借由推力结合到对应导电垫20。因此，半导体封装组合件10在将半导体装置封装12附接到半导体衬底14之后具有最终翘曲。另外，如果半导体装置封装12的翘曲超出可接受阀值，那么半导体装置封装12的边缘22处的焊料18可仅接触对应导电垫20或保持为未附接于对应导电垫20上。
根据上述描述，回焊操作是半导体装置封装12中引发翘曲的主要原因。因此，提议并未经历回焊操作的半导体装置封装。半导体装置封装还在与半导体衬底结合方面具有相对高的可靠性。图2是说明根据一些实施例的半导体装置封装200的横截面图。半导体装置封装200准备好装配，而不经历回焊操作。更确切地说，半导体装置封装200准备好以包括上面形成的多个导电垫204的半导体衬底202进行装配。半导体衬底202可被视为半导体装置封装200的外部装置。根据一些实施例，半导体装置封装200和半导体衬底202是晶圆级装置。集成电路可形成于半导体装置封装200和半导体衬底202中的任一者或两者中。半导体装置封装200包括半导体衬底206和多个导电结构208。导电结构208安置于半导体衬底206上。在半导体装置封装200以半导体衬底202进行装配之前，半导体衬底206可具有晶圆翘曲。导电结构208经设计以具有自适应性或变化的高度以补偿半导体衬底206的翘曲，使得导电结构208可分别附接到导电垫204。根据一些实施例，导电结构208的顶部表面经设计以具有大体上相同的层面L1。根据一些实施例，假定半导体衬底202不具有明显翘曲，且导电垫204具有大体上相同的高度。因此，导电垫204的顶部表面经设计以具有大体上相同的层面L2。另外，对于导电结构208省略回焊操作，这是因为导电结构208经布置以准备好附接到半导体衬底202的对应导电垫204。常规上，可将半导体装置封装加热到约240℃到260℃的温度，以在回焊操作期间熔化焊接凸块，且半导体装置封装可由于高温而翘曲。在所说明实施例中，省略回焊操作，且因此可解决由于回焊操作造成的半导体装置封装200的翘曲问题。
另外，导电结构208的材料可包括均质掺杂有用以抑制氧化锡的形成的抗氧化剂的锡-银(SnAg)。根据一些实施例，导电结构208还可掺杂有表面活性剂、润湿剂、分散剂或前述各者中的两者或更多者的组合，以进一步减少氧化锡的形成。通过以此方式减少氧化锡的形成，可省略回焊操作。
根据一些实施例，导电结构208中的每一者经设计为具有预定高度且具有大体上平面端面的柱。因此，导电结构208的横截面形状可以是矩形或正方形状的，或可成其它规则或不规则形状。此外，导电结构208中的每一者包括第一导电柱210和第二导电柱212。第二导电柱212安置于第一导电柱210上。根据一些实施例，第一导电柱210与第二导电柱212由不同材料构成。举例来说，第一导电柱210是金属柱(例如铜柱)，且第二导电柱212是掺杂有抗氧化剂的焊料柱。此外，第一导电柱210的高度是大体上相同的。然而，第二导电柱212的高度取决于半导体衬底206的翘曲而变化。举例来说，半导体衬底206的边缘部分214上的第二导电柱212的高度大于半导体衬底206的中心部分216上的第二导电柱212的高度。这是因为通常边缘部分214比半导体衬底206的中心部分216具有更大的翘曲。应注意，可通过在制造工艺期间计算半导体衬底206的曲度来良好地控制第二导电柱212的高度。在一些实施例中，半导体衬底206的中心C具有最大曲度。然而，这不是本发明的限制。半导体衬底206可在除中心C以外的位置处具有最大曲度。
出于说明的目的，在图3中详细地描述半导体装置封装200的部分218。图3是说明根据一些实施例的半导体装置封装300的一部分(例如，图2中的部分218)的横截面图。半导体装置封装300包括半导体衬底302、第一凸块下金属(凸块下金属)层304、第一导电柱306、第二导电柱308、第二凸块下金属层310、第三导电柱312和第四导电柱314。第一凸块下金属层304安置于第一衬垫320上，第一衬垫320在半导体衬底302的第一位置上。第一导电柱306安置于第一凸块下金属层304上。第二导电柱308安置于第一导电柱306上。第二凸块下金属层310安置于第二衬垫322上，第二衬垫322在半导体衬底302的第二位置上。钝化层324安置于半导体衬底302上，且绝缘层326安置于如图3中所展示的钝化层324上。
第三导电柱312安置于第二凸块下金属层310上。第四导电柱314安置于第三导电柱312上。根据一些实施例，第一位置比第二位置更接近半导体衬底302的中心(例如，如图2中所展示的中心C)，其中中心具有最大曲度。因此，第一导电柱306与第二导电柱308的总高度H1大于第三导电柱312与第四导电柱314的总高度H2。确切地说，第一导电柱306与第三导电柱312具有大体上相同的高度H3，第二导电柱308的高度是H4，第四导电柱314的高度是H5，且H5大于H4。
另外，第一导电柱306、第二导电柱308、第一凸块下金属层304、第二凸块下金属层310、第三导电柱312与第四导电柱314经布置以具有大体上相同的周界。举例来说，第一导电柱306、第二导电柱308、第一凸块下金属层304、第二凸块下金属层310、第三导电柱312与第四导电柱314经设计为圆柱形的，其具有大体上相同的周界。第一导电柱306的橫向周边经布置以与第二导电柱308的橫向周边对准。第三导电柱312的橫向周边经布置以与第四导电柱314的橫向周边对准。因此，第一导电柱306、第二导电柱308、第一凸块下金属层304、第二凸块下金属层310、第三导电柱312与第四导电柱314具有如图3中所展示的大体上相同的宽度W。根据一些实施例，第二导电柱308的高度H4和/或第四导电柱314的高度H5可比宽度W大了至少约0.65倍。然而，这不是本发明的限制。第二导电柱308的高度H4和/或第四导电柱314的高度H5可小于宽度W的约0.65倍。确切地说，可通过在制造工艺期间控制第二导电柱308和第四导电柱314的焊料体积来适应性地调整高度H4和H5，以补偿半导体衬底302的翘曲。在一些实施例中，第四导电柱314的焊料体积大于第二导电柱308的焊料体积，且因此高度H5大于高度H4。举例来说，高度H5可比高度H4大了至少约1.15倍、至少约1.2倍或至少约1.3倍。
此外，第一导电柱306和第三导电柱312是铜柱，且第二导电柱308和第四导电柱314是掺杂有抗氧化剂元素或化合物的焊料柱。确切地说，如果焊料柱掺杂有抗氧化剂元素，那么抗氧化剂元素可抑制焊料柱的表面上的氧化锡(Sn02)或氧化锡的形成。根据一些实施例，还可分别在第二导电柱308和第四导电柱314的表面上形成第一氧化锡层316和第二氧化锡层318。然而，第一氧化锡层316和第二氧化锡层318的厚度相对小。举例来说，第一氧化锡层316和第二氧化锡层318的厚度可小于约10纳米(nm)，这在装配工艺期间是可容许的。这是因为可借由装配工艺轻易地移除第一氧化锡层316和第二氧化锡层318，且可省略回焊工艺。因此，即使第一氧化锡层316和第二氧化锡层318分别形成于第二导电柱308和第四导电柱314的表面上，但第二导电柱308和第四导电柱314仍符合半导体装置封装300的装配准则。
返回参看图2，在装配工艺期间，倒装半导体装置封装200且将其附接到半导体衬底202以形成半导体封装组合件。图4是说明根据一些实施例的半导体封装组合件400的横截面图。半导体封装组合件400包括第一半导体衬底402、多个铜柱404、多个焊料柱406、第二半导体衬底408和多个导电垫410。铜柱404安置于第一半导体衬底402上的多个凸块下金属层(未展示)上。焊料柱406分别安置于铜柱404上。导电垫410安置于第二半导体衬底408上。根据一些实施例，焊料柱406掺杂有抗氧化剂。铜柱404经布置以具有大体上相同的高度。焊料柱406经布置以具有不同高度以补偿第一半导体衬底402的翘曲。应注意，已在装配工艺期间移除焊料柱406的表面上的薄氧化锡层。因此，存在极少或不存在安置于半导体封装组合件400的焊料柱406与导电垫410之间的氧化锡层。在装配工艺之后，所有焊料柱406分别与导电垫410结合，且没有焊料柱406悬置于对应导电垫410上。另外，在第一半导体衬底402的边缘部分412处，焊料柱406的横截面形状(例如，矩形或)可保持大体上完整，而不具有凹面轮廓。因此，解决了非接触和焊料颈部件的问题。可通过第一半导体衬底402与第二半导体衬底408之间进行压缩来使第一半导体衬底402的中心部分414中的焊料柱406变形。然而，在一些实施例中，可通过良好地设计第一半导体衬底402的边缘部分412处的焊料柱406的高度来在平衡条件下保持变形焊料柱406的结合。
图5是说明根据一些实施例的半导体封装组合件502的一部分(例如，图4中的部分416)的装配工艺的横截面图。在图5的最左侧上，第一半导体衬底506的焊料柱504被倒装且与第二半导体衬底510的导电垫508对准。焊料柱504安置于铜柱512上，铜柱512安置于第一半导体衬底506上。在一些实施例中，铜柱512的直径(或宽度)D1(其大体上等于焊料柱504的直径)大于导电垫508的直径(或宽度)D2。焊料柱504经布置以具有第一高度h1，第一高度h1受焊料柱504的体积控制。接着，在装配工艺之后，焊料柱504与导电垫508结合。在焊料柱504附接到导电垫508之后，焊料柱504具有第二高度h2。第二高度h2可与第一高度h1相同或不同。当第一半导体衬底506与第二半导体衬底510之间的压力是拉力时，第二高度h2可大于第一高度h1，即，图5的第二最左侧上的状况。尽管第二高度h2大于第一高度h1，但焊料柱504的横截面形状大体上保持为矩形或正方形。焊料柱504不是细长的以形成焊料颈部件。另一方面，当第一半导体衬底506与第二半导体衬底510之间的压力是推力时，第二高度h2可小于第一高度h1，且焊料柱504的宽度可大于D1，即，图5的第二最右侧上的状况。另外，焊料柱504的宽度可由于由第一半导体衬底506和第二半导体衬底510的压缩引起变形而大于D1。然而，如果导电垫508的直径D2大于焊料柱504的直径D1，那么焊料柱504可在装配工艺之后由于导电垫508的表面张力而变形成梯形。在图5的最右侧中，在焊料柱504附接到导电垫508之后，焊料柱504的横截面形状变形成梯形。当第一半导体衬底506与第二半导体衬底510之间的压力是拉力时，第二高度h2可大于第一高度h1。尽管第二高度h2大于第一高度h1，但焊料柱504的横截面形状大体上保持为梯形。焊料柱504不是细长的以形成焊料颈部件。
根据一些实施例，导电垫508的直径D2可小于铜柱512的直径D1。图6是说明根据一些实施例的半导体封装组合件的一部分的装配工艺的横截面图。在图6的左侧上，第一半导体衬底604的焊料柱602被倒装且与第二半导体衬底608的导电垫606对准。焊料柱602安置于铜柱610上，铜柱610安置于第一半导体衬底604上。在一些实施例中，铜柱610的直径(或宽度)D1'(其大体上等于焊料柱602的直径)大于导电垫606的直径(或宽度)D2'。焊料柱602经布置以具有第一高度h1'，第一高度h1'受焊料柱602的体积控制。接着，在装配工艺之后，焊料柱602与导电垫606结合。在焊料柱602附接到导电垫606之后，焊料柱602具有第二高度h2'。第二高度h2'可与第一高度h1'相同或不同。因为铜柱610的直径D1'大于导电垫606的直径D2'，所以焊料柱602的横截面形状可由于如图6的中间中所展示的表面张力而变形成梯形。当第一半导体衬底604与第二半导体衬底608之间的压力是拉力时，第二高度h2'可大于第一高度h1'。尽管第二高度h2'大于第一高度h1'，但焊料柱602的横截面形状大体上保持为梯形。焊料柱602不是细长的以形成焊料颈部件。另一方面，当第一半导体衬底604与第二半导体衬底608之间的压力是推力时，第二高度h2'可小于第一高度h1'，且焊料柱602可囊封导电垫606的顶部部分，即，图6的右侧上的状况。另外，焊料柱602的最宽宽度可由于由第一半导体衬底604和第二半导体衬底608的压缩引起变形而大于D1'。
图7A到图7H是根据本发明的一些实施例的在各阶段处所制造的半导体装置封装的一部分的横截面图。
在图7A中，提供半导体衬底700。半导体衬底700包括衬底702、第一衬垫704、第二衬垫706、钝化层708、绝缘层710、第一凸块下金属层712和第二凸块下金属层714。第一凸块下金属层712和第二凸块下金属层714分别形成于第一衬垫704和第二衬垫706上。衬底702可包含若干裸片，所述裸片中的每一者具有有源装置和无缘装置。
在图7B中，在半导体衬底700上形成光刻胶图案716。通过使用光刻法来形成光刻胶图案716，光刻法涉及对光敏材料(例如光刻胶)的沉积。使用光来将图案从光罩幕转移到光刻胶。使用溶剂来移除光刻胶的经受光的一部分，从而暴露下层的待图案化的部分。移除光刻胶的剩余部分，从而留下图案化层，即，光刻胶图案716。形成分别暴露第一凸块下金属层712和第二凸块下金属层714的第一沟槽和第二沟槽。
在图7C中，将铜(Cu)沉积到第一沟槽和第二沟槽中，以分别形成第一铜柱718和第二铜柱720。在一些实施例中，第一铜柱718与第二铜柱720具有大体上相同的高度。
在图7D中，将光刻胶图案716形成为高于第一铜柱718和第二铜柱720，以形成第一沟槽722和第二沟槽724。
在图7E中，将镍(Ni)沉积到第一沟槽722和第二沟槽724中，以分别在第一铜柱718和第二铜柱720上形成第一镍层726和第二镍层728。
在图7F中，将光刻胶图案716形成为高于第一镍层726和第二镍层728，以形成第一沟槽730和第二沟槽732。在一些实施例中，第一沟槽730与第二沟槽732具有大体上相同的深度。然而，这不是本发明的限制。第一沟槽730与第二沟槽732可经设计以具有不同深度。
在图7G中，将焊料沉积到第一沟槽730和第二沟槽732中，以分别形成第一焊料柱734和第二焊料柱736。可借由电镀操作形成第一焊料柱734和第二焊料柱736。此外，在电镀操作期间，可将电流密度控制为相对小，且可执行相对更长沉积时间以形成良好的焊料顶盖。在电镀操作之后，可在焊料表面上形成相对薄SnO2层。然而，SnO2层的厚度小于约10nm，此符合装配准则且可在正常装配工艺期间易于移除。
在一些实施例中，第一焊料柱734与第二焊料柱736具有大体上相同的高度。然而，这不是本发明的限制。取决于半导体衬底700的翘曲，第一焊料柱734与第二焊料柱736可具有不同高度。
在图7H中，移除光刻胶图案716以暴露绝缘层710。因此，形成准备好装配的第一导电结构738(例如，第一导电凸块)和第二导电结构740(例如，第二导电凸块)，其中第一导电结构738包括第一铜柱718、第一镍层726和第一焊料柱734，且第二导电结构740包括第二铜柱720、第二镍层728和第二焊料柱736。具体来说，图7H的所得半导体装置封装可直接以外部衬底进行装配，而不用经历回焊工艺。因为在装配工艺之前不对第一焊料柱734和第二焊料柱736执行回焊工艺，所以第一焊料柱734和第二焊料柱736在附接到如图2中所展示的外部衬底的对应导电垫时保持为柱状。
应注意，上文所提及的半导体封装组合件是(C2S)芯片到衬底的组合件。然而，这不是本发明的限制。类似概念可应用于芯片到晶圆(C2W)、晶圆上晶圆(WoW)、裸片堆叠和内插件堆叠的组合件中。在此处为简洁起见省略详细描述。
简单来说，一些实施例的半导体装置封装提供多个柱状焊料以补偿半导体衬底的翘曲。柱状焊料的高度可由柱状焊料的焊料体积适当地控制。因此，解决了由半导体衬底的翘曲引起的结合问题。此外，柱状焊料掺杂有抗氧化剂以抑制氧化锡的形成。当在柱状焊料的表面上抑制氧化锡的形成时，柱状焊料准备好与另一半导体衬底上的对应导电垫结合，且可省略回焊操作。因此，简化了半导体装置封装的制造过程流程，并降低了半导体装置封装的成本。此外，当省略回焊操作时，可解决由于回焊操作的半导体装置封装的翘曲问题。
如本文所使用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可以包含多个提及物。
如本文中所使用，术语“大致”、“大体上”、“大体”和“约”用以描述并考虑小变化。当与事件或情形结合使用时，术语可以指其中事件或情形明确发生的例子以及其中事件或情形极近似于发生的例子。举例来说，当结合数值使用时，术语可指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，那么可认为所述两个数值“大体上”相同或相等。
另外，有时在本文中按范围格式呈现量、比率和其它数值。应理解，此类范围格式是用于便利和简洁起见，且应灵活地理解成不仅包含明确地指定为范围限制的数值，而且包含涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值和子范围一般。
前文概述若干实施例的特征使得所属领域的技术人员可以更好地理解本发明的各方面。所属领域的技术人员应了解，其可以易于使用本发明作为设计或修改用于进行本文中所介绍的实施例的相同目的和/或获得相同优势的其它工艺和结构的基础。所属领域的技术人员还应认识到，此类等效构造并不脱离本发明的精神和范围，且其可在不脱离本发明的精神和范围的情况下在本文中进行各种改变、替代和更改。

Claims (11)

1.一种准备好装配的半导体装置封装，其包括：
半导体衬底；
第一凸块下金属层，其安置于所述半导体衬底上；
第一导电柱，其安置于所述第一凸块下金属层上；以及
第二导电柱，其安置于所述第一导电柱上；
其中所述第一导电柱的材料不同于所述第二导电柱的材料，且所述第二导电柱的所述材料包含抗氧化剂。
2.根据权利要求1所述的半导体装置封装，其中所述第一导电柱是铜柱，且所述第二导电柱是包含所述抗氧化剂的焊料柱。
3.根据权利要求1所述的半导体装置封装，其中所述第一导电柱具有宽度，所述第二导电柱具有高度，且所述高度比所述宽度大了至少0.65倍。
4.根据权利要求1所述的半导体装置封装，其进一步包括：
第二凸块下金属层，其安置于所述半导体衬底上；
第三导电柱，其安置于所述第二凸块下金属层上；以及
第四导电柱，其安置于所述第三导电柱上；
其中所述第三导电柱的材料不同于所述第四导电柱的材料，且所述第四导电柱的所述材料包含所述抗氧化剂。
5.根据权利要求4所述的半导体装置封装，其中所述第一导电柱与所述第三导电柱具有大体上相同的高度，且所述第二导电柱与所述第四导电柱具有不同高度。
6.一种形成准备好装配的半导体装置封装的方法，所述方法包括：
在半导体衬底上形成第一凸块下金属层；
在所述第一凸块下金属层上形成第一导电柱；以及
在所述第一导电柱上形成第二导电柱；
其中所述第一导电柱的材料不同于所述第二导电柱的材料，且所述第二导电柱准备好以第一导电垫进行装配。
7.根据权利要求6所述的方法，其中在所述第一导电柱上形成所述第二导电柱包括：
在所述第二导电柱的所述材料中提供抗氧化剂。
8.根据权利要求6所述的方法，其中所述第一导电柱是铜柱，且所述第二导电柱是包含抗氧化剂的焊料柱。
9.根据权利要求6所述的方法，其中所述第一导电柱具有第一宽度，所述第二导电柱具有第二宽度，且所述第二宽度大体上等于所述第一宽度。
10.根据权利要求6所述的方法，其进一步包括：
在所述半导体衬底上形成第二凸块下金属层；
在所述第二凸块下金属层上形成第三导电柱；以及
在所述第三导电柱上形成第四导电柱；
其中所述第三导电柱的材料不同于所述第四导电柱的材料，且所述第四导电柱准备好以第二导电垫进行装配。
11.根据权利要求10所述的方法，其中所述第二导电柱比所述第四导电柱更接近所述半导体衬底的中心，且所述第四导电柱的高度大于所述第二导电柱的高度。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119346A (zh) * 2018-08-16 2019-01-01 嘉盛半导体(苏州)有限公司 晶圆级芯片的封装方法及结构
CN113823616A (zh) * 2020-06-18 2021-12-21 华邦电子股份有限公司 导电柱凸块及其制造方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016121631A1 (de) * 2016-11-11 2018-05-17 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip, Anschlussträger für die Montage eines Halbleiterchips, Verfahren zur Herstellung eines optoelektronischen Bauteils und optoelektronisches Bauteil
JP2019040924A (ja) * 2017-08-22 2019-03-14 新光電気工業株式会社 配線基板及びその製造方法と電子装置
US10818627B2 (en) * 2017-08-29 2020-10-27 Advanced Semiconductor Engineering, Inc. Electronic component including a conductive pillar and method of manufacturing the same
WO2019230250A1 (ja) * 2018-05-31 2019-12-05 株式会社ジャパンディスプレイ 表示装置及びアレイ基板
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US11887921B2 (en) * 2020-08-28 2024-01-30 Stmicroelectronics S.R.L. Method of producing semiconductor devices and corresponding semiconductor device
KR20220029232A (ko) 2020-09-01 2022-03-08 삼성전자주식회사 반도체 패키지 및 이를 포함하는 반도체 장치
US12261102B2 (en) * 2021-08-30 2025-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1532931A (zh) * 2003-03-24 2004-09-29 精工爱普生株式会社 半导体装置及制法、半导体封装、电子设备及制法、电子仪器
US20110108982A1 (en) * 2009-11-09 2011-05-12 Hynix Semiconductor Inc. Printed circuit board
CN102456660A (zh) * 2010-10-14 2012-05-16 三星电子株式会社 堆叠式半导体封装件及其制造方法和半导体器件
CN103367304A (zh) * 2013-07-19 2013-10-23 日月光半导体制造股份有限公司 封装基板、覆晶式封装及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7749340B2 (en) * 2005-10-24 2010-07-06 Indium Corporation Of America Technique for increasing the compliance of lead-free solders containing silver
US8841766B2 (en) * 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
JP6045774B2 (ja) 2010-03-16 2016-12-14 日立化成株式会社 半導体封止充てん用エポキシ樹脂組成物、半導体装置、及びその製造方法
US9425136B2 (en) * 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US8970035B2 (en) * 2012-08-31 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1532931A (zh) * 2003-03-24 2004-09-29 精工爱普生株式会社 半导体装置及制法、半导体封装、电子设备及制法、电子仪器
US20110108982A1 (en) * 2009-11-09 2011-05-12 Hynix Semiconductor Inc. Printed circuit board
CN102456660A (zh) * 2010-10-14 2012-05-16 三星电子株式会社 堆叠式半导体封装件及其制造方法和半导体器件
CN103367304A (zh) * 2013-07-19 2013-10-23 日月光半导体制造股份有限公司 封装基板、覆晶式封装及其制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119346A (zh) * 2018-08-16 2019-01-01 嘉盛半导体(苏州)有限公司 晶圆级芯片的封装方法及结构
CN109119346B (zh) * 2018-08-16 2021-07-23 嘉盛半导体(苏州)有限公司 晶圆级芯片的封装方法及结构
CN113823616A (zh) * 2020-06-18 2021-12-21 华邦电子股份有限公司 导电柱凸块及其制造方法

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