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CN107946253A - 采用模制中介层的晶圆级封装 - Google Patents

采用模制中介层的晶圆级封装 Download PDF

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Publication number
CN107946253A
CN107946253A CN201710002754.4A CN201710002754A CN107946253A CN 107946253 A CN107946253 A CN 107946253A CN 201710002754 A CN201710002754 A CN 201710002754A CN 107946253 A CN107946253 A CN 107946253A
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CN
China
Prior art keywords
molding
layer
intermediary
layer structure
redistribution layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710002754.4A
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English (en)
Inventor
施信益
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
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Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to CN202110410673.4A priority Critical patent/CN113140519A/zh
Publication of CN107946253A publication Critical patent/CN107946253A/zh
Pending legal-status Critical Current

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Abstract

本发明公开了一种模制中介层，包含：一第一模塑料层，具有一第一面及一相对于第一面的第二面；一第一重分布层结构，设在第一面上；一第二重分布层结构，设在第二面上；多个金属插塞，埋设在第一模塑料层中，以电连接第一重分布层结构与第二重分布层结构；以及一无源器件，埋设在第一模塑料层中。

Description

采用模制中介层的晶圆级封装
技术领域
本发明涉及半导体封装技术领域，特别是涉及一种采用模制中介层的晶圆级封装(wafer level package,WLP)，其中集成无源器件被埋设在模制中介层中。
背景技术
2.5D半导体封装，例如CoWoS(Chip-On-Wafer-On-Substrate)技术是本领域所已知的，CoWoS技术通常使用穿硅通孔(TSV)技术将多个芯片结合至单一装置中。
此架构提供了更高密度的互连、降低整体互连长度以及减轻相关的电阻电容负载，从而在更小的形状因子上提高性能及减少功耗。
由于有TSV的中介层衬底的工艺较为复杂，所以TSV硅中介层通常较昂贵。因此，对于某些应用可能不适合形成包括TSV中介层的WLP产品。
此外，2.5D半导体封装在TSV硅中介层上并排放置多个芯片。例如电容或电阻等无源器件可被设置在安装芯片的同一表面上。这种布置导致TSV中介层具有较大表面积。然而，实际应用上通常希望能缩减中介层的尺寸。
发明内容
本发明提供一种具有较小尺寸的模制中介层，以及使用此模制中介层的半导体封装。
本发明一方面，提出一种模制中介层，包含：一第一模塑料层，具有一第一面及一相对于第一面的第二面；一第一重分布层结构，设在第一面上；一第二重分布层结构，设在第二面上；多个金属插塞，埋设在第一模塑料层中，以电连接第一重分布层结构与第二重分布层结构；以及一无源器件，埋设在第一模塑料层中，其中无源器件经由多个连接件电连接第一重分布层结构。
本发明另一方面，提出一种半导体封装，包含上述的模制中介层以及至少一半导体芯片，设置在模制中介层的第一重分布层结构上。半导体芯片被一第二模塑料层模封包覆。第一模塑料层与第二模塑料层具有不同组成。
本发明另一方面，提出一种制造半导体封装的方法。首先，提供一第一载板；然后，在第一载板上形成一第一重分布层结构；再在第一重分布层结构上形成一模板层，接着在模板层中形成多个导孔；之后，分别在多个导孔中形成金属插塞；随后移除模板层；然后，在第一重分布层结构上设置一无源器件；再将无源器件与金属插塞模封包覆在一第一模塑料层中；接着抛光第一模塑料层，显露出金属插塞；之后，在第一模塑料层上形成一第二重分布层结构；随后，在第二重分布层结构上形成多个锡球；最后，在第一重分布层结构上设置一半导体芯片。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
附图包括对本发明的实施例提供进一步的理解，及被并入且构成说明书中的一部份。附图说明一些本发明的实施例，并与说明书一起用于解释其原理。
图1至图13是根据本发明的实施例所绘示的制造具有模制中介层的晶圆级封装的示例性方法。
图14至图20是根据本发明的另一实施例所绘示的制造具有模制中介层的晶圆级封装的示例性方法。
图21绘示包含虚设金属插塞的金属插塞，其具有比非虚设金属插塞更大的通孔直径。
其中，附图标记说明如下：
300 载板
310 钝化层
410 重分布层(RDL)结构
412 介电层
414 金属层
418 接触垫
419 接触垫
500 模板层
501 导孔
501a 虚设导孔
510 金属插塞
510a 虚设金属插塞
418a 虚设焊垫
602 区域
603 区域
612 无源器件
613 无源器件
614 连接件
615 连接件
550 模塑料
710 重分布层(RDL)结构
712 介电层
714 金属层
714a 虚设金属层
810 锡球
802 防焊层
100 模制中介层
11 半导体芯片
12 半导体芯片
101 晶圆级封装
560 模塑料
10 芯片封装
510’ 虚设金属插塞
具体实施方式
在下文中，加以陈述本发明的具体实施方式，所述具体实施方式可参考相对应的附图，使所述些附图构成实施方式的一部分。同时也借由说明，公开本发明可据以施行的方式。所述实施例已被清楚地描述足够的细节，使所述本领域技术人员可据以实施本发明。其他实施例亦可被加以施行，且对于其结构上所做的改变仍属本发明所涵盖的范畴。
因此，下文的细节描述将不被视为一种限定，且本发明所涵盖的范畴仅被权利要求书以及其同意义的涵盖范围。本发明的一或多个实施例将参照附图描述，其中，相同元件符号始终用以表示相同元件，且其中阐述的结构未必按比例所绘制。
术语“芯片”、“半导体芯片”及“半导体晶粒”在整个说明书中可互换使用。
文中所使用的术语“晶圆”及“衬底”包括任何具有暴露表面的结构，在所述表面上根据本发明沉积一层，例如，形成例如重分布层的电路结构。术语“衬底”被理解为包括半导体晶圆，但不限在此。术语“衬底”亦可用以指加工过程中的半导体结构，且可包括已被制造在其上的其它层。
请参考图1至图13。图1至图13是根据本发明的实施例所绘示的制造具有模制中介层的晶圆级封装的示例性方法。
如图1所示，首先，提供一载板300。载板300可为一可被撕除的基材。载板300可包含玻璃、硅、陶瓷、金属或任何合适的支撑材料。在载板300的上表面上提供至少一介电层或钝化层310。钝化层310可以包括例如聚亚酰胺(polyimide)的有机材料或例如氮化硅、氧化硅，或其类似物的无机材料，但不限于此。
随后，如图2所示，在钝化层310上形成一重分布层(RDL)结构410。RDL结构410用作前侧(或芯片侧)RDL中介层，其能够扇出半导体芯片上的输出/输入垫。RDL结构410可包含至少一介电层412以及至少一金属层414。
根据本发明一实施例，介电层412可包含例如聚亚酰胺(polyimide)等有机材料，或例如氮化硅、氧化硅，或其类似物等无机材料，但不限于此。
金属层414可包含铝、铜、钨、钛、氮化钛，或其类似物。根据所示实施例，金属层414可以包含多个细间距布线，接触垫418从介电层412的上表面显露出来，而接触垫419直接与钝化层310接触。
应理解的是，金属层414和接触垫418及419的层和布局仅用于说明的目的。根据设计要求，在其他实施例中，可以在RDL结构410中形成更多层的金属布线。
如图3所示，在RDL结构410上涂覆一模板层500。例如，模板层500可以是一光刻胶，例如，I-line光刻胶或定向自组装(DSA)材料，但不限于此。
如图4所示，在模板层500中形成导孔501。每个导孔501延伸通过模板层500的整个厚度。根据本发明一实施例，导孔501可暴露相对应的接触垫418用于进一步连接。根据本发明一实施例，导孔501可包含至少一虚设导孔501a。
为了形成导孔501，可以对包含例如光刻胶的模板层500进行光刻工艺，包括但不限于曝光工艺和显影工艺。
根据本发明一实施例，导孔501可具有相同的通孔直径或尺寸。根据本发明其他实施例，导孔501可具有不同的通孔直径。例如，虚设导孔501a可具有比其它非虚设导孔更大的通孔直径。
如图5所示，在形成导孔501之后，分别在导孔501中形成金属插塞510。根据本发明一实施例，导孔501被金属完全填满，金属例如铜、钨、铝、钛、氮化钛或其类似物，从而形成金属插塞510。金属插塞510可以借由沉积、网版印刷或任何合适的方法形成。
根据本发明一实施例，金属插塞510可包含形成在虚设导孔501a内的至少一虚设金属插塞510a，目的在消除应力或控制翘曲。至少一虚设导孔501a可以直接设置在虚设焊垫418a上。虚设焊垫418a是电隔离焊垫。集成电路封装在操作时，不会有讯号通过虚设焊垫418a和虚设金属插塞510a。
可选择性进行一化学机械抛光(CMP)工艺以去除导孔501外面的多余金属。根据本发明一实施例，金属插塞510可以具有与模板层500的厚度t一样的高度。
根据本发明一实施例，金属插塞510可以具有相同的直径或尺寸。根据本发明其他实施例，金属插塞510可以具有不同的直径。例如，虚设金属插塞510a可具有比其它非虚设金属插塞更大的直径。
根据本发明一实施例，金属插塞510可以用作前侧RDL结构和背侧RDL结构、散热件或应力调节件(虚拟金属插塞)之间的互连。
如图6所示，在形成金属插塞510之后，完全移除模板层500，留下完整的金属插塞510，其包含虚设金属插塞510a。例如，若模板层500含有光刻胶时，模板层500可以通过等离子蚀刻或灰化工艺去除。接触垫418被显露出来，且无源器件设置区域602及603被定义在金属插塞510之间。
如图7所示，无源器件612及无源器件613分别设置在无源器件设置区域602及603内显露出的接触垫418上。无源器件612可以经由连接件614电连接到接触垫418，而无源器件613可以经由连接件615电连接到接触垫418。
根据本发明一实施例，连接件614及615可包含锡凸块、铜凸块、微凸块或铜柱，但不限于此。根据本发明一实施例，无源器件612及613可以包含电容、电阻或电感，但是不限于此。根据本发明一实施例，无源器件612及613可以借由使用表面黏着技术(SMT)设置在接触垫418上。
如图8所示，形成一模塑料550，将金属插塞510、无源器件612及613及RDL结构410包覆起来。可对模塑料550进行一固化工艺。模塑料550可包含环氧树脂和硅填料的混合物，但不限于此。模塑料550的厚度比无源器件612及613的厚度厚。
如图9所示，进行一抛光工艺，移除模塑料550的上部，以暴露出金属插塞510的上表面。
如图10所示，在模塑料550及金属插塞510上形成一重分布层(RDL)结构710。RDL结构710用作背侧(或PCB侧)RDL中介层。RDL结构710可以包含至少一介电层712和至少一金属层714。
根据本发明一实施例，介电层712可包含例如聚亚酰胺(polyimide)等有机材料，或例如氮化硅、氧化硅，或其类似物等无机材料，但不限于此。
金属层714可包含铝、铜、钨、钛、氮化钛，或其类似物。根据所示实施例，金属层714可以包含多个布线，接触垫718从介电层712的上表面显露出来。可选择性在虚设金属插塞510a上形成虚设金属层714a。虚设金属层714a是电隔离的，且不会连接到金属层714的其它布线。
应理解的是，金属层714和接触垫718的层和布局仅用于说明的目的。根据设计要求，在其他实施例中，可以在RDL结构710中形成更多层的金属布线。
随后，在接触垫718上形成锡球810，例如球型格栅数组(ball grid array,BGA)锡球。应理解的是，防焊层802可以形成在RDL结构710上。在形成锡球810之前，可以在接触垫718上形成凸块下金属(UBM)层(未明确示于图中)。
如图11所示，在形成锡球810之后，移除钝化层310及载板300，从而暴露出RDL结构410的接触垫419，完成晶圆级模制中介层100。随后，将晶圆级模制中介层100接合至载板320，其中锡球810与载板320直接接触。可以在载板320上提供一黏着剂层(未明确示于图中)。载板320可包括玻璃、硅、陶瓷、金属或任何合适的支撑材料。
如图12所示，将半导体芯片11与半导体芯片12设置在RDL结构410上。半导体芯片11与半导体芯片12可为覆晶芯片。半导体芯片11与半导体芯片12通过接触垫419电连接至RDL结构410。半导体芯片11与半导体芯片12通过RDL结构410及金属插塞510电连接至RDL结构710。
随后，形成一模塑料560，将RDL结构410及半导体芯片11与半导体芯片12包覆起来，从而形成一晶圆级封装101。为了不影响模塑料550的性质，模塑料560的玻璃转化温度可以低于模塑料550的玻璃转化温度。
根据本发明一实施例，模塑料560可在较低的温度下固化，例如，低于模塑料550的玻璃转化温度的温度。根据本发明一实施例，模塑料550和模塑料560可具有不同的组成。在其他实施例中，可以省略模塑料560。
如图13所示，可进行一切割工艺，将晶圆级封装101切割成个别的芯片封装10。应理解的是，在其他实施例中，每个芯片封装10可仅包含一个芯片。
本发明的技术特征在于，无源器件612及613埋设在模制中介层100中并且由模塑料550模封。可以减小每个芯片封装10中的模制中介层的整体尺寸。
请参考图14至图20。图14至图20是根据本发明的另一实施例所绘示的制造具有模制中介层的晶圆级封装的示例性方法，其中，相同元件符号用以表示相同的层、区域或组件。
如图14所示，同样地先提供一载板300。接着，在钝化层310上形成一重分布层(RDL)结构410。RDL结构410用作前侧(或芯片侧)RDL中介层，其能够扇出半导体芯片上的输出/输入垫。RDL结构410可包含至少一介电层412以及至少一金属层414。
在RDL结构410上涂覆一模板层500。例如，模板层500可以是一光刻胶，例如，I-line光刻胶或定向自组装(DSA)材料，但不限于此。随后，在模板层500中形成导孔501。每个导孔501延伸通过模板层500的整个厚度。
根据本发明一实施例，导孔501可具有相同的通孔直径或尺寸。根据本发明其他实施例，导孔501可具有不同的通孔直径。根据本发明其他实施例，有些导孔501是虚设导孔。
如图15所示，在形成导孔501之后，分别在导孔501中形成金属插塞510。根据本发明一实施例，导孔501被金属完全填满，金属例如铜、钨、铝、钛、氮化钛或其类似物，从而形成金属插塞510。金属插塞510可以借由沉积、网版印刷或任何合适的方法形成。根据本发明其他实施例，有些金属插塞510是虚设金属插塞。
可选择性进行一化学机械抛光(CMP)工艺以去除导孔501外面的多余金属。根据本发明一实施例，金属插塞510可以具有与模板层500的厚度t一样的高度。
根据本发明其他实施例，金属插塞510可以具有不同的通孔直径，例如，如图21所示，金属插塞510可包含虚设金属插塞510’，其具有比其它非虚设金属插塞更大的通孔直径。
根据本发明一实施例，金属插塞510可以用作前侧RDL结构和背侧RDL结构、散热件或应力调节件(虚拟金属插塞)之间的互连。
如图16所示，在形成金属插塞510之后，完全移除模板层500，留下完整的金属插塞510。例如，当模板层500含有光刻胶时，模板层500可以通过等离子蚀刻或灰化工艺去除。
如图17所示，形成一模塑料550，将金属插塞510及RDL结构410包覆起来。可对模塑料550进行一固化工艺。模塑料550可包含环氧树脂和硅填料的混合物，但不限于此。然后，进行一抛光工艺，移除模塑料550的上部，以暴露出金属插塞510的上表面。
如图18所示，在模塑料550及金属插塞510上形成一重分布层(RDL)结构710。RDL结构710用作背侧(或PCB侧)RDL中介层。RDL结构710可以包含至少一介电层712和至少一金属层714。
根据本发明一实施例，介电层712可包含例如聚亚酰胺(polyimide)的有机材料，或例如氮化硅、氧化硅，或其类似物的无机材料，但不限于此。
金属层714可包含铝、铜、钨、钛、氮化钛，或其类似物。根据所示实施例，金属层714可以包含多个布线，接触垫718从介电层712的上表面显露出来。
应理解的是，金属层714和接触垫718的层和布局仅用于说明的目的。根据设计要求，在其他实施例中，可以在RDL结构710中形成更多层的金属布线。
随后，在接触垫718上形成锡球810，例如球型格栅数组(ball grid array,BGA)锡球。应理解的是，防焊层802可以形成在RDL结构710上。在形成锡球810之前，可以在接触垫718上形成凸块下金属(UBM)层(未明确示于图中)。
如图19所示，在形成锡球810之后，移除钝化层310及载板300，从而暴露出RDL结构410的接触垫419，完成晶圆级模制中介层100。随后，将晶圆级模制中介层100接合至载板320，其中锡球810与载板320直接接触。可以在载板320上提供一黏着剂层(未明确示于图中)，以将锡球810黏附至载板320。载板320可包括玻璃、硅、陶瓷、金属或任何合适的支撑材料。
如图20所示，将半导体芯片11与半导体芯片12设置在RDL结构410上。半导体芯片11与半导体芯片12可为覆晶芯片。半导体芯片11与半导体芯片12通过接触垫419电连接至RDL结构410。半导体芯片11与半导体芯片12通过RDL结构410及金属插塞510电连接至RDL结构710。
随后，形成一模塑料560，将RDL结构410及半导体芯片11与半导体芯片12包覆起来，从而形成一晶圆级封装。为了不影响模塑料550的性质，模塑料560的玻璃转化温度可以低于模塑料550的玻璃转化温度。
根据本发明一实施例，模塑料560可在较低的温度下固化，例如，低于模塑料550的玻璃转化温度的温度。根据本发明一实施例，模塑料550和模塑料560可具有不同的组成。在其他实施例中，可以省略模塑料560。然后，可进行一切割工艺，将晶圆级封装切割成个别的芯片封装10。应理解的是，在其他实施例中，每个芯片封装10可仅包含一个芯片。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (21)

1.一种模制中介层，其特征在于，包含：
一第一模塑料层，具有一第一面及一相对在所述第一面的第二面；
一第一重分布层结构，设在所述第一面上；
一第二重分布层结构，设在所述第二面上；
多个金属插塞，埋设在所述第一模塑料层中，以电连接所述第一重分布层结构与所述第二重分布层结构；以及
一无源器件，埋设在所述第一模塑料层中，其中所述无源器件经由多个连接件电连接所述第一重分布层结构。
2.根据权利要求1所述的模制中介层，其特征在于，所述多个金属插塞包含一虚设金属插塞。
3.根据权利要求1所述的模制中介层，其特征在于，多个连接件内埋在所述第一模塑料层中。
4.根据权利要求1所述的模制中介层，其特征在于，所述第一重分布层结构包含至少一第一介电层及至少一第一金属层。
5.根据权利要求4所述的模制中介层，其特征在于，所述第一介电层包含一有机材料或一无机材料。
6.根据权利要求5所述的模制中介层，其特征在于，所述有机材料包含聚亚酰胺。
7.根据权利要求5所述的模制中介层，其特征在于，所述无机材料包含氮化硅或氧化硅。
8.根据权利要求4所述的模制中介层，其特征在于，所述第一介电层直接接触所述第一模塑料层。
9.根据权利要求1所述的模制中介层，其特征在于，所述第二重分布层结构包含一第二介电层及一第二金属层。
10.根据权利要求9所述的模制中介层，其特征在于，另包含一防焊层，设在所述第二重分布层结构上。
11.根据权利要求9所述的模制中介层，其特征在于，另包含多个锡球，设在所述第二重分布层结构上。
12.根据权利要求1所述的模制中介层，其特征在于，所述第一模塑料层的厚度大于所述无源器件的厚度。
13.一种半导体封装，包含：
一如权利要求1所述的模制中介层；以及
至少一半导体芯片，设置在所述模制中介层的所述第一重分布层结构上。
14.根据权利要求13所述的半导体封装，其中所述半导体芯片被一第二模塑料层模封包覆。
15.根据权利要求13所述的半导体封装，其中所述第一模塑料层与所述第二模塑料层具有不同组成。
16.一种制造半导体封装的方法，包含：
提供一第一载板；
在所述第一载板上形成一第一重分布层结构；
在所述第一重分布层结构上形成一模板层；
在所述模板层中形成多个导孔；
分别在所述多个导孔中形成金属插塞；
移除所述模板层；
在所述第一重分布层结构上设置一无源器件；
将所述无源器件与所述些金属插塞模封包覆在一第一模塑料层中；
抛光所述第一模塑料层，显露出所述金属插塞；
在所述第一模塑料层上形成一第二重分布层结构；
在所述第二重分布层结构上形成多个锡球；以及
在所述第一重分布层结构上设置一半导体芯片。
17.根据权利要求16所述的制造半导体封装的方法，其特征在于，另包含：
将所述半导体芯片以一第二模塑料层模封包覆。
18.根据权利要求17所述的制造半导体封装的方法，其特征在于，另包含：
在一温度低于所述第一模塑料层的玻璃转化温度下，固化所述第二模塑料层。
19.根据权利要求17所述的制造半导体封装的方法，其特征在于，在所述第一重分布层结构上设置所述半导体芯片之前，且在所述第二重分布层结构上形成所述多个锡球之后，所述方法另包含：
移除所述第一载板，如此形成一晶圆级模制中介层；以及
将所述晶圆级模制中介层贴合至一第二载板，其中所述多个锡球直接接触所述第二载板。
20.根据权利要求16所述的制造半导体封装的方法，其特征在于，所述模板层是一光刻胶层。
21.根据权利要求17所述的制造半导体封装的方法，其特征在于，所述无源器件包含一电容、一电阻或一电感。
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CN111952274A (zh) * 2019-05-14 2020-11-17 矽品精密工业股份有限公司 电子封装件及其制法
CN111952274B (zh) * 2019-05-14 2022-05-24 矽品精密工业股份有限公司 电子封装件及其制法
CN111883438A (zh) * 2020-07-03 2020-11-03 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
CN111883437A (zh) * 2020-07-03 2020-11-03 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
CN112992807A (zh) * 2021-02-01 2021-06-18 日月光半导体制造股份有限公司 半导体结构及其制造方法

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