CN107919279B - Method for forming patterned structure - Google Patents

Abstract

The present invention discloses a method for forming a patterned structure, comprising the following steps. First, after forming a hard mask layer on a material layer, a first etching process and a second etching process are performed to form a first opening and a second opening partially overlapping each other in the hard mask layer. Using the hard mask layer having the first opening and the second opening, a third etching process is performed on the material layer, and after the third etching process, a fourth etching process is performed on the dielectric layer and the hard mask layer under the material layer. The material of the mask layer is the same as that of the dielectric layer, so the fourth etching process can be used to remove the hard mask layer and form a groove in the dielectric layer.

Description

Methods of forming patterned structures

technical field

The present invention relates to a method for forming a patterned structure, in particular to a method for forming a patterned structure using a multiple patterning photolithography technique.

Background technique

An integrated circuit (IC) is constructed by means of device devices and interconnection structures formed by patterned features formed on a substrate or in different film layers. In the manufacturing process of IC, photolithography is an indispensable technology, which mainly forms the designed pattern, such as circuit layout pattern, on one or more photomasks, and then passes the exposure The exposure and development steps transfer the pattern on the photomask to the photoresist layer on a film layer, so as to accurately transfer the complex layout pattern to the semiconductor chip.

With the development of miniaturization in the semiconductor industry and the advancement of semiconductor manufacturing technology, the existing exposure technology, which is a widely used technology, is gradually approaching its limit. Therefore, at present, the industry has also developed a double exposure lithography technique or a more heavy exposure lithography technique to produce a more miniaturized semiconductor element structure. However, when the multiple exposure photolithography process is performed, on the patterned object or/and material layer, some areas will be subjected to multiple exposure photolithography processes and some areas will only receive a single exposure Photolithography production process, so it is easy to cause differences in the conditions (such as etching depth) between different regions and cause problems such as poor uniformity, which may affect other subsequent semiconductor production processes or/and the operating conditions of the formed semiconductor elements. cause negative impact.

Contents of the invention

The invention provides a method for forming a patterned structure, which is used to form a hard mask layer on the material layer before performing a multiple patterning photolithography process on the material layer, so that the hard mask layer is first patterned. After etching, the material layer is etched using the patterned hard mask layer as a mask, thereby improving the situation that the etching depths of some regions are different due to multiple photolithography manufacturing processes. In addition, since the material of the hard mask layer is the same as that of the dielectric layer under the material layer, the hard mask layer can be removed when the dielectric layer is etched, thereby simplifying the manufacturing process.

According to an embodiment of the present invention, the present invention provides a method for forming a patterned structure, including the following steps. First, a dielectric layer and a material layer are sequentially formed on a substrate. Then, a hard mask layer is formed on the material layer, and the material of the hard mask layer is the same as that of the dielectric layer. A first patterned mask is formed on the hard mask layer, and a first etching process is performed using the first patterned mask to form at least one first opening in the hard mask layer, and the first opening is at least The layer of material is partially exposed. After the first etching process, the first patterned mask is removed, and a second patterned mask is formed on the hard mask layer, and a second etching process is performed using the second patterned mask, to form at least one second opening in the hard mask layer. The second opening at least partially exposes the material layer, and the first opening partially overlaps the second opening. Using the hard mask layer with the first opening and the second opening as a mask, a third etching process is performed on the material layer to remove the material layer exposed by the first opening and the second opening. After the third etching process, a fourth etching process is performed on the dielectric layer and the hard mask layer to remove the hard mask layer and form a trench in the dielectric layer.

Description of drawings

1 is a schematic diagram of a patterned structure according to a first embodiment of the present invention;

Fig. 2 is a schematic cross-sectional view along the section line A-A' in Fig. 1;

3 to 10 are schematic diagrams of a method for forming a patterned structure according to a second embodiment of the present invention, wherein

Fig. 4 is a schematic cross-sectional view drawn along the section line B-B' in Fig. 3;

Fig. 5 is a schematic diagram of the manufacturing method after Fig. 4;

Figure 6 and Figure 7 are schematic diagrams of the production method after Figure 5;

Fig. 7 is a schematic cross-sectional view drawn along the section line C-C' in Fig. 6;

Fig. 8 is a schematic diagram of the manufacturing method after Fig. 7;

Fig. 9 is a schematic diagram of the manufacturing method after Fig. 8;

FIG. 10 is a schematic diagram of the manufacturing method following FIG. 9 .

Description of main component symbols

10 bases

11 oxide layer

20 dielectric layer

30 barrier layer

30P patterned barrier layer

40 material layers

40P patterned material layer

50 hard mask layer

61 First organic distribution layer

62 First anti-reflection layer

63 First patterned mask

63H First mask opening

71 Second organic distribution layer

72 Second anti-reflection layer

73 Second Patterning Mask

73H second mask opening

91 The first etching process

92 Second etching process

93 The third etching process

94 The fourth etching process

D1 first direction

D2 second direction

D3 vertical direction

DP1 first depth

DP2 second depth

H1 first opening

H2 second opening

P patterned structure

PS Subpattern

R1 first zone

R2 second zone

R3 third zone

TR groove

TR1 first groove

TR2 second groove

TR3 third groove

Detailed ways

Please refer to Figure 1 and Figure 2. FIG. 1 is a schematic diagram of a patterned structure according to a first embodiment of the present invention, and FIG. 2 is a schematic cross-sectional view along the section line A-A' in FIG. 1 . As shown in FIGS. 1 and 2 , the patterned structure P includes a patterned material layer 40P and a patterned barrier layer 30P located below the patterned material layer 40P. The patterned material layer 40P can be formed by patterning a material layer 40 , and the patterned barrier layer 30P can be formed by patterning a barrier layer 30 . In some embodiments, the patterned material layer 40P includes a storage node pad structure of a memory device, therefore, the material layer 40 may include metal conductive materials such as tungsten (tungsten, W), aluminum (aluminum, Al) , copper (copper, Cu) or other suitable conductive materials, and the barrier layer 30 may include titanium (titanium, Ti), titanium nitride (titanium nitride, TiN), tantalum nitride (Tantalum nitride, TaN) or other Suitable barrier materials, but not limited thereto. In some embodiments, the patterned structure P and the patterned material layer 40P can also be other components in a semiconductor integrated circuit.

As shown in FIGS. 1 and 2 , the patterned structures P are arranged in an array along a first direction D1 and a second direction D2 substantially perpendicular to the first direction D1, in order to form on the substrate 10 The patterned structure P can firstly form a dielectric layer 20, a barrier layer 30 and a material layer 40 on the substrate 10, and then perform photolithography and etching processes on the barrier layer 30 and the material layer 40 to form a patterned structure P. The material layer 40P and the patterned barrier layer 30P. However, when the pattern design of the patterned structure P is too dense, limited by the manufacturing process capability of the photolithography manufacturing process (such as the exposure manufacturing process) and cannot be formed by a single photolithography manufacturing process, multi-pattern photolithography is required. The pattern design of the patterned structure P is realized by using a multiple patterning photolithography manufacturing process. For example, the interval between the sub-patterns PS in the patterned structure P can be regarded as composed of a plurality of first regions R1 extending along the first direction D1 and a plurality of second regions R2 extending along the second direction D2. The area formed by interlacing, and the first area R1 and the second area R2 intersect each other can be regarded as a third area R3. The material layer 40 and the barrier layer 30 of each first region R1 can be formed by a photolithography and etching process, and the material layer 40 and the barrier layer 30 of each second region R2 can be formed by another photolithography and etching process. form. However, since the etching effect on the dielectric layer 20 is also produced when the barrier layer 30 and the material layer 40 are etched, the dielectric layer 20 in the third region R3 is affected by the twice etching process, so The dielectric layer 20 in the third region R3 is etched to a depth (such as the second depth DP2 shown in FIG. The first depth DP1) shown in is even deeper. The difference in depth of different regions of the dielectric layer 20 may have a negative impact on other subsequent manufacturing processes and/or the operation of the formed semiconductor device.

Please refer to Figure 1 and Figures 3 to 10. 3 to 10 are schematic diagrams of a method for forming a patterned structure according to a second embodiment of the present invention. Through the manufacturing method of this embodiment, the above-mentioned problems in the first embodiment can be improved. This embodiment provides a method for forming a patterned structure, including the following steps. First, as shown in FIG. 3 and FIG. 4 , a dielectric layer 20 and a material layer 40 are sequentially formed on a substrate 10, and a hard mask layer 50 is formed on the material layer 40, and the material of the hard mask layer 50 is the same as The material of the dielectric layer 20 is the same. For example, the materials of the hard mask layer 50 and the dielectric layer 20 may include silicon nitride or other suitable dielectric materials. In addition, the substrate 10 may include a semiconductor substrate or a non-semiconductor substrate, and the semiconductor substrate may include, for example, a silicon substrate, a silicon-germanium semiconductor substrate, or a silicon-on-insulator (SOI) substrate, etc., and the non-semiconductor substrate may include a glass substrate, Plastic substrate or ceramic substrate, etc., but not limited thereto. For example, when the substrate 10 includes a semiconductor substrate, a plurality of memory cells and/or transistor elements (not shown) may also be formed on the semiconductor substrate as required, or an oxide layer may also be formed first 11. Forming a dielectric layer 20 again, but not limited thereto. In addition, a barrier layer 30 may be formed between the material layer 40 and the dielectric layer 20 as required.

Next, a first patterned mask 63 is formed on the hard mask layer 50 , and a first etching process 91 is performed using the first patterned mask 63 . In some embodiments, a first organic distribution layer (ODL) 61 and a first resist may be sequentially formed on the hard mask layer 50 before the first patterned mask 63 is formed. The reflective layer 62 (for example, silicon-containing hard mask bottom anti-reflecting coating, SHB), but not limited thereto.

As shown in FIGS. 3 to 5 , the first patterned mask 63 may include a plurality of first mask openings 63H, and each first mask opening 63H extends along the first direction D1. Therefore, using the first patterned mask 63 to perform the first etching process 91 can form at least one first opening H1 in the hard mask layer 50, the first opening H1 at least partially exposes the material layer 40, and the first opening H1 The shape of substantially corresponds to the shape of the first mask opening 63H in the vertical direction D3, so the first opening H1 also extends along the first direction D1. In addition, in some embodiments, when the first etching process 91 is performed on the hard mask layer 50 , the material layer 40 exposed by the first opening H1 may also be slightly etched, but the present invention is not limited thereto.

As shown in FIGS. 4-5 , after the first etching process 91 , the first patterned mask 63 , the first anti-reflection layer 62 and the first organic distribution layer 61 are removed. As shown in FIGS. 6 to 8 , a second patterned mask 73 is formed on the etched hard mask layer 50 , and a second etching process 92 is performed using the second patterned mask 73 . Similarly, in some embodiments, a second organic distribution layer 71 and a second anti-reflection layer 72 may be sequentially formed on the hard mask layer 50 before the second patterned mask 73 is formed. , but not limited to this. The second patterned mask 73 may include a plurality of second mask openings 73H, and each second mask opening 73H extends along the second direction D2. Therefore, performing the second etching process 92 using the second patterned mask 73 can form at least one second opening H2 in the hard mask layer 50, the second opening H2 at least partially exposes the material layer 40, and the second opening H2 The shape of substantially corresponds to the shape of the second mask opening 73H in the vertical direction D3, so the second opening H2 also extends along the second direction D2, and the first opening H1 and the second opening H2 intersect and partially overlap each other.

In some embodiments, the above-mentioned first etching process and second etching process 92 may include anisotropic (anisotropic) etching process such as dry etching process for better critical dimension (Critical Dimension, CD ) control capability, but not limited thereto. In addition, when the second etching process 92 is performed on the hard mask layer 50, the material layer 40 exposed by the second opening H2 may also be slightly etched, and in this case, the first opening H1 overlaps the second opening H2 The corresponding material layer 40 is etched deeper than the material layer 40 in other regions, but the barrier layer 30 below the material layer 40 will not be exposed. In other words, after the second etching process 92 and before the subsequent third etching process 93 , the barrier layer 30 is completely covered by the material layer 40 without being exposed. In addition, after the second etching process 92 , the second patterned mask 73 , the second anti-reflection layer 72 and the second organic distribution layer 71 are removed.

Next, as shown in FIGS. 8 to 9 , using the hard mask layer 50 having the first opening H1 and the second opening H2 as a mask, a third etching process 93 is performed on the material layer 40 to remove the first The material layer 40 exposed by the opening H1 and the second opening H2. It is worth noting that the third etching process 93 has a higher etching selectivity ratio between the material layer 40 and the barrier layer 30, that is to say, the etching rate of the third etching process 93 for the material layer 40 should be much higher than that for the material layer 40. The etching rate of the barrier layer 30 can make the third etching process 93 stop at the barrier layer 30 without etching the dielectric layer 20 below the barrier layer 30 . In other words, before and after the third etching process 93 is performed, the dielectric layer 20 is covered by the barrier layer 30 without being exposed. In addition, after the third etching process 93 , part of the barrier layer 30 is exposed outside the material layer 40 to ensure that the material layer 40 is effectively etched into the desired shape.

After that, as shown in FIGS. 9 to 10 , after the third etching process, a fourth etching process 94 is performed to remove the barrier layer 30 not covered by the material layer 40 and the hard mask layer 50 . In order to ensure that the portion of the barrier layer 30 to be etched is effectively removed by the fourth etching process 94, the fourth etching process 94 also etches a portion of the dielectric layer 20 to form a trench in the dielectric layer 20 TR. In addition, in this embodiment, the fourth etching process 94 can also be used to remove the hard mask layer 50, so the fourth etching process 94 can be regarded as a process for the barrier layer 30, the dielectric layer 20 and the hard mask The mold layer 50 is etched. The fourth etching process 94 preferably has a better etching selectivity ratio between the dielectric layer 20 and the material layer 40, that is to say, the fourth etching process 94 has a better etching selectivity for the dielectric layer 20 and the hard mask layer 50. The etch rate should be greater than the etch rate for the material layer 40 , thereby avoiding excessive etching of the material layer 40 by the fourth etching process 94 after removing the hard mask layer 50 . In some embodiments, the above-mentioned third etching process and fourth etching process 94 may preferably include an anisotropic etching process such as a dry etching process for better critical dimension control, but not Not limited to this. In addition, since the hard mask layer 50 is made of the same material as the dielectric layer 20, part of the barrier layer 30 can be removed through the fourth etching process 94 and removed when the trench TR is formed in the dielectric layer 20. The hard mask layer 50 thus achieves the effect of simplifying the manufacturing process.

As shown in FIGS. 8 to 10 , after the third etching process 93 and before the fourth etching process 94, the dielectric layer 20 is covered by the barrier layer 30 without being exposed, while the hard mask layer 50 is still covered. part of the material layer 40 . After the third etching process 93 , part of the barrier layer 30 is exposed outside the material layer 40 , and the barrier layer 30 exposed by the material layer 40 is removed in the fourth etching process 94 . The material layer 40 and the barrier layer 30 are patterned by the third etching process 93 and the fourth etching process 94 to become the patterned material layer 40P and the patterned barrier layer 30P respectively. In some embodiments, the patterned material layer 40P may include a storage node pad structure of a memory device, but is not limited thereto.

It is worth noting that after the third etching process 93 and before the fourth etching process 94, although the depth of the barrier layer 30 corresponding to the overlap of the first opening H1 and the second opening H2 may be etched deeper than that of other regions The barrier layer 30 is etched deeper, but the thickness of the barrier layer 30 can be used to be smaller than the thickness of the material layer 40 and the thickness of the dielectric layer 20, so that after the fourth etching process 94, the second The etched depth of the dielectric layer 20 corresponding to the overlapping portion of the first opening H1 and the second opening H2 is not significantly different from the etched depth of the dielectric layer 20 in other regions. For example, the thickness of the barrier layer 30 may be about 50 angstrom, the thickness of the material layer 40 may be about 500 angstrom, and the thickness of the dielectric layer 20 may be about 800 angstrom, but not limited thereto.

In other words, if the part of the substrate 10 corresponding to the first opening H1 is defined as the first region R1, the part of the substrate 10 corresponding to the second opening H2 is defined as the second region R2, and the first region R1 and the second region R1 are defined as The overlap of the two regions R2 is defined as the third region R3, and the trench TR is formed in the first region R1, the second region R2 and the third region R3, and the trench TR located in the third region R3 (such as shown in FIG. 10 The depth of the third trench TR3 shown) (such as the second depth DP2 shown in FIG. 10) will be substantially equal to the trench TR of the first region R1 or/and the second region R2 outside the third region R3. (eg, the first trench TR1 and/or the second trench TR2 shown in FIG. 10 ) (eg, the first depth DP1 shown in FIG. 10 ). Through the method for forming a patterned structure in this embodiment, the depths of the trenches TR in the dielectric layer 20 in the first region R1 , the second region R2 and the third region R3 can be made uniform. In addition, by controlling the thickness of the hard mask layer 50 so that the thickness of the hard mask layer 50 after the third etching process 93 and before the fourth etching process 94 is smaller than the thickness of the dielectric layer 20, it can ensure the fourth The etching process 94 can completely remove the hard mask layer 50 and make the trench TR not penetrate through the dielectric layer 20 , thus helping to improve the process window of the fourth etching process 94 . In addition, since the trench depths in different regions of the dielectric layer 20 do not have significant differences, it is possible to avoid negative effects on other subsequent manufacturing processes or/and the operation conditions of the formed semiconductor elements due to differences in trench depths. influences.

To sum up, in the method for forming a patterned structure of the present invention, a hard mask layer is formed on the material layer prior to performing a multiple patterning photolithography process, so that the hard mask layer is first covered. After patterning, the material layer is etched using the patterned hard mask layer as a mask, thereby improving the difference in etching depth between partial regions that may be caused by multiple photolithography manufacturing processes. In addition, the material of the hard mask layer of the present invention is the same as that of the dielectric layer under the material layer, so the hard mask layer can be removed when the dielectric layer is etched, thereby achieving the simplification of the manufacturing process. Effect.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (9)

1. A method of forming a patterned structure, comprising: sequentially forming a dielectric layer and a material layer on a substrate; forming a hard mask layer on the material layer, wherein the material of the hard mask layer is the same as that of the dielectric layer; A first patterned mask is formed on the hard mask layer, and a first etching process is performed using the first patterned mask to form at least one first opening in the hard mask layer, wherein the the first opening at least partially exposes the material layer; After the first etching process, remove the first patterned mask, and form a second patterned mask on the hard mask layer, and use the second patterned mask to perform a second an etching process to form at least one second opening in the hard mask layer, wherein the second opening at least partially exposes the material layer, and the first opening partially overlaps the second opening; Using the hard mask layer having the first opening and the second opening as a mask, performing a third etching process on the material layer to remove the exposed portion of the first opening and the second opening material layers; and After the third etching process, a fourth etching process is performed on the dielectric layer and the hard mask layer to remove the hard mask layer and form a trench in the dielectric layer, The method further includes forming a barrier layer between the material layer and the dielectric layer, wherein after the third etching process and before the fourth etching process, the dielectric layer is blocked by the barrier layer Covering, wherein the thickness of the barrier layer is less than the thickness of the material layer. 2. The method for forming a patterned structure according to claim 1, wherein after the third etching process, part of the barrier layer is exposed outside the material layer, and the barrier layer exposed by the material layer Layers are removed in the fourth etch process. 3. The method for forming a patterned structure as claimed in claim 1, wherein after the second etching process and before the third etching process, the barrier layer is completely covered by the material layer. 4. The method for forming a patterned structure as claimed in claim 1, wherein the hard mask layer covers part of the material layer after the third etching process and before the fourth etching process. 5. The method for forming a patterned structure according to claim 1, wherein the base of the part corresponding to the first opening is defined as a first region, and the part of the base corresponding to the second opening is defined as a second region , the overlap between the first area and the second area is defined as a third area, the groove is formed in the first area, the second area and the third area, and the depth of the groove located in the third area equal to the depth of the trench in the first zone or the second zone outside the third zone. 6. The method for forming a patterned structure according to claim 1, wherein the first opening extends along a first direction, the second opening extends along a second direction, and the first direction is perpendicular to the second direction pay. 7. The method for forming a patterned structure as claimed in claim 1, wherein the material layer is patterned by the third etching process and the fourth etching process to form a patterned material layer, and the patterned material layer A storage node pad structure including a memory device. 8. The method for forming a patterned structure as claimed in claim 1, wherein materials of the hard mask layer and the dielectric layer comprise silicon nitride. 9. The method for forming a patterned structure as claimed in claim 1, wherein the trench does not penetrate through the dielectric layer.