CN107911110A - level shift circuit based on input control diode - Google Patents
level shift circuit based on input control diode Download PDFInfo
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- H—ELECTRICITY
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- H—ELECTRICITY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
Description
技术领域technical field
本发明涉及模拟集成电路设计领域，特别复杂的SOC设备领域。具体讲,涉及基于输入控制二极管的电平移位电路。The invention relates to the field of analog integrated circuit design, especially the field of complex SOC equipment. Specifically, it relates to a level-shifting circuit based on an input-controlled diode.
背景技术Background technique
在无线传感器网络，随着微型保健设备和环境监测系统等领域应用的片上系统(systems on chips，SOCs)变得越来越复杂，整个系统若均采用高压电路则功耗过大，而采用低压电路的速度又很难满足性能要求。最好的解决办法是在不同模块提供不同电压，高速电路提供高压，低速电路提供低压即可。因此电平移位(level shifter，LS)电路的提出具有重要意义。In wireless sensor networks, as the systems on chips (SOCs) used in the fields of micro-health care equipment and environmental monitoring systems become more and more complex, if the entire system uses high-voltage circuits, the power consumption will be too large, and low-voltage circuits will consume too much power. The speed of the circuit is difficult to meet the performance requirements. The best solution is to provide different voltages in different modules, the high-speed circuit provides high voltage, and the low-speed circuit provides low voltage. Therefore, it is of great significance to propose a level shifter (level shifter, LS) circuit.
目前有两种主流电平移位电路结构：交叉耦合结构和电流镜结构。图1所示的是基于交叉耦合结构的电平移位电路结构。在这种机构中，低电平信号VDDL以及MN1、MN2之间的反相器使节点Q和Qb电压不平衡，而交叉耦合PMOS器件则再次增加Q与Qb之间的差值达到VDDH。该结构的缺点在于，当VDDL较小时，MN1、MN2的栅极电压过小，电平移位则较难实现。这种问题已经通过增大NMOS的尺寸得到解决，但是会引起功耗大、延迟大等问题。There are currently two mainstream level-shifting circuit structures: cross-coupling and current mirror structures. Figure 1 shows the level shifting circuit structure based on the cross-coupling structure. In this mechanism, the low-level signal V DDL and the inverter between MN1, MN2 unbalance the node Q and Qb voltages, while the cross-coupled PMOS device again increases the difference between Q and Qb to V DDH . The disadvantage of this structure is that when V DDL is small, the gate voltages of MN1 and MN2 are too small, and level shifting is difficult to implement. This problem has been solved by increasing the size of the NMOS, but it will cause problems such as large power consumption and large delay.
图2所示的是基于电流镜结构的电平移位电路结构。这种结构具有输入电压低、速度快、面积小等优点。这种结构中的上拉部分和下拉部分几乎没有重叠，但MN1和MP2的静电流将会增加待机功率。Figure 2 shows the level shift circuit structure based on the current mirror structure. This structure has the advantages of low input voltage, high speed, and small area. The pull-up and pull-down parts in this structure have little overlap, but the static current of MN1 and MP2 will increase the standby power.
基于电流镜的结构中，威尔逊电流镜结构的电平移位电路(Wilson currentmirror based level shifter，WCMLS)是较为优秀的一种结构。图3所示为WCMLS结构图，它使用反馈晶体管MP3来关断切换后流过MN1和MP1的静态电流，可有效降低电平移位电路的待机功率。但该结构源电流被切断后，B节点电压会上升，MP2的栅端电压过高会使流过MP2的电流大大降低，导致节点A处的电压下降。尽管电压降可以通过反馈控制增加源极电流，但电流增加较小，无法将节点A的电压拉回VDDH，最终稳定在低于VDDH的电压，这会增大后面反向器的静态电流和待机功率。Among the structures based on the current mirror, the Wilson current mirror based level shifter (WCMLS) is an excellent structure. Figure 3 shows the WCMLS structure diagram, which uses the feedback transistor MP3 to turn off the quiescent current flowing through MN1 and MP1 after switching, which can effectively reduce the standby power of the level shift circuit. However, after the source current of this structure is cut off, the voltage at node B will rise, and the high gate voltage of MP2 will greatly reduce the current flowing through MP2, resulting in a drop in the voltage at node A. Although the voltage drop can increase the source current through feedback control, the current increase is small and cannot pull the voltage of node A back to V DDH , and finally stabilizes at a voltage lower than V DDH , which will increase the quiescent current of the subsequent inverter and standby power.
发明内容Contents of the invention
为克服现有技术的不足，针对以上WCMLS中出现的B节点电压会上升的问题，本发明旨在提出一种基于输入控制二极管的新型拓扑结构。在该结构中，二极管电路的引入可以在关断源电流的情况下保证电平移位电路的正常运行，并有效减小WCMLS的待机功率。本发明采用的技术方案是，基于输入控制二极管的电平移位电路，由N型MOS器件MN1～MN4、P型MOS器件MP1，MP2、二极管Di、一个低压反向器以及两个高压反向器组成，MP1，MP2源端接VDDH，栅端连在一起连接在MN1的漏端，构成电流源结构；MN1源端连接MN3漏端，MN3源端接地；MN1的漏端同时连接在二极管Di的上端，二极管下端连接MN4漏端，MN4源端接地；输入信号连接MN1、MN4栅端以及低压反向器输入端，低压反向器输出端连接MN2栅端。MP2漏端，MN2漏端连接，直接连接到第一个高压反向器输入端，MN2源端接地。两个高压反向器串联连接输出高压电平。In order to overcome the deficiencies of the prior art and aim at the problem that the voltage of the B node in the above WCMLS will rise, the present invention aims to propose a new topology based on the input control diode. In this structure, the introduction of the diode circuit can ensure the normal operation of the level shift circuit when the source current is turned off, and effectively reduce the standby power of the WCMLS. The technical scheme adopted in the present invention is based on the level shift circuit of the input control diode, which consists of N-type MOS devices MN1-MN4, P-type MOS devices MP1, MP2, diode Di, a low-voltage inverter and two high-voltage inverters The source terminals of MP1 and MP2 are connected to V DDH , and the gate terminals are connected together to the drain terminal of MN1 to form a current source structure; the source terminal of MN1 is connected to the drain terminal of MN3, and the source terminal of MN3 is grounded; the drain terminal of MN1 is connected to the diode Di at the same time. The upper end of the diode, the lower end of the diode is connected to the drain end of MN4, and the source end of MN4 is grounded; the input signal is connected to the gate end of MN1, MN4 and the input end of the low-voltage inverter, and the output end of the low-voltage inverter is connected to the gate end of MN2. The drain of MP2 is connected to the drain of MN2, directly connected to the input of the first high-voltage inverter, and the source of MN2 is grounded. Two high voltage inverters are connected in series to output high voltage level.
第一个高压反向器输入端为A节点，输出端为D节点，MP1及MP2的栅极为B节点，低压反向器输入端为C节点，当输入信号IN由低电平到高电平跳变时，MN1和MN4导通，MP1中出现电流；MP2通过电流镜结构复制MP1电流来对节点A充电，输入控制二极管Di被激活后将会使节点B电压降低。A节点被充到高电平之后，经过反向器使D节点为低电平，MN3关断，关闭电流源的MP1支路，降低了电平移位电路的待机功率；电平移位器中，输入控制二极管Di和二极管连接的PM1将形成分压器，以保证节点处的电压B低于VDDH，为MP2的栅端电压留下充足的余量；这种状态下将在节点A处保持足够的上拉强度并消除电压降，有效减小反向器中的静态电流。The input end of the first high-voltage inverter is node A, the output end is node D, the gates of MP1 and MP2 are node B, and the input end of the low-voltage inverter is node C. When the input signal IN changes from low level to high level When jumping, MN1 and MN4 are turned on, and current appears in MP1; MP2 copies the MP1 current through the current mirror structure to charge node A, and the input control diode Di is activated to reduce the voltage of node B. After the A node is charged to a high level, the D node is low through the inverter, MN3 is turned off, and the MP1 branch of the current source is turned off, which reduces the standby power of the level shift circuit; in the level shifter, The input control diode Di and the diode-connected PM1 will form a voltage divider to ensure that the voltage at node B is lower than VDDH, leaving sufficient margin for the gate voltage of MP2; this state will maintain sufficient The pull-up strength is high and the voltage drop is eliminated, effectively reducing the quiescent current in the inverter.
当输入IN由高电平到低电平跳变时，MN1，MN2以及MN4将会被关断，电平移位电路处于关闭状态。When the input IN transitions from high level to low level, MN1, MN2 and MN4 will be turned off, and the level shift circuit is in the off state.
本发明的特点及有益效果是：Features and beneficial effects of the present invention are:
本发明中的电平移位器电路，输入控制二极管的应用可以有效保证WCMLS的工作状态，减小反向器的待机电流，与传统的WCMLS电路方案相比，所提出的电路稳定性高，功耗低。In the level shifter circuit of the present invention, the application of the input control diode can effectively ensure the working state of the WCMLS and reduce the standby current of the inverter. Compared with the traditional WCMLS circuit scheme, the proposed circuit has high stability and high performance. low consumption.
附图说明：Description of drawings:
图1基于交叉耦合结构的电平移位电路结构。Figure 1 is based on the level shifting circuit structure of the cross-coupling structure.
图2基于电流镜结构的电平移位电路结构。Figure 2 is based on the level shifting circuit structure of the current mirror structure.
图3威尔逊电流镜结构的电平移位电路结构。The level shift circuit structure of the Wilson current mirror structure in Fig. 3.
图4基于输入控制二极管的电平移位电路结构。Figure 4 is based on the level shifting circuit structure of the input control diode.
具体实施方式Detailed ways
本发明旨在WCMLS电路结构基础之上，提供一种低功耗电平移位电路，本发明提出的技术方案电路图如图4所示。从图中得知，该电路由WCMLS电路结构和输入控制二极管组成，该结构可以有效减小WCMLS电路结构的待机功率。该电平移位电路中各晶体管之间的连接方式如下：The present invention aims to provide a low power consumption level shift circuit based on the WCMLS circuit structure. The circuit diagram of the technical solution proposed by the present invention is shown in FIG. 4 . It is known from the figure that the circuit is composed of a WCMLS circuit structure and an input control diode, which can effectively reduce the standby power of the WCMLS circuit structure. The connection between the transistors in the level shift circuit is as follows:
所述电路由N型MOS器件MN1～MN4、P型MOS器件MP1，MP2、二极管Di、一个低压反向器以及两个高压反向器组成。MP1，MP2源端接VDDH，栅端连在一起连接在MN1的漏端，构成电流源结构。MN1源端连接MN3漏端，MN3源端接地。MN1的漏端同时连接在二极管Di的上端，二极管下端连接MN4漏端，MN4源端接地。输入信号连接MN1、MN4栅端以及低压反向器输入端，低压反向器输出端连接MN2栅端。MP2漏端，MN2漏端连接，直接连接到第一个高压反向器输入端，MN2源端接地。两个高压反向器串联连接输出高压电平。为更好说明原理，假设第一个高压反向器输入端为A节点，输出端为D节点，MP1及MP2的栅极为B节点，低压反向器输入端为C节点。The circuit is composed of N-type MOS devices MN1-MN4, P-type MOS devices MP1, MP2, diode Di, a low-voltage inverter and two high-voltage inverters. The source terminals of MP1 and MP2 are connected to V DDH , and the gate terminals are connected together to the drain terminal of MN1 to form a current source structure. The source terminal of MN1 is connected to the drain terminal of MN3, and the source terminal of MN3 is grounded. The drain end of MN1 is connected to the upper end of the diode Di at the same time, the lower end of the diode is connected to the drain end of MN4, and the source end of MN4 is grounded. The input signal is connected to the gate terminals of MN1 and MN4 and the input terminal of the low-voltage inverter, and the output terminal of the low-voltage inverter is connected to the gate terminal of MN2. The drain of MP2 is connected to the drain of MN2, directly connected to the input of the first high-voltage inverter, and the source of MN2 is grounded. Two high voltage inverters are connected in series to output high voltage level. To better explain the principle, assume that the input end of the first high-voltage inverter is node A, the output end is node D, the gates of MP1 and MP2 are node B, and the input end of the low-voltage inverter is node C.
该结构中，当输入信号IN由低电平到高电平跳变时，MN1和MN4导通，MP1中出现电流。MP2通过电流镜结构复制MP1电流来对节点A充电，输入控制二极管Di被激活后将会使节点B电压降低。A节点被充到高电平之后，经过反向器使D节点为低电平，MN3关断，关闭电流源的MP1支路，降低了电平移位电路的待机功率。在本专利中的电平移位器中，输入控制二极管Di和二极管连接的PM1将形成分压器，以保证节点处的电压B低于VDDH，为MP2的栅端电压留下充足的余量。这种状态下将在节点A处保持足够的上拉强度并消除电压降，有效减小反向器中的静态电流。In this structure, when the input signal IN transitions from low level to high level, MN1 and MN4 are turned on, and current appears in MP1. MP2 copies the MP1 current through the current mirror structure to charge node A, and the input control diode Di is activated to reduce the voltage of node B. After the A node is charged to a high level, the D node is turned to a low level through an inverter, the MN3 is turned off, and the MP1 branch of the current source is turned off, thereby reducing the standby power of the level shift circuit. In the level shifter in this patent, the input control diode Di and the diode-connected PM1 will form a voltage divider to ensure that the voltage B at the node is lower than VDDH, leaving sufficient margin for the gate voltage of MP2. This state will maintain sufficient pull-up strength at node A and eliminate the voltage drop, effectively reducing the quiescent current in the inverter.
当输入IN由高电平到低电平跳变时，MN1，MN2以及MN4将会被关断，电平移位电路处于关闭状态。When the input IN transitions from high level to low level, MN1, MN2 and MN4 will be turned off, and the level shift circuit is in the off state.
为使本发明的目的、技术方案和优点更加清晰，下面将结合实例给出本发明实施方式的具体描述。采用0.18微米工艺的基础上，晶体管的最佳尺寸如下：In order to make the purpose, technical solutions and advantages of the present invention more clear, the following will give a specific description of the implementation of the present invention in conjunction with examples. Based on the 0.18 micron process, the optimum size of the transistor is as follows:
当输入信号为0.3V，输出电压为3.3V时，功率消耗为1.02nW，实现了低功耗的优异性能。When the input signal is 0.3V and the output voltage is 3.3V, the power consumption is 1.02nW, realizing the excellent performance of low power consumption.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020057138A1 (en) * | 2018-09-20 | 2020-03-26 | 北京嘉楠捷思信息技术有限公司 | Full swing voltage conversion circuit and operation unit, chip, hashboard, and computing device using same |
| CN111478693A (en) * | 2020-05-07 | 2020-07-31 | 北京中科芯蕊科技有限公司 | Near-threshold level converter |
| CN113541676A (en) * | 2021-08-10 | 2021-10-22 | 宜矽源半导体南京有限公司 | A low power consumption high voltage level shift circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130131070A (en) * | 2012-05-23 | 2013-12-03 | 한양대학교 에리카산학협력단 | Voltage level shifter |
| CN103856208A (en) * | 2012-11-29 | 2014-06-11 | 英飞凌科技奥地利有限公司 | System and Method for Level Shifter |
| CN105958994A (en) * | 2016-04-25 | 2016-09-21 | 深圳大学 | Subthreshold level shifter having wide input voltage range |
| US9673821B1 (en) * | 2014-10-28 | 2017-06-06 | University Of South Florida | Wide operating level shifters |
-
2017
- 2017-10-25 CN CN201711006129.3A patent/CN107911110A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130131070A (en) * | 2012-05-23 | 2013-12-03 | 한양대학교 에리카산학협력단 | Voltage level shifter |
| CN103856208A (en) * | 2012-11-29 | 2014-06-11 | 英飞凌科技奥地利有限公司 | System and Method for Level Shifter |
| US9673821B1 (en) * | 2014-10-28 | 2017-06-06 | University Of South Florida | Wide operating level shifters |
| CN105958994A (en) * | 2016-04-25 | 2016-09-21 | 深圳大学 | Subthreshold level shifter having wide input voltage range |
Non-Patent Citations (1)
| Title |
|---|
| JUN ZHOU等: "An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage", 《IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020057138A1 (en) * | 2018-09-20 | 2020-03-26 | 北京嘉楠捷思信息技术有限公司 | Full swing voltage conversion circuit and operation unit, chip, hashboard, and computing device using same |
| US11409314B2 (en) | 2018-09-20 | 2022-08-09 | Canaan Creative Co., Ltd. | Full swing voltage conversion circuit and operation unit, chip, hash board, and computing device using same |
| CN111478693A (en) * | 2020-05-07 | 2020-07-31 | 北京中科芯蕊科技有限公司 | Near-threshold level converter |
| CN113541676A (en) * | 2021-08-10 | 2021-10-22 | 宜矽源半导体南京有限公司 | A low power consumption high voltage level shift circuit |
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