CN107910356A - A kind of efficient terminal structure of vertical-type high voltage power device and preparation method thereof - Google Patents

Abstract

The present invention provides a kind of efficient terminal structure of vertical-type high voltage power device and preparation method thereof.The structure includes substrate, the isolated insulation layer being arranged between field ring doped region, field plate and the substrate of substrate top surface, doped region, electrode structure, the passivation layer structure of substrate back.The efficient terminal structure of vertical-type high voltage power device obtained by technical solution provided by the invention, has the characteristics that efficient, isolated insulation ply stress is small, stability is good, easy processing.

Description

A vertical high-voltage power device high-efficiency terminal structure and manufacturing method thereof

technical field

The invention relates to a high-voltage power device, in particular to a high-efficiency terminal structure of a vertical high-voltage power device and a manufacturing method thereof.

Background technique

The power semiconductor chip (such as IGBT, MOSFET, MCT, etc.) is composed of an active area and a terminal area. The active area is the main flow area of the chip. area periphery. In the transition area between the active area and the terminal area, the circumference around the chip is a gate bus bar, which is used to uniformly transmit the gate PAD signal to each cell.

Taking the current common IGBT as an example, the structure of the IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) device is very similar to that of the MOSFET (metallic oxide semiconductor field effect transistor). The main difference between the two is It is the IGBT that replaces the N+ buffer layer of the MOSFET with the P+ substrate, and a PN junction is created between the P+ and N- regions. There are three poles: grid G, emitter E and collector C. The IGBT device is a fully voltage-controlled device. In addition to the advantages of low power consumption, high frequency, high voltage, and high current, the drive circuit and control circuit it requires are simple, and the drive power consumption is low. It is regarded as the first step in power electronics technology. The representative product of the three revolutions is the core device for intelligent management of electric energy and energy saving and emission reduction.

With the sustained and rapid economic development, the energy crisis has become increasingly serious, and the contradiction between supply and demand has become increasingly prominent. It is imperative to develop energy-saving industries and new energy industries. In terms of energy saving, power electronic devices play an important role. They are not only the key components of mechanical automation and intelligent control, but also semiconductor devices that save electric energy. Therefore, it is an important measure to save electric energy to vigorously develop the design and manufacture of power electronic devices and the development and application of modules. As a representative of power electronic devices, IGBT is the product of choice to improve the performance index and energy saving index of the whole machine system.

The design of the terminal structure is one of the key technologies of semiconductor devices, which is closely related to the breakdown voltage, on-state voltage drop and other parameters of the device. When the chip area increases to a certain extent, the probability of defects inside the chip increases significantly, and the chip yield decreases significantly. Therefore, the chip area is limited by material defects. In the case of a certain chip area, the higher the terminal efficiency, the smaller the area, the larger the flow area of the active region, and the lower the on-state voltage drop. At the same time, the higher the withstand voltage level of the device, the larger the terminal size, so the efficiency of the high-voltage device terminal directly affects the on-state voltage drop of the chip. Designing an efficient terminal junction is crucial to the development of high-voltage devices.

Terminal technology is a direct method to reduce the surface electric field and improve the terminal withstand voltage. When the withstand voltage level of the device is increased, the terminal area increases exponentially, the area of the active area of the chip is greatly reduced, and the flow capacity of the high-voltage chip is greatly limited; at the same time, the middle plate and the substrate of the high-voltage terminal structure are thicker The isolated insulating layer can reduce the number of terminal field rings and effectively improve the terminal efficiency, but the resulting film stress will cause the substrate to warp and affect the steps of the photolithography process; the irregular edges formed by the field plate edge etching are also very easy A tip discharge occurs.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art. Taking IGBT as an example, a high-efficiency terminal structure for high-voltage power semiconductor devices is proposed, which has the characteristics of high efficiency, low stress on the isolation insulating layer, good stability and easy processing.

In order to achieve the above object, the present invention provides the following technical solutions:

A vertical high-voltage power device high-efficiency terminal structure, including:

The substrate 101 and the terminal doped regions 106 and 107 and the isolation insulating layer 102 provided on the upper surface of the substrate 101,

isolating the terminal primary field plate 109 and the terminal secondary field plate 110 disposed on the insulating layer 102;

The terminal doped region 106 is provided with an electrical connection layer 108 electrically connected to the terminal primary field plate 109 and the terminal secondary field plate 110 respectively;

A passivation layer 103 is respectively provided on the terminal primary field plate 109 and the terminal secondary field plate 110;

The lower surface of the substrate 101 is provided with a rear doped region 104; an electrode 105 is provided under the rear doped region 104, and the electrode 105 is in ohmic contact with the rear doped region 104;

The first type field plate 111 is provided with a terminal primary field plate 109 and is located in the active area;

One side of the first type field plate 111 is sequentially provided with a second type field plate 112 including a terminal primary field plate 109 and a terminal secondary field plate 110 , and a third type field plate 113 including a terminal secondary field plate 110 .

A first optimal solution for a high-efficiency terminal structure of a vertical high-voltage power device,

The substrate 101 is n-type, the doped regions 104 and 106 are p-type, and the doped region 107 is n-type.

A second preferred solution for a high-efficiency terminal structure of a vertical high-voltage power device,

The substrate 101 is p-type, the doped regions 104 and 106 are n-type, and the doped region 107 is p-type.

A third optimal solution for a vertical high-voltage power device high-efficiency terminal structure,

The doped region 106 has a depth of 1-30 microns, a concentration of 10E12-10E18 cm ^-3 , and a width of 3-30 microns; The impurity region 106 is completed by the same process.

A fourth optimal solution for a vertical high-voltage power device high-efficiency terminal structure,

The doped region 107 has a depth of 1-30 microns, a concentration of 10E12-10E18 cm ^-3 , and a width of 0-100 microns; The impurity region 107 is completed by the same process.

A fifth optimal solution for a vertical high-voltage power device high-efficiency terminal structure,

The horizontal position of the etched edge of the terminal primary field plate 109 in the first type field plate 111 is above the doped region 106 .

A sixth optimal solution for a vertical high-voltage power device high-efficiency terminal structure,

The terminal primary field plate 109 has a length of 0-100 microns; the isolation insulating layer 102 between the terminal primary field plate 109 and the substrate 101 is made of polysilicon or metal material, and has a thickness of 0.02-3 microns; the first type field plate 111 and The terminal primary field plate 109 in the second type field plate 112 is completed by the same process.

A seventh optimal solution for a vertical high-voltage power device high-efficiency terminal structure,

The terminal secondary field plate 110 has a length of 0-100 microns; the isolation insulating layer 102 between the secondary terminal field plate 110 and the substrate 101 is made of polysilicon or metal material and has a thickness of 0.02-3 microns; the second type field plate 112 and the second The terminal secondary field plate 110 among the three types of field plates 113 is completed in the same process.

An eighth optimal solution for a vertical high-voltage power device high-efficiency terminal structure,

There are 1110-20 field plates of the first type, 1120-30 field plates of the second type, and 1130-30 field plates of the third type.

A ninth optimal solution for a vertical high-voltage power device high-efficiency terminal structure,

The terminal structure is based on IGBT, MCT, and BJT three-terminal devices made of Si, SiC, and GaN semiconductor materials.

A method for manufacturing a high-efficiency terminal of a vertical high-voltage power device includes the following steps:

(1) Forming the back doped region 104 of the terminal region on the lower surface of the substrate 101;

(2) forming front terminal doped regions 106, 107 on the upper surface of the substrate 101;

(3) forming an isolation insulating layer 102 on the upper surface of the substrate 101;

(4) forming an electrical connection layer 108, a terminal primary field plate 109 and a terminal secondary field plate 110 on the upper surface of the substrate 101;

(5) forming a passivation layer 103 on the upper surface of the substrate 101;

(6) Forming the electrode 105 on the lower surface of the back doped region 104 .

Compared with the closest prior art, the technical solution provided by the present invention has the following excellent effects:

1. The high-efficiency terminal structure of the vertical high-voltage power device provided by the present invention has the advantages of high efficiency, small stress on the isolation insulating layer and good stability;

2. The method for manufacturing the high-efficiency terminal structure of the vertical high-voltage power device provided by the present invention has the advantage of easy processing.

Description of drawings

Figure 1: Schematic diagram of the high-efficiency terminal structure of the vertical high-voltage power device in the present invention;

Among them, 101 substrate; 106, 107 terminal doping regions; 102 isolation insulating layer; 109 terminal primary field plate; 110 terminal secondary field plate; 108 electrical connection layer; 103 passivation layer; Electrode; 111 first type field plate; 112 second type field plate; 113 third type field plate.

Detailed ways

The technical solutions of the present invention will be clearly and completely described below in conjunction with accompanying drawing 1 and specific embodiments. Apparently, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In this embodiment, a vertical high-voltage power device high-efficiency terminal structure includes

Substrate 101;

terminal doped regions 106, 107, which are arranged on the upper surface of the substrate 101;

an isolation insulating layer 102, which is disposed on the upper surface of the substrate 101;

a terminal primary field plate 109 and a terminal secondary field plate 110, which are arranged on the isolation insulating layer 102;

An electrical connection layer 108, which is disposed on the terminal doped region 106 on the upper surface of the substrate 101, and electrically connects the terminal doped region 106 and the terminal field plates 109, 110;

a passivation layer 103, which is disposed on the isolation insulating layer 102 and the terminal field plates 109, 110;

back doped region 104 (taking IGBT as an example), which is arranged on the lower surface of the substrate 101;

an electrode 105, which is disposed under the doped back region 104 and is in ohmic contact with the doped back region 104;

The first type of field plate 111, which is arranged in the area near the active area of the chip, that is, the leftmost in FIG. 1;

the second type field plate 112, which is arranged on the right side of the first type field plate 111;

The third type field plate 113 is arranged on the right side of the third type field plate 112 .

Example 1

If the substrate 101 is n-type, the doped regions 104 and 106 are p-type, and the doped region 107 is n-type;

Taking an n-type substrate as an example, the doped region 106 is p-type, the doping depth of the doped region is 1-30 microns, the concentration is 10E12-18 cm-3, and the width is 3-30 microns. The doped regions in the field plate-like structures 111, 112, 113 can be completed in the same process.

Taking an n-type substrate as an example, the doped region 107 is n-type, the doping depth of the doped region is 1-30 microns, the concentration is 10E12-18 cm ^-3 , and the width is 0-100 microns. The doped regions in the field plate-like structures 111, 112, 113 can be completed in the same process.

Taking an n-type substrate as an example, the length of the terminal primary field plate 109 is 0-100 microns, and the thickness of the isolation insulating layer 102 between the terminal primary field plate 109 and the substrate 101 is 0.02-3 microns, which can be made of polysilicon or metal Material composition, the terminal primary field plate structure in the first and second type field plate structures 111, 112 can be completed in the same process.

Taking an n-type substrate as an example, the length of the terminal secondary field plate 110 is 0-100 microns, and the thickness of the isolation insulating layer 102 between the terminal secondary field plate 109 and the substrate 101 is 0.02-3 microns, which can be made of polysilicon or metal Material composition, the terminal secondary field plate structure in the second and third types of field plate structures 112 and 113 can be completed in the same process.

In this embodiment, the terminal structure may be composed of 0-20 first-type field plate structures 111 , 0-30 second-type field plate structures 112 , 0-30 third-type field plate structures 113 , and a stop field ring. Its preferred value is designed according to the withstand voltage requirements of the device.

Taking an n-type substrate as an example, the horizontal position of the etched edge of the first-type field plate 111 terminal primary field plate 109 is above the p-type doped region 106, that is, the etched edge does not form an electric field peak with the n-type doped region 107, The possibility of tip discharge is avoided.

Example 2

If the substrate 101 is p-type, the doped regions 104 and 106 are n-type, and the doped region 107 is p-type.

Taking the p-type substrate as an example, the doped region 106 is n-type, the doping depth of the doped region is 1-30 microns, the concentration is 10E12-18 cm-3, and the width is 3-30 microns. The doped regions in the field plate-like structures 111, 112, 113 can be completed in the same process.

Taking the p-type substrate as an example, the doped region 107 is p-type, the doping depth of the doped region is 1-30 microns, the concentration is 10E12-18 cm ^-3 , and the width is 0-100 microns. The doped regions in the field plate-like structures 111, 112, 113 can be completed in the same process.

Taking the p-type substrate as an example, the length of the terminal primary field plate 109 is 0-100 microns, and the thickness of the isolation insulating layer 102 between the terminal primary field plate 109 and the substrate 101 is 0.02-3 microns, which can be made of polysilicon or metal Material composition, the terminal primary field plate structure in the first and second type field plate structures 111, 112 can be completed in the same process.

Taking a p-type substrate as an example, the length of the terminal secondary field plate 110 is 0-100 microns, and the thickness of the isolation insulating layer 102 between the terminal secondary field plate 109 and the substrate 101 is 0.02-3 microns, which can be made of polysilicon or metal Material composition, the terminal secondary field plate structure in the second and third types of field plate structures 112 and 113 can be completed in the same process.

In this embodiment, the terminal structure may be composed of 0-20 first-type field plate structures 111 , 0-30 second-type field plate structures 112 , 0-30 third-type field plate structures 113 , and a stop field ring. Its preferred value is designed according to the withstand voltage requirements of the device.

Taking the p-type substrate as an example, the horizontal position of the etched edge of the first-type field plate 111 terminal primary field plate 109 is above the n-type doped region 106, that is, the etched edge does not form an electric field peak with the p-type doped region 107, The possibility of tip discharge is avoided.

The structures in the above-mentioned embodiments are applicable to various materials and types of devices, such as three-terminal devices such as IGBT, MCT, and BJT developed based on semiconductor materials such as Si, SiC, and GaN.

In this embodiment, the high-efficiency terminals of vertical high-voltage power devices can be prepared according to the following steps, specifically:

1. Form the back doped region 104 of the terminal region on the lower surface of the substrate 101 .

2. Form the front doping 106, 107 of the terminal region on the upper surface of the substrate 101

3. Form an isolation insulating layer 102 on the upper surface of the substrate 101 .

4. Form an electrical connection layer 108 and field plate structures 109 and 110 on the upper surface of the substrate 101 .

5. Form a passivation layer 103 structure on the upper surface of the substrate 101 .

6. Forming an electrode structure 105 on the lower surface of the doped region 104 at the back of the terminal region.

The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Those of ordinary skill in the art should understand that the specific implementation methods of the present invention can be modified or equivalently replaced with reference to the above embodiments, which do not depart from the present invention Any modifications or equivalent replacements in spirit and scope are within the protection scope of the pending claims.

Claims (11)

1. A vertical high-voltage power device high-efficiency terminal structure, characterized in that the terminal structure comprises: the substrate (101) and the terminal doped regions (106, 107) and isolation insulating layer (102) provided on the upper surface of the substrate (101), A terminal primary field plate (109) and a terminal secondary field plate (110) arranged on the isolation insulating layer (102); The terminal doped region (106) is provided with an electrical connection layer (108) electrically connected to the terminal primary field plate (109) and the terminal secondary field plate (110) respectively; A passivation layer (103) is respectively provided on the terminal primary field plate (109) and the terminal secondary field plate (110); The lower surface of the substrate (101) is provided with a doped back area (104); an electrode (105) is arranged under the doped back area (104), and the electrode (105) and the doped back area (104) ohmic contact; A first-type field plate (111), provided with the terminal primary field plate (109), located in the active region; One side of the first type field plate (111) is sequentially provided with a second type field plate (112) including the terminal primary field plate (109) and the terminal secondary field plate (110), and a second type field plate (112) including A third type of field plate (113) of said terminal secondary field plate (110). 2. A vertical high-voltage power device high-efficiency terminal structure as claimed in claim 1, characterized in that, The substrate 101 is n-type, the doped regions 104 and 106 are p-type, and the doped region 107 is n-type. 3. A vertical high-voltage power device high-efficiency terminal structure as claimed in claim 1, characterized in that, The substrate 101 is p-type, the doped regions 104 and 106 are n-type, and the doped region 107 is p-type. 4. A vertical high-voltage power device high-efficiency terminal structure as claimed in claim 1, characterized in that, The doped region (106) has a depth of 1-30 microns, a concentration of 10E12-10E18 cm ^-3 , and a width of 3-30 microns; the first, second and third types of field plates (111, 112 and 113) The doped region (106) is completed by the same step process. 5. A vertical high-voltage power device high-efficiency terminal structure as claimed in claim 1, characterized in that, The doped region (107) has a depth of 1-30 microns, a concentration of 10E12-10E18 cm ^-3 , and a width of 0-100 microns; the first, second and third types of field plates (111, 112 and 113) The doping region (107) is completed by the same process. 6. A vertical high-voltage power device high-efficiency terminal structure as claimed in claim 1, characterized in that, The horizontal position of the etched edge of the terminal primary field plate (109) in the first type field plate (111) is located above the doped region (106). 7. A vertical high-voltage power device high-efficiency terminal structure as claimed in claim 1, characterized in that, The terminal primary field plate (109) has a length of 0-100 microns; the isolation insulating layer (102) between the terminal primary field plate (109) and the substrate (101) is made of polysilicon or metal material, The thickness is 0.02-3 microns; the terminal primary field plate (109) in the first and second type field plates (111, 112) is completed by the same step process. 8. A vertical high-voltage power device high-efficiency terminal structure as claimed in claim 1, characterized in that, The length of the terminal secondary field plate (110) is 0 to 100 microns; the isolation insulating layer (102) between the terminal secondary field plate (110) and the substrate (101) is made of polysilicon or a metal material with a thickness of 0.02-3 microns; the terminal secondary field plate (110) in the second and third type field plates (112, 113) is completed in the same process step. 9. A vertical high-voltage power device high-efficiency terminal structure as claimed in claim 1, characterized in that, There are 0-20 first-type field plates (111), 0-30 second-type field plates (112), and 0-30 third-type field plates (113). 10. A vertical high-voltage power device high-efficiency terminal structure as claimed in claim 1, characterized in that, The terminal structure is based on IGBT, MCT and BJT three-terminal devices made of Si, SiC and GaN semiconductor materials. 11. A method for manufacturing a high-efficiency terminal of a vertical high-voltage power device as claimed in claim 1, wherein: The method comprises the steps of: (1) forming a doped region (104) on the back side of the terminal region on the lower surface of the substrate (101); (2) forming front terminal doped regions (106, 107) on the upper surface of the substrate (101); (3) forming an isolation insulating layer (102) on the upper surface of the substrate (101); (4) forming an electrical connection layer (108), a terminal primary field plate (109) and a terminal secondary field plate (110) on the upper surface of the substrate (101); (5) forming a passivation layer (103) on the upper surface of the substrate (101); (6) forming an electrode (105) on the lower surface of the back doped region (104).