CN107896091A - A kind of low-power consumption broadband varactor doubler circuit - Google Patents

Abstract

The present invention relates to a kind of low-power consumption broadband varactor doubler circuit.Its application in RF communication system than lower limit of existing frequency source frequency, the method that frequency multiplier is cascaded by voltage controlled oscillator realize high-frequency frequency source.The present invention includes a push push structure, input balun, two matching networks；Push push structures are made up of two HBT triodes, and input balun is realized by way of double layer of metal levels are coupled, and two matching networks include input matching network and output matching network.The present invention realizes the performance of wider frequency operating range and low-power consumption.

Description

A low-power broadband frequency doubler circuit

technical field

The invention belongs to the technical field of microelectronics, and relates to a low power consumption broadband frequency doubler circuit.

Background technique

In recent years, with the rapid development of millimeter-wave wireless communication systems, the application of millimeter-wave frequency sources in imaging, medical, military and other fields has become more and more popular, and the application frequency band has become higher and higher, and the demand for millimeter-wave signal sources has also increased. more urgent. However, the directly obtained high-frequency frequency source cannot meet the requirements of the communication system in terms of frequency stability and phase noise, so it is necessary to design a broadband frequency multiplier to realize the high-frequency frequency source to meet the requirements of the communication system. As the most basic building block in the high-frequency frequency source, the frequency multiplier increases the frequency of the voltage-controlled oscillator to a higher frequency band, and plays a decisive role in the performance of the frequency source. Under the premise of ensuring power consumption, the frequency multiplier should have a wide frequency coverage to meet the needs of different applications.

The commonly used structures of frequency multipliers include single-tube frequency multiplier, push-push frequency multiplier and injection-locked frequency multiplier. The single-tube frequency multiplier has a simple structure and is easy to implement because it uses a single transistor. However, its poor suppression of the fundamental wave limits its application in radio frequency communication systems. The traditional injection-locked frequency multiplier uses the nonlinearity of the transistor. The harmonic generator can generate harmonic signals of the input frequency, and then these harmonic signals are injected into the oscillator. When the resonant frequency of the oscillator is n times the frequency of the input signal , The nth harmonic obtains the maximum loop gain, thereby realizing the function of n-fold frequency. This type of frequency multiplier has a narrow operating frequency range, limited application range and complex structure, making it difficult to realize. Therefore, how to improve the operating bandwidth of the frequency multiplier under the requirement of low power consumption has become a key issue in the design of the frequency multiplier circuit.

Chinese patent CN 102270964 A proposes a phase splitter circuit that responds to an input signal to generate N signals with phase differences, and then realizes N frequency multiplication by means of frequency mixing. The phase splitter and mixer are mainly used, but the disadvantage is that the structure is complex and the application frequency band is not high.

Chinese patent CN 104079242 A proposes a triple frequency multiplier using a Lange coupler and two transistor structures, mainly using the Lange coupler. The disadvantage is that the design of the two Lange couplers is complex and time-consuming, there are too many passive components in the circuit structure, and the chip area is relatively large.

Contents of the invention

The object of the present invention is to provide a frequency doubler circuit with low power consumption and wide frequency band, which is suitable for InP HBT (HBT refers to heterojunction bipolar transistor) technology.

The present invention includes a push-push structure, an input balun, and two matching networks; the push-push structure is composed of two HBT tubes, and the input balun is realized by coupling the upper and lower layers of two metal layers. The network includes an input matching network and an output matching network.

The first HBT tube (T1) and the second HBT tube (T2) form a push-push structure, wherein the collector of the first HBT tube (T1) is connected to the collector of the second HBT tube (T2) as the output terminal (Vout ). The emitter of the first HBT tube (T1) is connected to the emitter of the second HBT tube (T2), and then grounded. The base of the first HBT tube (T1) is connected to the non-inverting output terminal (B2P) of the secondary of the balun (TR1), and the base of the second HBT tube (T2) is connected to the inverting output terminal (B2N) of the secondary of the balun. connected.

One end of the input matching capacitor (C1) is connected to the input signal, and the other end is connected to the non-inverting input end (B1P) of the balun primary. The inverting input (B1N) of the balun primary is connected to ground. One end of the output matching capacitor (C2) is connected to the output end (Vout) of the push-push structure, and the other end is used as the output end of the whole circuit. One end of the first matching inductor (L1) is connected to the collector of the first HBT tube (T1), and the other end is connected to one end of the second filter capacitor (C4) and then connected to the bias voltage Vcc. One end of the second matching inductor (L2) is connected to the collector of the second HBT transistor (T2), and the other end is connected to one end of the fourth filter capacitor (C6) and then connected to the bias voltage Vcc. One end of the first bias resistor (R1) is connected to the base of the first HBT transistor (T1), and the other end is connected to one end of the first filter capacitor (C3) and then connected to the bias voltage Vb. One end of the second bias resistor (R2) is connected to the base of the second HBT transistor (T2), and the other end is connected to one end of the third filter capacitor (C5) and then connected to the bias voltage Vb.

The other end of the first filter capacitor (C3), the other end of the second filter capacitor (C4), the other end of the third filter capacitor (C5), and the other end of the fourth filter capacitor (C6) are all grounded.

The beneficial effects of the present invention are:

The push-push frequency multiplier of the present invention can overcome the deviation caused by the process because of the symmetry of its circuit, and has a good degree of suppression to the fundamental wave, a wide working frequency band (130-200GHz), and low power consumption. There is 10.8mW.

Compared with the prior art, the present invention has fewer passive components, simple structure, high application frequency band and small chip area.

Description of drawings

Fig. 1 is the overall circuit diagram of the present invention.

Detailed ways

The circuit structure of the present invention will be further described in detail below in conjunction with the accompanying drawings. In order to illustrate the effect of the present invention, a 0.5um InP HBT process is used for design tape-out verification.

As shown in Figure 1, a low-power broadband frequency doubler circuit includes a push-push structure, an input balun, and two matching networks;

The first HBT tube (T1) and the second HBT tube (T2) form a push-push structure, wherein the collector of the first HBT tube (T1) is connected to the collector of the second HBT tube (T2) as the output terminal (Vout ). The emitter of the first HBT tube (T1) is connected to the emitter of the second HBT tube (T2), and then grounded. The base of the first HBT transistor (T1) is connected to the non-inverting output terminal (B2P) of the balun secondary, and the base of the second HBT transistor (T2) is connected to the inverting output terminal (B2N) of the balun secondary.

One end of the input matching capacitor (C1) is connected to the input signal, and the other end is connected to the non-inverting input end (B1P) of the balun primary. The inverting input (B1N) of the balun primary is connected to ground. One end of the output matching capacitor (C2) is connected to the output end (Vout) of the push-push structure, and the other end is used as the output end of the whole circuit. One end of the first matching inductor (L1) is connected to the collector of the first HBT tube (T1), and the other end is connected to one end of the second filter capacitor (C4) and then connected to the bias voltage Vcc. One end of the second matching inductor (L2) is connected to the collector of the second HBT transistor (T2), and the other end is connected to one end of the fourth filter capacitor (C6) and then connected to the bias voltage Vcc. One end of the first bias resistor (R1) is connected to the base of the first HBT transistor (T1), and the other end is connected to one end of the first filter capacitor (C3) and then connected to the bias voltage Vb. One end of the second bias resistor (R2) is connected to the base of the second HBT transistor (T2), and the other end is connected to one end of the third filter capacitor (C5) and then connected to the bias voltage Vb.

The other end of the first filter capacitor (C3), the other end of the second filter capacitor (C4), the other end of the third filter capacitor (C5), and the other end of the fourth filter capacitor (C6) are all grounded.

The input signal can be expressed as Vin=Vicos(ωt), where Vi is the amplitude and ω is the angular frequency. According to the model of the nonlinear device, the output signal can be expressed by Taylor series as:

Substituting Vin＝Vicos(ωt) into formula (1), by simplifying the first four terms, we can get:

The current in formula (2) includes DC items and high-order harmonic items. By adding a filter matching circuit with a suitable frequency band after the frequency multiplier, the overall circuit can output the required harmonics while suppressing the output of other harmonics.

The invention is a frequency doubler working at 140GHz, which adopts an active balanced topological structure, and a passive balun (TR1) at the input end converts a single-ended signal into a differential signal. The so-called differential signal refers to a pair of signals with the same amplitude and opposite phase. The collectors of the transistors are connected together to add all the even harmonics while canceling the fundamental and other odd harmonics. Therefore, the suppression effect on the fundamental wave is better. The input matching is composed of passive baluns, so the input bandwidth can be very wide, that is, the working frequency band will be very wide. The output matching is matched on the frequency band of the second harmonic, so the other even harmonics such as the fourth and sixth harmonics are greatly suppressed. The entire circuit consists of only 2 transistors and some passive components, so the power consumption is only generated by these two transistors, and the power consumption is only 10.8mW through calculation.

Claims (1)

1. A low power consumption broadband frequency doubler circuit is characterized in that comprising a push-push structure, an input balun, and two matching networks; The first HBT tube (T1) and the second HBT tube (T2) form a push-push structure, wherein the collector of the first HBT tube (T1) is connected to the collector of the second HBT tube (T2) as the output terminal (Vout ); the emitter of the first HBT tube (T1) is connected to the emitter of the second HBT tube (T2), and then grounded; the base of the first HBT tube (T1) and the non-inverting output terminal of the secondary of the balun (TR1) (B2P) is connected, and the base of the second HBT tube (T2) is connected to the inverting output terminal (B2N) of the balun secondary; One end of the input matching capacitor (C1) is connected to the input signal, and the other end is connected to the non-inverting input end (B1P) of the balun primary; the inverting input end (B1N) of the balun primary is grounded; one end of the output matching capacitor (C2) is connected to the push- The output end (Vout) of the push structure is connected, and the other end is used as the output end of the whole circuit; one end of the first matching inductor (L1) is connected to the collector of the first HBT tube (T1), and the other end is connected to the second filter capacitor (C4). Connected to the bias voltage Vcc; one end of the second matching inductor (L2) is connected to the collector of the second HBT tube (T2), and the other end is connected to the fourth filter capacitor (C6) and then connected to the bias voltage Vcc; the first bias One end of the setting resistor (R1) is connected to the base of the first HBT tube (T1), the other end is connected to one end of the first filter capacitor (C3) and then connected to the bias voltage Vb; one end of the second biasing resistor (R2) is connected to the second HBT The base of the tube (T2), the other end is connected to one end of the third filter capacitor (C5) and then connected to the bias voltage Vb; The other end of the first filter capacitor (C3), the other end of the second filter capacitor (C4), the other end of the third filter capacitor (C5), and the other end of the fourth filter capacitor (C6) are all grounded.