CN107871724B - Substrate structure and method of making the same - Google Patents
Substrate structure and method of making the same Download PDFInfo
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- CN107871724B CN107871724B CN201610846610.2A CN201610846610A CN107871724B CN 107871724 B CN107871724 B CN 107871724B CN 201610846610 A CN201610846610 A CN 201610846610A CN 107871724 B CN107871724 B CN 107871724B
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- protrusion
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- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 209
- 239000002184 metal Substances 0.000 claims abstract description 79
- 229910052751 metal Inorganic materials 0.000 claims abstract description 79
- 239000011241 protective layer Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims 2
- 230000032798 delamination Effects 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 9
- 238000002161 passivation Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 239000005022 packaging material Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000007788 roughening Methods 0.000 description 3
- 239000002335 surface treatment layer Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- ICXAPFWGVRTEKV-UHFFFAOYSA-N 2-[4-(1,3-benzoxazol-2-yl)phenyl]-1,3-benzoxazole Chemical compound C1=CC=C2OC(C3=CC=C(C=C3)C=3OC4=CC=CC=C4N=3)=NC2=C1 ICXAPFWGVRTEKV-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Laminated Bodies (AREA)
Abstract
一种基板结构及其制法包括：介电层、形成于该介电层上且具有凸部的金属层、以及形成于该介电层及该金属层与该凸部上的保护层，以通过该凸部而增加该金属层与该保护层之间的结合面积及卡固效果，避免该金属层与该保护层之间发生分层。
A substrate structure and a manufacturing method thereof include: a dielectric layer, a metal layer formed on the dielectric layer and having a convex portion, and a protective layer formed on the dielectric layer, the metal layer and the convex portion, to The convex portion increases the bonding area and the clamping effect between the metal layer and the protective layer, so as to avoid delamination between the metal layer and the protective layer.
Description
Technical Field
The present disclosure relates to a substrate structure, and more particularly, to a substrate structure having a metal layer and a method for fabricating the same.
Background
With the rapid development of the electronic industry and the evolution of the packaging technology, the size or volume of the semiconductor package is also continuously reduced, and the semiconductor package is made to be light, thin, small and small. At present, a substrate of a semiconductor package applied in an electronic product, such as a carrier of a mobile phone chip, a lens module circuit board or a coil board, has a large copper surface area on a surface thereof to achieve a technical effect of dissipating heat or reducing noise, and an insulating protection layer is required to be formed to isolate an absolute line so as to prevent the line from contacting other elements.
Fig. 1A is a schematic cross-sectional view of a semiconductor package 1 of the prior art. As shown in fig. 1, the semiconductor package 1 includes a package substrate 11 and a semiconductor chip 12 mounted on the package substrate 11, wherein the package substrate 11 includes a dielectric layer 10, circuit layers 110 and 112 formed on opposite sides of the dielectric layer 10, and an insulating passivation layer 13 formed on the dielectric layer 10 and the circuit layers 110 and 112 and having openings 130 exposing the circuit layers 110 and 112, so that the semiconductor chip 12 is flip-chip bonded to the upper circuit layer 110 of the package substrate 11 through a plurality of solder bumps 14 by electrode pads 120 thereof, and then a plurality of solder balls 15 are formed on the lower circuit layer 112 of the package substrate 11.
In the package substrate 11, however, the circuit layers 110,112 and the insulating protection layer 13 are made of different materials, and the materials of the dielectric layer 10 and the insulating protection layer 13 are different, so when temperature cycle (temperature cycle) or stress variation is performed in the manufacturing process of the semiconductor package 1, such as passing through a reflow furnace or undergoing drop-down process or test, the areas where the circuit layers 110 and 112 are bonded to the insulating passivation layer 13 or the dielectric layer 10 is bonded to the insulating passivation layer 13 are easily separated from each other due to CTE mismatch, stress concentration, poor bonding, and the like, a delamination problem occurs, which may cause the solder bumps 14 and the solder balls 15 to fail to effectively electrically connect the semiconductor chip 12 and the package substrate 11, or the product fails a reliability test, resulting in poor yield of the product.
As shown in fig. 1B, although the surface of the circuit layer 110 may be formed with a roughened structure 110a, the roughness Ra value of which is about 0.1 to 0.5 μm, to increase the bonding property between the circuit layer 110 and the insulating protection layer 13, the bonding surface between the circuit layer 110 and the insulating protection layer 13 still presents a flat surface, so that the stress distribution direction continuously extends along the bonding surface between the circuit layer 110 and the insulating protection layer 13 (as shown by arrow a in fig. 1B, i.e. in a horizontal direction relative to the surface of the dielectric layer 10), and thus delamination is still easily generated.
In addition, with the demand for miniaturization (miniaturization) of semiconductor packages, the size of the circuit layer 110 is also reduced, so that the roughening process is not easy to be performed. Furthermore, even if the roughening process is performed, the delamination between the circuit layers 110,112 and the insulation protection layer 13 or between the dielectric layer 10 and the insulation protection layer 13 cannot be effectively prevented.
Therefore, how to overcome the disadvantages of the conventional techniques is a technical problem to be solved in the present circles.
Disclosure of Invention
In view of the above-mentioned shortcomings of the known technology, the present disclosure provides a substrate structure and a method for fabricating the same, which can prevent the delamination between the metal layer and the protection layer.
The substrate structure of the present disclosure includes: a dielectric layer having opposing first and second sides; a first metal layer formed on a first side of the dielectric layer and having a plurality of integrally formed first protrusions; and a protective layer formed on the first side of the dielectric layer and the first metal layer and the first protrusion.
The present disclosure also provides a method for manufacturing a substrate structure, including: providing a bearing part with a plurality of concave parts on the surface; forming a first metal layer on the carrier and in the recess, so that the first metal layer forms an integrally formed first convex part in the recess; forming a dielectric layer on the carrier and the first metal layer; removing the carrier to expose the first metal layer and the first protrusion; and forming a protective layer on the dielectric layer, the first metal layer and the first protrusion.
In the foregoing substrate structure and the manufacturing method thereof, the dielectric layer has a second protrusion integrally formed in the recess. In addition, after the bearing piece is removed, the protective layer is also formed on the second convex part.
In the foregoing substrate structure and the manufacturing method thereof, the surface of the first protrusion is a roughened surface.
In addition, the substrate structure and the manufacturing method thereof further include forming a second metal layer on the dielectric layer, wherein the second metal layer is electrically connected to the first metal layer through the conductive via hole formed in the dielectric layer.
In view of the above, the substrate structure and the method for manufacturing the same of the present disclosure mainly increase the bonding area and the engaging effect between the first metal layer and the protective layer and between the dielectric layer and the protective layer by the first metal layer having the integrally formed first protrusion and the dielectric layer having the integrally formed second protrusion, so as to improve the bonding performance between the two heterogeneous materials, and the bonding surface between the first metal layer and the protective layer and between the dielectric layer and the protective layer will present a discontinuous surface, so that the stress will be dispersed along the first protrusion and the second protrusion, thereby avoiding the delamination between the first metal layer and the protective layer and between the dielectric layer and the protective layer compared to the known technology.
Drawings
FIG. 1A is a schematic cross-sectional view of a prior art semiconductor package;
FIG. 1B is a schematic partial cross-sectional view of a prior art package substrate;
fig. 2A to 2E are schematic cross-sectional views illustrating a method for fabricating a substrate structure according to the present disclosure; and
fig. 3 is a partially enlarged cross-sectional view of another embodiment of fig. 2E.
Description of the symbols
1 semiconductor package
10,22 dielectric layer
11 packaging substrate
110,112 wiring layer
110a roughening structure
12 semiconductor wafer
120 electrode pad
13 insulating protective layer
130,240,250 opening holes
14 solder bump
15 solder ball
2 substrate structure
20 load bearing member
20a barrier layer
20b carrier plate
200 recess
21 first metal layer
210 first convex part
22a first side
22b second side
220 second convex part
23 second metal layer
230 conductive blind hole
24 welding-proof layer
25 protective layer
26 surface treatment layer
30 roughened surface
Height of T
The directions of arrows A, B and C.
Detailed Description
The embodiments of the present disclosure are described below with reference to specific embodiments, and other advantages and technical effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings of the present specification are only used for matching with the disclosure of the present specification to provide understanding and reading for those skilled in the art, and are not used to limit the limit conditions of the present disclosure, so they have no technical essence, and any structural modification, ratio relationship change or size adjustment should still fall within the scope of the technical disclosure without affecting the technical effect and the achievable purpose of the present disclosure. In addition, the terms "above", "first", "second" and "first" used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or adjustments of the relative relationship thereof may be considered as the scope of the present disclosure without substantial changes in the technical content.
Fig. 2A to 2E are schematic cross-sectional views illustrating a method for manufacturing the substrate structure 2 according to the present disclosure.
As shown in fig. 2A, a carrier 20 having a plurality of recesses 200 on a surface thereof is provided.
In the present embodiment, the carrier 20 includes a carrier 20b and an isolation layer 20a disposed on the carrier, and the recess 200 is formed on the isolation layer 20 a. Of course, the concave portion 200 can be formed directly on the carrier plate 20b without providing the isolation layer 20 a.
As shown in fig. 2B, a patterned first metal layer 21 is formed on the carrier 20, and the first metal layer 21 is filled into a portion of the concave portion 200, so that the first metal layer 21 has a first convex portion 210 integrally formed in the concave portion 200. Of course, the position of the concave portion 200 can also be matched with the position of the first metal layer 21, so that the first metal layer 21 is filled into all the concave portions 200.
In the present embodiment, the first metal layer 21 is used for a conductive circuit, a heat sink, an electromagnetic shield, or other functions required by the package substrate, and the material forming the first metal layer 21 is copper. The first metal layer 21 is formed by patterning a circuit.
As shown in fig. 2C, a dielectric layer 22 is formed on the carrier 20 and the first metal layer 21, and a second metal layer 23 is formed on the dielectric layer 22, such that the second metal layer 23 is electrically connected to the first metal layer 21 through the conductive via 230 in the dielectric layer 22.
In the present embodiment, the second metal layer 23 is formed of copper or other metal materials, and the dielectric layer 22 is formed of dielectric materials such as poly-p-Phenylene Benzobisoxazole (PBO), Polyimide (PI) or Prepreg (PP).
In addition, the dielectric layer 22 defines a first side 22a and a second side 22b opposite to each other, so that the first side 22a is bonded to the isolation layer 20a of the carrier 20, the first side 22a of the dielectric layer 22 is formed with a second protrusion 220 integrally formed in a portion of the recess 200, the first metal layer 21 is embedded in the first side 22a of the dielectric layer 22, a surface of the first metal layer 21 is flush with the first side 22a of the dielectric layer 22, and the second metal layer 23 is disposed on the second side 22b of the dielectric layer 22.
It should be understood that a plurality of dielectric layers (not shown) and a plurality of metal layers (not shown) may be formed on the second side 22b of the dielectric layer 22 as required, and is not limited to the drawings.
As shown in fig. 2D, a solder mask layer 24 is formed on the second side 22b of the dielectric layer 22, and the carrier plate 20b and the isolation layer 20a are removed to expose the first metal layer 21 and the first protrusion 210 thereof, and the first side 22a and the second protrusion 220 thereof of the dielectric layer 22.
In the present embodiment, the solder mask layer 24 is formed with a plurality of openings 240, such that a portion of the surface of the second metal layer 23 is exposed to the openings 240.
As shown in fig. 2E, a protection layer 25 is formed on the first side 22a of the dielectric layer 22 and at least a portion of the second protrusion 220 thereof, and on the first metal layer 21 and at least a portion of the first protrusion 210 thereof. In addition, the positions of the first protrusion 210 and the second protrusion 220 can also be matched with the position of the protection layer 25, so that the protection layer 25 covers all the first protrusion 210 and the second protrusion 220.
In the present embodiment, the passivation layer 25 is formed with a plurality of openings 250, such that a portion of the surface of the first metal layer 21 and a portion of the first protrusion 210, and a portion of the first side 22a and a portion of the second protrusion 220 of the dielectric layer 22 are exposed out of the openings 250, and the material forming the passivation layer 25 is an insulating material, such as a green paint, to serve as a solder mask.
In addition, a surface treatment layer 26 may be formed on the second metal layer 23, the first metal layer 21 and the first protrusion 210 thereof in the openings 240,250 as required, and the surface of the surface treatment layer 26 may be protruded according to the first protrusion 210.
As shown in fig. 3, the height t of the first protrusion 210 is greater than 0.5 μm. The height of the second protrusion 220 is also greater than 0.5 μm.
In the manufacturing method of the substrate structure 2 of the present disclosure, the first metal layer 21 has the first protruding portion 210 integrally formed, so that the first protruding portion 210 can be embedded and clamped in the protection layer 25, and the bonding area between the first metal layer 21 and the protection layer 25 is increased to improve the bonding property between the first metal layer 21 and the protection layer 25, in addition, the bonding surface between the first metal layer 21 and the protection layer 25 will present a discontinuous surface (i.e., a non-flat surface), so that the stress will be dispersed along the first protruding portion 210 (as shown by arrow directions B and C in fig. 2E, i.e., the oblique line direction relative to the first side 22 a), so compared with the known technology, the present disclosure can avoid the problem of delamination between the first metal layer 21 and the protection layer 25.
In addition, the dielectric layer 22 has the integrally formed second protrusion 220, so that the second protrusion 220 can be embedded and clamped in the protection layer 25, the bonding area between the dielectric layer 22 and the protection layer 25 is increased to improve the bonding property between the two, and the bonding surface between the dielectric layer 22 and the protection layer 25 presents a discontinuous surface, so that the stress is dispersed along the second protrusion 220, and compared with the prior art, the present disclosure can also avoid the problem of delamination between the dielectric layer 22 and the protection layer 25.
It should be understood that the surface of the first metal layer 21 (or the dielectric layer 22) and the surface of the first protrusion 210 (or the second protrusion 220) may be roughened as required, as shown in fig. 3, to form a roughened surface 30 with a roughness Ra value of about 0.1 to 0.5 μm.
In addition, after the subsequent die-placing process and the packaging process of the substrate structure 2, a packaging material (not shown) is bonded to the dielectric layer 22 or the first metal layer 21 for heat dissipation or electromagnetic shielding, so as to increase the bonding area between the first metal layer 21 (or the dielectric layer 22) and the packaging material through the first protrusion 210 (or the second protrusion 220) located in the opening 250, thereby improving the bonding performance between the first metal layer 21 (or the dielectric layer 22) and the packaging material, and the bonding surface between the first metal layer 21 (or the dielectric layer 22) and the packaging material presents a discontinuous surface, so that the stress is dispersed along the first protrusion 210 (or the second protrusion 220), thereby the substrate structure 2 of the present disclosure can avoid the problem of delamination between the first metal layer 21 (or the dielectric layer 22) and the packaging material.
The present disclosure also provides a substrate structure 2, comprising: a dielectric layer 22, a first metal layer 21 and a protection layer 25.
The dielectric layer 22 has a first side 22a and a second side 22b opposite to each other.
The first metal layer 21 is formed on the first side 22a of the dielectric layer 22 and has a plurality of integrally formed first protrusions 210.
The passivation layer 25 is formed on the first side 22a of the dielectric layer 22, the first metal layer 21 and the first protrusion 210.
In one embodiment, the dielectric layer 22 has a second protrusion 220 integrally formed thereon, and the passivation layer 25 is further formed on the second protrusion 220.
In one embodiment, the surface of the first protrusion 210 is a roughened surface 30.
In one embodiment, the substrate structure 2 further includes a second metal layer 23 formed on the second side 22b of the dielectric layer 22 and electrically connected to the first metal layer 21 through a conductive via 230 in the dielectric layer 22.
In summary, the substrate structure and the method for fabricating the same of the present disclosure increase the bonding area and the embedding effect between the first metal layer and the protection layer and between the dielectric layer and the protection layer by the first metal layer having the first protrusion and the dielectric layer having the second protrusion, so as to improve the bonding property between the first metal layer and the protection layer and between the dielectric layer and the protection layer, and the bonding surface between the first metal layer and the protection layer and between the dielectric layer and the protection layer will present a discontinuous surface, so that the stress will be dispersed along the first protrusion and the second protrusion, thereby avoiding the delamination between the first metal layer and the protection layer or between the dielectric layer and the protection layer.
The above-described embodiments are merely illustrative of the principles of the present disclosure and technical effects thereof, and are not intended to limit the present disclosure. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present disclosure. Therefore, the scope of the disclosure should be determined from the following claims.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610846610.2A CN107871724B (en) | 2016-09-23 | 2016-09-23 | Substrate structure and method of making the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610846610.2A CN107871724B (en) | 2016-09-23 | 2016-09-23 | Substrate structure and method of making the same |
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| Publication Number | Publication Date |
|---|---|
| CN107871724A CN107871724A (en) | 2018-04-03 |
| CN107871724B true CN107871724B (en) | 2021-08-13 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409273A (en) * | 2007-10-08 | 2009-04-15 | 全懋精密科技股份有限公司 | Ball-planting side surface structure of packaging substrate and manufacturing method thereof |
| CN102867798A (en) * | 2011-07-08 | 2013-01-09 | 欣兴电子股份有限公司 | Coreless packaging substrate and manufacturing method thereof |
| CN103208456A (en) * | 2013-03-22 | 2013-07-17 | 上海宏力半导体制造有限公司 | Semiconductor structure forming method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100368115B1 (en) * | 2001-01-26 | 2003-01-15 | 삼성전자 주식회사 | Bonding pad structure of semiconductor device and method for fabricating the same |
| US9673125B2 (en) * | 2012-10-30 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnection structure |
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2016
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409273A (en) * | 2007-10-08 | 2009-04-15 | 全懋精密科技股份有限公司 | Ball-planting side surface structure of packaging substrate and manufacturing method thereof |
| CN102867798A (en) * | 2011-07-08 | 2013-01-09 | 欣兴电子股份有限公司 | Coreless packaging substrate and manufacturing method thereof |
| CN103208456A (en) * | 2013-03-22 | 2013-07-17 | 上海宏力半导体制造有限公司 | Semiconductor structure forming method |
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| CN107871724A (en) | 2018-04-03 |
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