CN107871674A - A kind of method for packing of 50 μm of copper posts - Google Patents
A kind of method for packing of 50 μm of copper posts Download PDFInfo
- Publication number
- CN107871674A CN107871674A CN201710879079.3A CN201710879079A CN107871674A CN 107871674 A CN107871674 A CN 107871674A CN 201710879079 A CN201710879079 A CN 201710879079A CN 107871674 A CN107871674 A CN 107871674A
- Authority
- CN
- China
- Prior art keywords
- copper
- packing
- photoresist
- copper posts
- electroplated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010949 copper Substances 0.000 title claims abstract description 68
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 67
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 67
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000012856 packing Methods 0.000 title claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 15
- 238000000576 coating method Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 238000007747 plating Methods 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 238000002161 passivation Methods 0.000 claims abstract description 6
- 239000007788 liquid Substances 0.000 claims description 9
- 238000004528 spin coating Methods 0.000 claims description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 7
- 239000003292 glue Substances 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 239000003795 chemical substances by application Substances 0.000 claims description 5
- 238000009499 grossing Methods 0.000 claims description 5
- 241000370738 Chlorion Species 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims 1
- 238000010422 painting Methods 0.000 claims 1
- 238000004377 microelectronic Methods 0.000 abstract description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 238000004026 adhesive bonding Methods 0.000 description 9
- 238000001020 plasma etching Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 206010013786 Dry skin Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The present invention relates to a kind of method for packing of 50 μm of copper posts, including：Cleaning, passivation, sputtering, coating photoresist layer, plating and backflow.Present invention optimizes technological process, reduces packaging cost, reduces chip size, has complied with that market is increasingly light to microelectronic product, the requirement of thin, short, small and low priceization；Pin spacing is further reduced simultaneously, the number of pins i.e. I/O quantity in single chip is added, meets height precise and tinyization of electronic product, have a good application prospect.
Description
Technical field
The invention belongs to wafer stage chip encapsulation field, more particularly to a kind of method for packing of 50 μm of copper posts.
Background technology
Semiconductor chip features size progressively reduces with Moore's Law, along with electronic system high-performance, multi-functional, small
The requirement of type and low cost, integrated antenna package need more input/output end port numbers, higher electrical property and heat management
Performance.Therefore, conventional package is difficult to meet the needs of micro- spacing superchip encapsulation, and copper pillar bumps technology is excellent mutual because of its
Even ability provides advanced encapsulation solution for above-mentioned application, turns into the mainstream technology of chip package.Copper pillar bumps mainly by
Copper post and tin cap are formed, and copper post part has extension ability, but does not possess welding performance, to supporting lug overall structure.
But due to technological reason, conventional copper post size is 80-100 μm at present, limits the further of chip size
Reduce.Therefore, urgent need seeks a kind of new method for packing and further reduces copper post size.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of method for packing of 50 μm of copper posts, and this method optimizes technique
Flow, packaging cost is reduced, reduce chip size, it is increasingly light to microelectronic product, thin, short, small and low to have complied with market
Valencyization requirement；Pin spacing is further reduced simultaneously, the number of pins i.e. I/O quantity in single chip is added, meets
Height precise and tinyization of electronic product, has a good application prospect.
The invention provides a kind of method for packing of 50 μm of copper posts, including：
(1) cleaning wafer removes the foreign matter on surface and dirty；
(2) passivation layer is coated again as cushion in crystal column surface；
(3) copper, titanium Seed Layer are sputtered in passivation layer surface again；
(4) photoresist is coated as photoresist layer in copper, titanium seed layer surface；Wherein coating photoresist includes spin coating, whirl coating
And get rid of side；
(5) copper post and tin cap are electroplated by ECD；Wherein, copper post is electroplated using SC28 copper electroplating liquids；
(6) finally by the tin backflow globulate of plating.
The amount of coating photoresist in the step (4) is 5-10ml.
Spin coating speed in the step (4) is 750-800rpm, spin coating time 10-15s；Whirl coating speed is 350-
400rpm, whirl coating time are 20-25s；It is 500-600rpm to get rid of side speed, and it is 2-4s to get rid of the side time.
The composition of SC28 copper electroplating liquids in the step (5) is：Copper 26-30g/L, sulfuric acid 150-250g/L, chlorion
30-50mg/L, brightener MD 2-8ml/L (firmly believe happy chemical trade (Shanghai) Co., Ltd. of think of), smoothing agent LO 1-4ml/L
(firmly believing happy chemical trade (Shanghai) Co., Ltd. of think of).
The current density that plating in the step (5) uses is 4ASD.
In the step (5) ten are presoaked before plating copper post three times.
Beneficial effect
Present invention optimizes technological process, reduces packaging cost, reduces chip size, has complied with market to microelectronics
Product is increasingly light, the requirement of thin, short, small and low priceization；Pin spacing is further reduced simultaneously, adds drawing in single chip
Pin number is I/O quantity, meets height precise and tinyization of electronic product, has a good application prospect.
Brief description of the drawings
Fig. 1 is the gluing schematic diagram of the present invention；
Fig. 2 is the product figure of the present invention.
Embodiment
With reference to specific embodiment, the present invention is expanded on further.It should be understood that these embodiments are merely to illustrate the present invention
Rather than limitation the scope of the present invention.In addition, it is to be understood that after the content of the invention lectured has been read, people in the art
Member can make various changes or modifications to the present invention, and these equivalent form of values equally fall within the application appended claims and limited
Scope.
Embodiment 1
1st, clean
The effect of cleaning is to remove the foreign matter of crystal column surface and dirty, mainly including following process：IPA cleanings → QDR water
Wash → SRD dryings → baking oven baking.All process steps 50um copper posts technique and 80-100um copper post techniques are essentially identical during cleaning.
2nd, RPV passivation layers again
RPV can play a part of insulation, against corrosion, buffering stress and planarization, finally will be left in wafer as cushion
Surface, mainly including following process：Plasma etching → gluing → exposure → development → solidification → plasma etching.RPV
When all process steps 50um copper posts technique and 80-100um copper post techniques it is essentially identical.
3rd, SPT is sputtered
SPT effect is sputtering Ti barrier layers and Cu Seed Layers, the effect of conduction is played during plating, mainly including following work
Sequence：Prerinse → baking → sputtering.All process steps 50um copper posts technique and 80-100um copper post techniques are essentially identical during SPT.
4th, PR photoresist layers
Image on mask plate is exactly transferred on silicon wafer as photoresist layer by PR, determine RDL and copper post opening and
Pattern, it will be removed after plating, mainly including following process：Gluing → trimming → exposure → development, as shown in Figure 1.
Compared with 80-100um copper post techniques, 50um copper post technique height of the copper pillar is lower, and copper post is smaller, therefore photoetching
The thickness of glue is relatively thin, and it is abnormal the unclean caused cull of development otherwise easily occur.Gluing mainly includes following three work step：
Spin coating, whirl coating and get rid of side.80-100um copper posts technique is because the photoresist thickness of needs is blocked up, it is necessary to carry out gluing twice, and
The glue amount of gluing is 5ml, and spin coating speed is 1800rpm, time 1s, and the speed of whirl coating is 450rpm, time 25s.
The glue amount of second of gluing is 4ml, and spin coating speed is 1500rpm, time 1s, and the speed of whirl coating is 800rpm, the time is
10s, it is 1500rpm, time 1s to get rid of side speed.50um copper post technique glue thickness glue is thin, therefore need to only carry out a gluing, gluing
Glue amount be 9ml, spin coating speed is 750rpm, time 10s, and whirl coating speed is 350rpm, time 20s, gets rid of side speed and is
500rpm, time 2s.It can be seen that the gluing program of 50um copper post techniques is more simple and efficient.
5th, ECD is electroplated
ECD is the principle using electrolytic cell, and long copper post is with by mounting connection chip internal in the metal openings of chip
Function and external devices, mainly including following process：Plasma etching → ECD is electroplated → removes photoresist → and Cu copper corrosions → Ti titaniums are rotten
Erosion → plasma etching → electric leakage current test.
Compared with 80-100um copper post techniques, the PR CD of 50um copper post techniques are smaller, thus electroplate when electroplate liquid be more difficult into
Enter PR CD, height copper post easily occur, therefore the preimpregnation number before plating need to be increased to ten three times by eight times.Simultaneously because
Height of the copper pillar is lower, therefore more preferable to the uniformity requirement of height of the copper pillar, therefore uses SC28 copper electroplating liquids to be electroplated instead of SC40 copper
Liquid, copper post uniformity is effectively improved by reducing rate of deposition.
The composition and content of SC40 copper electroplating liquids are as follows：Copper 40g/L, sulfuric acid 140g/L, chlorion 50mg/L, brightener
R120ml/L, smoothing agent R2-A 6ml/L, smoothing agent R2-B 6ml/L, the current density used during plating is 8ASD.
The composition and content of SC28 copper electroplating liquids are as follows：Copper 28g/L, sulfuric acid 200g/L, chlorion 40mg/L, brightener MD
5ml/L, smoothing agent LO 3ml/L, the current density used during plating is 4ASD.
6th, RF flows back
RF is by the tin backflow globulate of plating, is easy to rear road to be welded with substrate, mainly including following process：Coating
→ RF flows back → removes scaling powder → shearing force testing.All process steps 50um copper posts technique and 80-100um copper post techniques are basic during RF
It is identical.
7th, AOI outward appearances are examined
AOI is the outward appearance and copper post size and height of the copper pillar of checking chip, and bad chip is carried out into NG on mapping,
Mainly include following process：2D scannings -3D scannings-abnormal chips judgement-AOI mapping generations.All process steps 50um during AOI
Copper post technique and 80-100um copper post techniques are essentially identical.
Claims (6)
1. a kind of method for packing of 50 μm of copper posts, including：
(1) cleaning wafer removes the foreign matter on surface and dirty；
(2) passivation layer is coated again as cushion in crystal column surface；
(3) copper, titanium Seed Layer are sputtered in passivation layer surface again；
(4) photoresist is coated as photoresist layer in copper, titanium seed layer surface；Wherein coating photoresist includes spin coating, whirl coating and gets rid of
Side；
(5) copper post and tin cap are electroplated by ECD；Wherein, copper post is electroplated using SC28 copper electroplating liquids；
(6) finally by the tin backflow globulate of plating.
A kind of 2. method for packing of 50 μm of copper posts according to claim 1, it is characterised in that：Painting in the step (4)
The amount for covering photoresist is 5-10ml.
A kind of 3. method for packing of 50 μm of copper posts according to claim 1, it is characterised in that：It is even in the step (4)
Glue speed is 750-800rpm, spin coating time 10-15s；Whirl coating speed is 350-400rpm, and the whirl coating time is 20-25s；Get rid of
Side speed is 500-600rpm, and it is 2-4s to get rid of the side time.
A kind of 4. method for packing of 50 μm of copper posts according to claim 1, it is characterised in that：In the step (5)
The composition of SC28 copper electroplating liquids is：Copper 26-30g/L, sulfuric acid 150-250g/L, chlorion 30-50mg/L, brightener MD 2-
8ml/L, smoothing agent LO 1-4ml/L.
A kind of 5. method for packing of 50 μm of copper posts according to claim 1, it is characterised in that：Electricity in the step (5)
It is 4ASD to plate the current density used.
A kind of 6. method for packing of 50 μm of copper posts according to claim 1, it is characterised in that：Electroplated in the step (5)
Ten are presoaked before copper post three times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710879079.3A CN107871674A (en) | 2017-09-26 | 2017-09-26 | A kind of method for packing of 50 μm of copper posts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710879079.3A CN107871674A (en) | 2017-09-26 | 2017-09-26 | A kind of method for packing of 50 μm of copper posts |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107871674A true CN107871674A (en) | 2018-04-03 |
Family
ID=61752901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710879079.3A Pending CN107871674A (en) | 2017-09-26 | 2017-09-26 | A kind of method for packing of 50 μm of copper posts |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107871674A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114906798A (en) * | 2022-05-06 | 2022-08-16 | 强一半导体（苏州）有限公司 | Method for growing copper pillars on the surface of package substrate based on MEMS processing technology |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064136A (en) * | 2009-10-29 | 2011-05-18 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| CN102074486A (en) * | 2009-10-20 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Method for forming integrated circuit structure |
| US20170005035A1 (en) * | 2015-06-30 | 2017-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked Semiconductor Devices and Methods of Forming Same |
-
2017
- 2017-09-26 CN CN201710879079.3A patent/CN107871674A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074486A (en) * | 2009-10-20 | 2011-05-25 | 台湾积体电路制造股份有限公司 | Method for forming integrated circuit structure |
| CN102064136A (en) * | 2009-10-29 | 2011-05-18 | 台湾积体电路制造股份有限公司 | Integrated circuit structure |
| US20170005035A1 (en) * | 2015-06-30 | 2017-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked Semiconductor Devices and Methods of Forming Same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114906798A (en) * | 2022-05-06 | 2022-08-16 | 强一半导体（苏州）有限公司 | Method for growing copper pillars on the surface of package substrate based on MEMS processing technology |
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Application publication date: 20180403 |