CN107845679A - A kind of ring grid field effect transistor based on negative capacitance and preparation method thereof - Google Patents

Abstract

The invention provides a gate-all-around field effect transistor based on negative capacitance and a manufacturing method thereof, wherein a ferroelectric material is formed between the high-K dielectric layer and the metal gate layer of the gate structure of the gate-all-around field effect transistor based on negative capacitance layer; the layer of ferroelectric material has a negative capacitance. The ferroelectric material layer with negative capacitance acts as a built-in voltage amplifier, which can reduce the subthreshold swing of the device to the following. Moreover, the transistor uses Si nanowires as the channel material, and the high-K metal gate fully surrounds the Si nanowires, which can obtain better gate control capability and avoid short channel effects. The manufacturing method of the gate-around field effect transistor based on the negative capacitance of the present invention has simple manufacturing process and is beneficial to reduce the production cost.

Description

A gate-all-round field effect transistor based on negative capacitance and its manufacturing method

technical field

The invention belongs to the field of semiconductor manufacturing, and relates to a ring gate field effect transistor based on negative capacitance and a manufacturing method thereof.

Background technique

Conventional FETs require at least a 60mV change in gate voltage at 300K to produce a 10-fold (an order of magnitude) change in current. The minimum subthreshold slope determines the basic lower operating voltage.

Figure 1 shows a schematic diagram of the structure of an existing field effect transistor, where S represents the source region, D represents the drain region, Channel represents the channel region, oxide represents the gate oxide layer, G represents the gate, and V _gs represents the gate Source voltage, V _ds represents the source-drain voltage, and t _ox represents the thickness of the gate oxide layer.

Fig. 2 shows the longitudinal circuit schematic diagram of the structure shown in Fig. 1, where C _ox represents the gate oxide layer capacitance, C _s represents the channel capacitance, V _g represents the gate voltage, is the potential of the silicon surface.

A key factor limiting the operating voltage is the subthreshold swing S, which satisfies:

Among them, dV _gs represents the gate-source voltage change, I _d is the source-drain current, d(log ₁₀ I _d ) represents the magnitude of the source current change, Represents the change of silicon surface potential, and decade represents the order of magnitude.

Since C _s and C _ox are usually positive values, making Greater than 1. However, reducing the gate oxide thickness (t _ox ) and using high-K dielectrics can only make As close to 1 as possible, but can not make it reach 1 or less than 1, so the limit value of S is about 60mV/decade.

Nanowire-based devices offer a new option for next-generation integrated circuits. Nanowire-based gate-all-around field-effect transistors have perfect gate control and can effectively suppress short-channel effects. However, the manufacturing process of the nanowires in the prior art is complicated and the cost is high.

Therefore, how to provide a negative capacitance-based gate-all-round field effect transistor and its manufacturing method to further reduce the subthreshold swing, effectively suppress the short channel effect, and reduce costs has become an important technology to be solved urgently by those skilled in the art. question.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a negative capacitance-based gate-all-round field effect transistor and its manufacturing method, which are used to solve the problem of high subthreshold swing and manufacturing process of field effect transistors in the prior art. complicated question.

In order to achieve the above object and other related objects, the present invention provides a negative capacitance-based gate-all-around field effect transistor. A ferroelectric material layer is formed; the ferroelectric material layer has a negative capacitance.

Optionally, the material of the ferroelectric material layer includes one or more of HfZrO ₂ , PZT, SBT, BRT, and NBT.

Optionally, the thickness of the ferroelectric material layer is in the range of 5-10 nm.

Optionally, the gate-all-around field effect transistor includes a Si nanowire; the high-K dielectric layer surrounds the surface of the Si nanowire; the ferroelectric material layer surrounds the surface of the high-K dielectric layer; the metal The gate layer surrounds the surface of the ferroelectric material layer.

Optionally, the Si nanowires are cylindrical Si nanowires or polygonal cylindrical Si nanowires, and the diameter of the cylindrical nanowires is 50-90 nm.

Optionally, the gate-all-around field effect transistor further includes:

sidewall structures formed on both sides of the gate region structure;

A source region and a drain region are respectively formed on two sides of the gate region structure, and both the source region and the drain region are in contact with the Si layer where the Si nanowire is located.

Optionally, the source region and the drain region include a TiN/Al composite layer.

Optionally, the metal gate layer includes a TiN/Al composite layer.

The present invention also provides a method for manufacturing a gate-all-around field effect transistor based on negative capacitance, comprising the following steps:

S1: providing an SOI substrate sequentially including a Si substrate, an insulating buried layer and a top layer of silicon from bottom to top;

S2: patterning the top layer of silicon, forming at least one Si nanowire in the top layer of silicon;

S3: Etching away at least a part of the insulating buried layer located under the Si nanowires, so as to release the Si nanowires;

S4: Form a surrounding high-K dielectric layer, a ferroelectric material layer, and a metal gate layer sequentially on the surface of the Si nanowire; the high-K dielectric layer, ferroelectric material layer, and metal gate layer constitute a gate structure of a transistor; The ferroelectric material layer has a negative capacitance.

Optionally, also include the steps:

S5: making sidewall structures on both sides of the gate structure;

S6: Forming a source region and a drain region on both sides of the gate structure; both the source region and the drain region are in contact with the Si layer where the Si nanowire is located.

Optionally, in the step S3, when the buried insulating layer under the Si nanowires is etched to release the Si nanowires, a preset thickness of the buried insulating layer is retained.

Optionally, in the step S3, when the insulating buried layer under the Si nanowires is etched to release the Si nanowires, the Si substrate is exposed, and the exposed Si substrate surface An insulating layer of a predetermined thickness is formed.

Optionally, in the step S3, further comprising the step of oxidizing the surface of the Si nanowire, removing the oxide layer on the surface of the Si nanowire, and repeating the steps of oxidation and removal of the oxide layer at least once to obtain a cylindrical Si Nanowires.

Optionally, the diameter of the cylindrical Si nanowire is 50-90 nm.

Optionally, the material of the ferroelectric material layer includes one or more of HfZrO ₂ , PZT, SBT, BRT, and NBT.

Optionally, the thickness of the ferroelectric material layer is in the range of 5-10 nm.

Optionally, the source region and the drain region include a TiN/Al composite layer.

Optionally, the metal gate layer includes a TiN/Al composite layer.

As mentioned above, the negative capacitance-based gate-all-around field effect transistor and its manufacturing method of the present invention have the following beneficial effects: the present invention forms a A layer of ferroelectric material; the layer of ferroelectric material has a negative capacitance. The ferroelectric material layer with negative capacitance acts as a built-in voltage amplifier, which can reduce the subthreshold swing of the device to below 60mV/decade. The manufacturing method of the gate-around field effect transistor based on the negative capacitance of the present invention has simple manufacturing process and is beneficial to reduce the production cost.

Description of drawings

FIG. 1 is a schematic structural diagram of a field effect transistor in the prior art.

FIG. 2 shows a vertical circuit schematic diagram of the structure shown in FIG. 1 .

FIG. 3 is a graph showing the charge density per unit area of a conventional gate oxide layer as a function of voltage.

Fig. 4 is a graph showing the charge density per unit area of ferroelectric materials as a function of voltage.

FIG. 5 is a schematic structural diagram of a gate-all-around field effect transistor based on a negative capacitance of the present invention on a first cross-section.

FIG. 6 is a schematic structural diagram of a gate-all-around field effect transistor based on a negative capacitance of the present invention on a second cross-section.

FIG. 7 is a vertical circuit schematic diagram of the negative capacitance-based gate-all-around field effect transistor of the present invention.

FIG. 8 shows a schematic structural view of the SOI substrate provided for the fabrication method of the negative capacitance-based gate-all-around field effect transistor of the present invention.

FIG. 9 shows a schematic diagram of patterning the top layer of silicon and forming Si nanowires in the top layer of silicon for the fabrication method of the negative capacitance-based gate-all-around field effect transistor of the present invention.

Fig. 10 is a cross-sectional view of the structure shown in Fig. 9 along A-A' direction.

Fig. 11 is a B-B' sectional view of the structure shown in Fig. 9 .

FIG. 12 is a schematic diagram showing that at least a part of the insulating buried layer under the Si nanowires is etched away to release the Si nanowires in the fabrication method of the gate-all-around field effect transistor based on the negative capacitance of the present invention.

Fig. 13 is a cross-sectional view of the structure shown in Fig. 12 along A-A' direction.

Fig. 14 shows a B-B' cross-sectional view of the structure shown in Fig. 12 .

FIG. 15 is a schematic diagram of oxidation of the surface of the Si nanowires for the fabrication method of the gate-all-around field effect transistor based on the negative capacitance of the present invention.

FIG. 16 shows a schematic diagram of removing the oxide layer on the surface of the Si nanowires to obtain cylindrical Si nanowires for the fabrication method of the gate-all-around field effect transistor based on the negative capacitance of the present invention.

17-18 are schematic diagrams of forming a high-K dielectric layer surrounding the surface of the Si nanowire for the fabrication method of the negative capacitance-based gate-all-around field effect transistor of the present invention.

19-20 are schematic diagrams of forming a ferroelectric material layer surrounding the surface of the high-K dielectric layer for the fabrication method of the negative capacitance-based gate-all-around field effect transistor of the present invention.

Component designation description

1 Si substrate

2 insulating buried layer

3 top silicon

4 Si nanowires

5 insulating layers

6 High K dielectric layer

7 ferroelectric material layer

8 metal gate layer

9 side wall structure

10 source area

11 Drain area

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 3 through 20. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Embodiment one

The present invention provides a gate-all-around field effect transistor based on negative capacitance, wherein a ferroelectric material layer is formed between the high-K dielectric layer and the metal gate layer of the gate structure of the gate-all-around field effect transistor based on negative capacitance; The layer of ferroelectric material has a negative capacitance.

Specifically, a ferroelectric material refers to a dielectric material that has spontaneous polarization within a certain temperature range, and the direction of the spontaneous polarization can be changed by changing the direction of an applied electric field.

As an example, the material of the ferroelectric material layer includes HfZrO ₂ (zirconium hafnium oxide), PZT (lead zirconate titanate, chemical formula is Pb(Zr,Ti)O ₃ ), SBT (strontium bismuth tantalate, chemical formula is SrBi ₂ TaO ₉ ), BRT ((Bi,R) ₄ Ti ₃ O ₁₂ ) obtained by doping rare earth elements R such as La, Nd, etc.), NBT (sodium bismuth titanate, chemical formula (NaBi)TiO) one or more species. The thickness range of the ferroelectric material layer is 5-10 nm.

FIG. 3 is a graph showing the variation of the charge density Q per unit area of a conventional gate oxide layer with the voltage V _ox . Figure 4 is a graph showing the change of the charge density per unit area Q of the ferroelectric material with the voltage _Vfe . Among them, the capacitance of the material layer satisfies From the curve, it is expressed as the slope of the curve.

It can be seen that there is a linear relationship between Q and the voltage V _ox in FIG. 3 , and the slope of the line is positive, indicating that the conventional gate oxide layer has a positive capacitance. In Fig. 4, the relationship between Q and voltage V _fe is nonlinear, and the slope of the curve is negative (as shown by the dotted line in Fig. 4 ). Therefore, the capacitance of the ferroelectric material satisfies have negative capacitance.

As an example, please refer to FIG. 5 and FIG. 6, which are respectively shown as structural schematic diagrams of a gate-all-around field-effect transistor based on a negative capacitance of the present invention on the first cross-section and the second cross-section, and the gate-all-around field effect transistor includes Si nanowires 4; the high-K dielectric layer 6 surrounds the surface of the Si nanowire 4; the ferroelectric material layer 7 surrounds the surface of the high-K dielectric layer 6; the metal gate layer 8 surrounds the ferroelectric material Layer 7 surface. The Si nanowire 4 is used as a channel of a gate-around field effect transistor.

In this embodiment, the gate-all-around field effect transistor based on negative capacitance is manufactured based on an SOI substrate, and the SOI substrate includes a Si substrate 1 , an insulating buried layer 2 and a top layer of silicon in sequence from bottom to top. The insulating buried layer 2 is made of silicon oxide. The Si nanowires 4 are obtained by patterning the top silicon.

The Si nanowires may be cylindrical Si nanowires or polygonal cylindrical Si nanowires. In this embodiment, the Si nanowires are preferably cylindrical Si nanowires with a diameter of 50-90 nm. The cylindrical nanowire structure is more symmetrical, which is beneficial to obtain better gate control effect.

Further, the gate-around field effect transistor further includes: sidewall structures 9 formed on both sides of the gate structure, and source regions 10 and drain regions 11 respectively formed on both sides of the gate structure, and the Both the source region 10 and the drain region 11 are in contact with the Si layer where the Si nanowires are located.

As an example, the source region 10 and the drain region 11 include a TiN/Al composite layer, wherein the TiN layer is located between the Si layer and the Al layer. A good ohmic contact can be formed between the TiN/Al composite layer and the Si layer, so there is no need to form an additional heavily doped layer. In this embodiment, the metal gate layer 8 is also preferably a TiN/Al composite layer.

Please refer to FIG. 7 , which is a vertical circuit schematic diagram of the negative capacitance-based gate-all-around field effect transistor of the present invention. It can be seen that the ferroelectric material layer 7 is formed between the high-K dielectric layer 6 and the metal gate layer 8, which is equivalent to connecting a negative capacitance in series between the high-K dielectric layer 6 and the metal gate layer 8, thus satisfying When the absolute value of C _Fe is greater than C _ox , C _ox + C _Fe is less than 0, making thus making That is, the negative capacitance-based gate-all-round field effect transistor of the present invention can reduce the subthreshold swing of the device to below 60mV/decade.

At the same time, the negative capacitance-based gate-all-around field effect transistor of the present invention uses Si nanowires as channel materials, and the high-K metal gate completely surrounds the Si nanowires, which can obtain better gate control ability and avoid short channel effects. Both the source region and the drain region of the transistor use a TiN/Al composite layer, without the need to form an additional heavily doped layer, and the structure is simpler.

Embodiment two

The present invention also provides a method for manufacturing a gate-all-around field effect transistor based on negative capacitance, comprising the following steps:

Step S1 is first performed: as shown in FIG. 8 , an SOI substrate including a Si substrate 1 , an insulating buried layer 2 and a top layer of silicon 3 is provided sequentially from bottom to top.

As an example, the insulating buried layer 2 is made of silicon oxide, and its thickness ranges from 150-350 nm. The thickness range of the top layer silicon 3 is 50-90nm.

Then step S2 is performed: as shown in FIGS. 9-11 , pattern the top layer of silicon 3 , and form at least one Si nanowire 4 in the top layer of silicon 3 . Wherein, Fig. 9 shows the top view of the structure obtained in this step, Fig. 10 shows the A-A' direction sectional view of the structure shown in Fig. 9, and Fig. 11 shows the B-B' direction sectional view of the structure shown in Fig. 9 .

Specifically, photolithography and ICP dry etching processes are used to pattern the top silicon 3 to obtain the Si nanowires 4 .

Then step S3 is performed: as shown in FIGS. 12-14 , at least a part of the insulating buried layer under the Si nanowire 4 is etched away, so as to release the Si nanowire 4 . Wherein, Fig. 12 shows the top view of the structure obtained in this step, Fig. 13 shows the A-A' direction sectional view of the structure shown in Fig. 12, and Fig. 14 shows the B-B' direction sectional view of the structure shown in Fig. 12.

Specifically, a wet etching process is used to remove the insulating buried layer to release the Si nanowires. The etching solution used in the wet etching process includes hydrofluoric acid solution.

Specifically, when the buried insulating layer located under the Si nanowires is etched to release the Si nanowires, the buried insulating layer with a preset thickness can be retained, or the Si substrate can be exposed, and the exposed Si substrate can be exposed. An insulating layer 5 with a predetermined thickness is formed on the surface of the Si substrate. The insulating layer 5 can be obtained by thermally oxidizing the Si substrate.

This step may further include the step of oxidizing the surface of the Si nanowire, removing the oxide layer on the surface of the Si nanowire, and repeating the oxidation and removal of the oxide layer at least once to obtain a cylindrical Si nanowire. Wherein, FIG. 15 is a schematic diagram showing the oxidation of the surface of the Si nanowire by the method for fabricating the gate-all-around field effect transistor based on the negative capacitance of the present invention. FIG. 16 shows a schematic diagram of removing the oxide layer on the surface of the Si nanowires to obtain cylindrical Si nanowires for the fabrication method of the gate-all-around field effect transistor based on the negative capacitance of the present invention.

As an example, the cylindrical Si nanowires have a diameter of 50-90 nm. The cylindrical nanowire structure is more symmetrical, which is beneficial to obtain better gate control effect.

Then perform step S4: as shown in Figures 17-20 and Figures 5-6, form a surrounding high-K dielectric layer 6, a ferroelectric material layer 7, and a metal gate layer 8 on the surface of the Si nanowire 4 in sequence; The high-K dielectric layer 6, the ferroelectric material layer 7 and the metal gate layer 8 constitute the gate region structure of the transistor; the ferroelectric material layer 7 has a negative capacitance. 17-18 are schematic diagrams showing the formation of the high-K dielectric layer 6 surrounding the surface of the Si nanowire 4 for the fabrication method of the gate-all-around field effect transistor based on the negative capacitance of the present invention. 19-20 are schematic diagrams showing the formation of the ferroelectric material layer 7 surrounding the surface of the high-K dielectric layer 6 for the fabrication method of the gate-all-around field effect transistor based on the negative capacitance of the present invention. 5-6 are schematic diagrams of forming a metal gate layer 8 surrounding the surface of the ferroelectric material layer 7 for the fabrication method of the negative capacitance-based gate-all-around field effect transistor of the present invention.

Specifically, adopt atomic layer deposition (ALD), chemical vapor deposition (CVD) or physical vapor deposition (PVD) to form the high-K dielectric layer (dielectric constant K is higher than the dielectric constant of silicon dioxide 3.9) . The material of the high-K dielectric layer includes but not limited to metal oxides, nitrides and the like. In this embodiment, the high-K dielectric layer 6 is preferably made of HfO ₂ , and the thickness of the high-K dielectric layer 6 is in the range of 10-20 nm.

Specifically, the material of the ferroelectric material layer 7 includes HfZrO ₂ (zirconium hafnium oxide), PZT (lead zirconate titanate, chemical formula is Pb(Zr,Ti)O ₃ ), SBT (strontium bismuth tantalate, chemical formula is SrBi ₂ TaO ₉ ), BRT ((Bi,R) ₄ Ti ₃ O ₁₂ ) obtained by doping rare earth elements R such as La, Nd, etc.), NBT (sodium bismuth titanate, chemical formula (NaBi)TiO) one or more species. The thickness range of the ferroelectric material layer is 5-10 nm.

In this embodiment, the ferroelectric material layer 7 is preferably made of HfZrO ₂ , and its preparation method includes any one of atomic layer deposition (ALD), chemical vapor deposition (CVD) or physical vapor deposition (PVD). kind.

In the present invention, a ferroelectric material layer with negative capacitance is formed between the high-K dielectric layer and the metal gate layer, and the ferroelectric material layer with negative capacitance is used as a built-in voltage amplifier, which can reduce the subthreshold swing of the device to 60mV/decade the following.

Further, step S5 is performed: as shown in FIG. 5 , forming sidewall structures 9 on both sides of the gate structure.

Further, step S6 is performed: as shown in FIG. 5 , respectively forming a source region 10 and a drain region 11 on both sides of the gate region structure.

Specifically, the source region 10 , the drain region 11 and the metal gate layer 8 all preferably include a TiN/Al composite layer.

So far, a gate-all-round field effect transistor based on negative capacitance has been produced, and a ferroelectric material layer is formed between the high-K dielectric layer and the metal gate layer of the transistor gate structure; the ferroelectric material layer has negative capacitance and can be used as The built-in voltage amplifier can reduce the subthreshold swing of the device to less than 60mV/decade. Moreover, the transistor uses Si nanowires as the channel material, and the high-K metal gate fully surrounds the Si nanowires, which can obtain better gate control capability and avoid short channel effects. Both the source region and the drain region of the transistor use a TiN/Al composite layer, without forming an additional heavily doped layer, the structure is simpler, and the manufacturing process is simpler, which is beneficial to reduce production costs.

In summary, the negative capacitance-based gate-all-around field effect transistor of the present invention has a ferroelectric material layer formed between the high-K dielectric layer and the metal gate layer of the gate region structure of the gate-all-around field effect transistor; the ferroelectric material layer have negative capacitance. The ferroelectric material layer with negative capacitance acts as a built-in voltage amplifier, which can reduce the subthreshold swing of the device to below 60mV/decade. The manufacturing method of the gate-around field effect transistor based on the negative capacitance of the present invention has simple manufacturing process and is beneficial to reduce the production cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (18)

1. A kind of 1. ring grid field effect transistor based on negative capacitance, it is characterised in that：The ring gate field-effect based on negative capacitance Formed with ferroelectric material layer between the high-K dielectric layer and Metal gate layer of the grid region structure of transistor；The ferroelectric material layer has Negative capacitance.
2. 2. the ring grid field effect transistor according to claim 1 based on negative capacitance, it is characterised in that：The ferroelectric material The material of layer includes HfZrO₂, one or more in PZT, SBT, BRT, NBT.
3. 3. the ring grid field effect transistor according to claim 1 based on negative capacitance, it is characterised in that：The ferroelectric material The thickness range of layer is 5-10nm.
4. 4. the ring grid field effect transistor based on negative capacitance according to claim 1-3 any one, it is characterised in that institute Stating ring grid field effect transistor includes Si nano wires；The high-K dielectric layer is surrounded on the Si nanowire surfaces；The ferroelectricity material The bed of material is surrounded on the high-K dielectric layer surface；The Metal gate layer is surrounded on the ferroelectric material layer surface.
5. 5. the ring grid field effect transistor according to claim 4 based on negative capacitance, it is characterised in that：The Si nano wires For cylinder Si nano wires or polygon cylinder Si nano wires, a diameter of 50-90nm of the cylinder nano wire.
6. 6. the ring grid field effect transistor according to claim 4 based on negative capacitance, it is characterised in that the ring grid field effect Transistor is answered also to include：

   Sidewall structure, it is formed at the grid region structure both sides；

   Source region and drain region, are respectively formed in the grid region structure both sides, and the source region and drain region with the Si nano wires institute Contacted in Si layers.
7. 7. the ring grid field effect transistor according to claim 6 based on negative capacitance, it is characterised in that：The source region and leakage Area includes TiN/Al composite beds.
8. 8. the ring grid field effect transistor according to claim 1 based on negative capacitance, it is characterised in that：The Metal gate layer Including TiN/Al composite beds.
9. 9. a kind of preparation method of the ring grid field effect transistor based on negative capacitance, it is characterised in that comprise the following steps：

   S1：There is provided one includes the SOI substrate of Si substrates, insulating buried layer and top layer silicon successively from bottom to top；

   S2：The graphical top layer silicon, forms an at least Si nano wire in the top layer silicon；

   S3：At least a portion insulating buried layer below the Si nano wires is eroded, to discharge the Si nano wires；

   S4：Circular high-K dielectric layer, ferroelectric material layer and Metal gate layer are sequentially formed in the Si nanowire surfaces；The high K Dielectric layer, ferroelectric material layer and Metal gate layer form the grid region structure of transistor；The ferroelectric material layer has negative capacitance.
10. 10. the preparation method of the ring grid field effect transistor according to claim 9 based on negative capacitance, it is characterised in that Also include step：

    S5：Sidewall structure is made in the grid region structure both sides；

    S6：Source region and drain region are made respectively in the grid region structure both sides；The source region and drain region with the Si nano wires institute Contacted in Si layers.
11. 11. the preparation method of the ring grid field effect transistor according to claim 9 based on negative capacitance, it is characterised in that： In the step S3, when insulating buried layer of the corrosion below the Si nano wires discharges the Si nano wires, retain The insulating buried layer of preset thickness.
12. 12. the preparation method of the ring grid field effect transistor according to claim 9 based on negative capacitance, it is characterised in that： In the step S3, when insulating buried layer of the corrosion below the Si nano wires discharges the Si nano wires, exposure Go out the Si substrates, and the insulating barrier of preset thickness is formed in the Si substrate surfaces exposed.
13. 13. the preparation method of the ring grid field effect transistor according to claim 9 based on negative capacitance, it is characterised in that： In the step S3, in addition to the step of oxidation Si nanowire surfaces, oxide layer of the removal Si nanowire surfaces, And repeated oxidation and go removing oxide layer step at least once, to obtain cylinder Si nano wires.
14. 14. the preparation method of the ring grid field effect transistor according to claim 13 based on negative capacitance, it is characterised in that： A diameter of 50-90nm of the cylinder Si nano wires.
15. 15. the preparation method of the ring grid field effect transistor according to claim 9 based on negative capacitance, it is characterised in that： The material of the ferroelectric material layer includes HfZrO₂, one or more in PZT, SBT, BRT, NBT.
16. 16. the preparation method of the ring grid field effect transistor according to claim 9 based on negative capacitance, it is characterised in that： The thickness range of the ferroelectric material layer is 5-10nm.
17. 17. the preparation method of the ring grid field effect transistor according to claim 9 based on negative capacitance, it is characterised in that： The source region includes TiN/Al composite beds with drain region.
18. 18. the preparation method of the ring grid field effect transistor according to claim 9 based on negative capacitance, it is characterised in that： The Metal gate layer includes TiN/Al composite beds.