CN107833924B - Top-gate thin film transistor and preparation method thereof, array substrate and display panel - Google Patents

Abstract

The present disclosure provides a top-gate thin film transistor and a preparation method thereof, an array substrate and a display panel, and relates to the technical field of display. The preparation method of the top-gate thin film transistor includes: preparing a second gate insulating layer on a substrate formed with a semiconductor active layer, a source electrode and a drain electrode, a first gate insulating layer, and a first gate electrode, and forming a second gate insulating layer on the substrate. An etching protection layer is formed over the second gate insulating layer; the substrate on which the second gate insulating layer and the etching protection layer are formed is placed in a hydrofluoric acid cleaning device for oxidation treatment and hydrofluoric acid cleaning to The etching protection layer is removed during the hydrofluoric acid cleaning process; and a second gate electrode is prepared on the substrate after the hydrofluoric acid cleaning. The present disclosure can improve the surface damage caused by cleaning the gate insulating layer with hydrofluoric acid, thereby ensuring the electrical performance of the thin film transistor and the stability of the subsequent process.

Description

Top-gate thin film transistor and preparation method thereof, array substrate and display panel

technical field

The present disclosure relates to the field of display technology, and in particular, to a top-gate thin film transistor and a preparation method thereof, an array substrate and a display panel.

Background technique

With the rapid development of semiconductor technology, LTPS (Low Temperature Poly-silicon, low-temperature polysilicon) backplane technology has the advantages of high mobility, high aperture ratio, and GOA (Gate Driver on Array, array substrate row drive), etc. Compared with the display panel based on a-Si (amorphous silicon) technology, the display panel based on LTPS technology has better display effect, so it has received more and more extensive attention.

Nowadays, people have higher and higher resolution requirements for displays, and high PPI (Pixels Per Inch, pixels per inch) displays are a great challenge to the existing LTPS process. In the LTPS process, there will be a process step of etching the gate insulating layer. This step requires hydrofluoric acid (HF) cleaning of the gate insulating layer, but the cleaning process will inevitably have a certain impact on the gate insulating layer. This results in thinning of the gate insulating layer, and even a risk of short circuit at the slope, thereby affecting the stability of the subsequent process and the electrical characteristics of a TFT (Thin Film Transistor, thin film transistor).

It should be noted that the information disclosed in the above Background section is only for enhancement of understanding of the background of the present disclosure, and therefore may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

SUMMARY OF THE INVENTION

The purpose of the present disclosure is to provide a top-gate thin film transistor and a method for fabricating the same, an array substrate, and a display panel, thereby at least to a certain extent overcoming one or more problems caused by limitations and defects of the related art.

Other features and advantages of the present disclosure will become apparent from the following detailed description, or be learned in part by practice of the present disclosure.

According to one aspect of the present disclosure, there is provided a method for fabricating a top-gate thin film transistor, comprising:

A second gate insulating layer is prepared on the substrate formed with the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode, and an etching protection layer is formed over the second gate insulating layer ;

The substrate on which the second gate insulating layer and the etching protection layer are formed is placed in a hydrofluoric acid cleaning device for oxidation treatment and hydrofluoric acid cleaning, so as to remove the etching protective layer;

A second gate electrode is prepared on the substrate after the hydrofluoric acid cleaning.

In an exemplary embodiment of the present disclosure, forming an etch protection layer over the second gate insulating layer includes:

An amorphous silicon film is formed over the second gate insulating layer.

In an exemplary embodiment of the present disclosure, placing the substrate on which the second gate insulating layer and the etch protection layer are formed for oxidation treatment in a hydrofluoric acid cleaning device includes:

The substrate on which the second gate insulating layer and the amorphous silicon film are formed is placed in a hydrofluoric acid cleaning device for ozone oxidation treatment, so that the amorphous silicon film is converted into a silicon oxide film.

In an exemplary embodiment of the present disclosure, forming an etch protection layer over the second gate insulating layer includes:

A silicon oxide film is formed over the second gate insulating layer.

In an exemplary embodiment of the present disclosure, the thickness of the etching protection layer is

In an exemplary embodiment of the present disclosure, the second gate insulating layer and the etching protection layer are prepared in the same thin film deposition equipment.

In an exemplary embodiment of the present disclosure, preparing the second gate insulating layer on the substrate formed with the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode includes:

One or more of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film are formed on the substrate on which the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode are formed .

In an exemplary embodiment of the present disclosure, the substrate formed with a semiconductor active layer, source and drain electrodes, a first gate insulating layer, and a first gate electrode includes:

substrate substrate;

a source electrode and a drain electrode formed above the base substrate;

a semiconductor active layer formed over the source electrode and the drain electrode;

a first gate insulating layer formed over the semiconductor active layer; and,

a first gate formed over the first gate insulating layer.

In an exemplary embodiment of the present disclosure, the substrate formed with the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode further includes:

The buffer layer is formed on the side of the base substrate facing the semiconductor active layer.

According to one aspect of the present disclosure, there is provided a top-gate thin film transistor prepared by using the above-mentioned preparation method.

According to an aspect of the present disclosure, there is provided an array substrate including the above-mentioned top-gate thin film transistor.

According to an aspect of the present disclosure, there is provided a display panel including the above-mentioned top-gate thin film transistor.

In the top-gate thin film transistor and the method for fabricating the same provided by the exemplary embodiments of the present disclosure, an etching protection layer is formed on the surface of the second gate insulating layer before the hydrofluoric acid cleaning is performed, and the etching protection layer is formed thereon. The substrate is placed in a hydrofluoric acid cleaning device for cleaning. In this way, in the hydrofluoric acid cleaning device, the etching protection layer will be oxidized to form an oxide film, and the oxide film will protect the second gate insulating layer below it during the hydrofluoric acid cleaning Therefore, the second gate insulating layer is prevented from being excessively thinned by hydrofluoric acid etching, thereby improving the surface damage of the second gate insulating layer, thereby ensuring the electrical performance of the thin film transistor and improving the stability of the subsequent process. .

It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 schematically shows a schematic structural diagram of a thin film transistor in an exemplary embodiment of the present disclosure;

Fig. 2 schematically shows the surface damage data caused by cleaning the gate insulating layer under different conditions with hydrofluoric acid in the prior art;

Fig. 3 schematically shows the scanning analysis test chart of the top of the gate insulating layer before hydrofluoric acid cleaning in the prior art;

Fig. 4 schematically shows the scanning analysis test diagram at the ramp of the gate insulating layer before hydrofluoric acid cleaning in the prior art;

Fig. 5 schematically shows the scanning analysis test chart of the gate insulating layer after hydrofluoric acid cleaning in the prior art;

FIG. 6 schematically shows a flow chart of a method for fabricating a thin film transistor in an exemplary embodiment of the present disclosure;

FIG. 7 to FIG. 9 are schematic diagrams illustrating the fabrication process of the thin film transistor in the exemplary embodiment of the present disclosure.

Detailed ways

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed. In other instances, well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The thicknesses and shapes of the layers in the drawings do not reflect true scale, but are only for convenience of illustrating the present disclosure. The same reference numerals in the drawings denote the same or similar parts, and thus their repeated descriptions will be omitted.

This example embodiment provides a thin film transistor, which is a double top-gate transistor. FIG. 1 is a schematic structural diagram of the double top-gate thin film transistor. The structure of the thin film transistor 10 may mainly include:

A base substrate 101, the base substrate 101 may be a glass substrate or a flexible substrate;

The buffer layer 102 located above the base substrate 101, the buffer layer 102 may be a single-layer structure or a multi-layer structure;

The source electrode 103 and the drain electrode 104 above the buffer layer 102 , and the semiconductor active layer 105 . below;

The first gate insulating layer 106 and the first gate electrode 107 located above the source electrode 103 and the drain electrode 104 and the semiconductor active layer 105, the first gate insulating layer 106 may include a silicon nitride film, a silicon oxide film, an oxynitride One or more of silicon film, aluminum oxide film, and hafnium oxide film, which can be a single-layer structure or a multi-layer composite structure;

A second gate insulating layer 108 and a second gate electrode 109 located over the first gate insulating layer 106 and the first gate electrode 107, the second gate insulating layer 108 may include a silicon nitride film, a silicon oxide film, and a silicon oxynitride One or more of the films, which can be a single-layer structure or a multi-layer composite structure;

and a protective layer 110 over the second gate insulating layer 108 and the second gate electrode 109 .

It should be noted that: in the preparation process of the above-mentioned thin film transistor, specifically after the formation of the second gate insulating layer 108 and before the formation of the second gate electrode 109, it is necessary to perform a HF cleaning with hydrofluoric acid. That is, the substrate is placed in a hydrofluoric acid cleaning device, and sequentially undergoes a process of ozone O ₃ oxidation treatment, hydrofluoric acid HF cleaning, and ozone O ₃ oxidation treatment, in order to uniformly oxidize the semiconductor active layer 105, so that the The crystallization in the subsequent ELA (Excimer Laser Annealing, excimer laser crystallization) process is more uniform.

和

的情况下，无论采用何种刻蚀方式，在顶部和爬坡处的膜层均有

左右的减薄。However, the hydrofluoric acid cleaning will inevitably cause certain damage to the surface of the second gate insulating layer 108 . Among them, FIG. 2 shows the surface damage data of the second gate insulating layer 108 caused by the hydrofluoric acid cleaning under different conditions through experiments. The different conditions described here may be, for example, different thicknesses of the gate insulating layer, different gate etching methods (wet WET etching and inductively coupled plasma ICP etching), and the like. From this, it can be seen that the film thickness of the second gate insulating layer 108 is

and

In the case of , no matter what etching method is used, the film layer on the top and the climb has

Thinning around.

左右。在进行氢氟酸清洗之后，如图5所示，第二栅绝缘层108进行扫描分析测试结果显示，第二栅绝缘层108在爬坡处和顶部的厚度均减薄

左右。A specific example is given below. Before performing the hydrofluoric acid cleaning, as shown in FIG. 3 and FIG. 4 , the scanning analysis test results of the second gate insulating layer 108 show that the thickness of the second gate insulating layer 108 at the slope is smaller than that at the top

about. After cleaning with hydrofluoric acid, as shown in FIG. 5 , the scanning analysis and test results of the second gate insulating layer 108 show that the thicknesses of the second gate insulating layer 108 at the slope and the top are reduced.

about.

在此基础上，由于a-Si晶化后得到的p-Si在晶界处会有一定的凸起，因此会使爬坡处存在短路的风险。In this way, for the top position of the second gate insulating layer 108, the thinned film will have a certain influence on the electrical characteristics of the TFT device during operation; and for the originally thin climbing position, such thinning The amount will bring the risk of short circuit, thus affecting the stability of the subsequent process. Specifically, the thickness of the second gate insulating layer 108 deposited at the slope is reduced to a certain extent, and further thinning will occur after the hydrofluoric acid cleaning. The combined effect of these two thinnings makes the slope climb. The thinning amount at the

On this basis, since the p-Si obtained after crystallization of a-Si will have a certain bulge at the grain boundary, there will be a risk of short circuit at the climb.

Based on this, the present exemplary embodiment provides a method for fabricating a thin film transistor, which is used for fabricating a double top-gate thin film transistor with the above structure. As shown in FIG. 6 , the preparation method of the thin film transistor 10 may include:

S1. Referring to FIG. 7, a second gate insulating layer 108 is prepared on the substrate on which the source electrode 103 and the drain electrode 104, the semiconductor active layer 105, the first gate insulating layer 106, and the first gate electrode 107 are formed, and forming an etching protection layer 200 over the second gate insulating layer 108;

S2. Referring to FIG. 8 , place the substrate on which the second gate insulating layer 108 and the etch protection layer 200 are formed into a hydrofluoric acid cleaning device for oxidation treatment and hydrofluoric acid cleaning, so that in the process of hydrofluoric acid cleaning removing the etching protection layer 200;

S3. Referring to FIG. 9, a second gate electrode 109 is prepared on the substrate after being cleaned with hydrofluoric acid.

Wherein, the hydrofluoric acid cleaning device may include an oxidation treatment unit, a hydrofluoric acid cleaning unit, and an oxidation treatment unit which are connected in sequence.

In the preparation method of the thin film transistor provided by the exemplary embodiment of the present disclosure, before the hydrofluoric acid cleaning is performed on the second gate insulating layer 108, an etching protection layer 200 is formed on the surface thereof, and the etching protection layer 200 is formed on the surface of the second gate insulating layer 108. The substrate is placed in a hydrofluoric acid cleaning device for cleaning. In this way, in the hydrofluoric acid cleaning device, the etching protection layer 200 will be oxidized to form an oxide film, and the oxide film will play a role in the second gate insulating layer 108 below it during the hydrofluoric acid cleaning. The protective effect prevents the second gate insulating layer 108 from being excessively thinned by hydrofluoric acid etching, thereby improving the surface damage of the second gate insulating layer 108, thereby ensuring the electrical performance of the thin film transistor 10 and improving the subsequent Process stability.

The manufacturing method of the thin film transistor in this exemplary embodiment will be described in detail below with reference to the accompanying drawings.

In step S1, referring to FIG. 7, a second gate insulating layer is prepared on the substrate on which the source electrode 103 and the drain electrode 104, the semiconductor active layer 105, the first gate insulating layer 106, and the first gate electrode 107 are formed 108 , and an etching protection layer 200 is formed over the second gate insulating layer 108 .

In this example embodiment, the substrate on which the source electrode 103 and the drain electrode 104, the semiconductor active layer 105, the first gate insulating layer 106, and the first gate electrode 107 are formed may include: a base substrate 101, which is formed on a substrate The buffer layer 102 above the base substrate 101 , the source electrode 103 , the drain electrode 104 , and the semiconductor active layer 105 are formed above the buffer layer 102 , and the first electrode 103 , the drain electrode 104 , and the semiconductor active layer 105 are formed above the source electrode 103 , the drain electrode 104 . A gate insulating layer 106 is formed on the first gate electrode 107 above the first gate insulating layer 106 .

The semiconductor active layer 105 may be formed above the source electrode 103 and the drain electrode 104, or may be formed below the source electrode 103 and the drain electrode 104, which is not limited herein.

It should be noted that: "above" and "below" in this embodiment are described based on the order of the preparation process, that is, the structure formed first is at the bottom, and the structure formed later is at the top. The relative position of up and down is not absolute.

Based on this, the preparation of the second gate insulating layer 108 may include: forming a silicon nitride SiN film, a silicon oxide SiO ₂ film, and a silicon oxynitride SiNO film on the above-mentioned substrate by a CVD (Chemical VaporDeposition) method one or more of. The second gate insulating layer 108 may be a single-layer structure or a multi-layer composite structure.

Of course, this embodiment is not limited to this, and the second gate insulating layer 108 may also be prepared by using other insulating materials.

On this basis, the forming the etching protection layer 200 over the second gate insulating layer 108 may include: forming the etching protection layer 200 over the second gate insulating layer 108 by a CVD method.

The etching protection layer 200 and the second gate insulating layer 108 may be prepared in the same CVD equipment, eg, the same PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) equipment. In this way, the etching protection layer 200 is directly deposited after the second gate insulating layer 108 is deposited in the same device, so that the introduction of other impurities can be avoided, thereby obtaining a high-quality film.

在该厚度范围内，既可有效的防止第二栅绝缘层108在氢氟酸清洗过程中受到氢氟酸刻蚀而被过度减薄，又不至于增大第二栅绝缘层108的厚度，从而可保证薄膜晶体管具有良好的电学性能。Preferably, the thickness of the etching protection layer 200 may be

Within this thickness range, the second gate insulating layer 108 can be effectively prevented from being excessively thinned by hydrofluoric acid etching during the hydrofluoric acid cleaning process, and the thickness of the second gate insulating layer 108 will not be increased. Thus, the thin film transistor can be guaranteed to have good electrical performance.

In an implementation manner of this example, the etching protection layer 200 may be an amorphous silicon a-Si thin film. In this case, forming the etching protection layer 200 over the second gate insulating layer 108 may be: forming an amorphous silicon a-Si thin film over the second gate insulating layer 108 .

In another implementation manner of this example, the etching protection layer 200 may also be a silicon oxide SiO ₂ film. In this case, forming the etching protection layer 200 over the second gate insulating layer 108 may be: forming a silicon oxide SiO ₂ film over the second gate insulating layer 108 .

In step S2 , referring to FIG. 8 , the substrate on which the second gate insulating layer 108 and the etching protection layer 200 are formed is placed in a hydrofluoric acid cleaning device for oxidation treatment and hydrofluoric acid cleaning, so that During the cleaning process, the etching protection layer 200 is removed.

In this exemplary embodiment, the substrate needs to undergo ozone O ₃ oxidation treatment, hydrofluoric acid cleaning, and ozone O ₃ oxidation treatment in sequence in the hydrofluoric acid cleaning device. During the O ₃ oxidation treatment, the film layer formed on the substrate, especially the etching protection layer 200 on the surface of the substrate, will be oxidized to generate a corresponding oxide, and the oxide will be etched during hydrofluoric acid cleaning Lose.

When the etching protection layer 200 is an amorphous silicon a-Si film, the amorphous silicon a-Si film will be converted into a silicon oxide _SiO2 film after being oxidized by O ₃ in a hydrofluoric acid cleaning device. In this case, in the hydrofluoric acid cleaning process, the silicon oxide SiO ₂ film will be etched first, and then the second gate insulating layer 108 such as the silicon nitride SiN film may be etched in a small amount, which can effectively surface damage to the second gate insulating layer 108 is reduced.

It should be noted that: in the oxidation process of amorphous silicon a-Si thin film, according to the difference of its thickness, there may be a situation that most of the amorphous silicon a-Si is oxidized, but a small amount of amorphous silicon a-Si is not oxidized. At this time, the residual amorphous silicon a-Si is also etched during the hydrofluoric acid cleaning process.

When the etching protection layer 200 is a silicon oxide SiO ₂ film, the silicon oxide SiO ₂ film still remains a silicon oxide SiO ₂ film after being oxidized by O ₃ in a hydrofluoric acid cleaning device. In this case, in the hydrofluoric acid cleaning process, the silicon oxide SiO ₂ film will be etched first, and then the second gate insulating layer 108 such as the silicon nitride SiN film may be etched in a small amount, which can effectively surface damage to the second gate insulating layer 108 is reduced.

之间，而氧化硅SiO₂薄膜的沉积厚度较小时其均一性较差，因此本实施例优选采用非晶硅a-Si薄膜作为所述刻蚀保护层200。Considering that the thickness of the etching protection layer 200 is relatively small, for example, in

However, when the deposition thickness of the silicon oxide SiO ₂ film is small, its uniformity is poor. Therefore, in this embodiment, an amorphous silicon a-Si film is preferably used as the etching protection layer 200 .

In step S3, referring to FIG. 9, a second gate electrode 109 is prepared on the substrate after being cleaned with hydrofluoric acid.

In this example embodiment, the second gate electrode 109 is formed on the second gate insulating layer 108 after cleaning with hydrofluoric acid, and a protective layer 110 can also be formed on the second gate electrode 109 after that.

Wherein, the material of the first gate 107 and the second gate 109 can be any one of metals or alloys such as molybdenum, tungsten, tantalum, molybdenum-tungsten; the first gate insulating layer 106, the second gate insulating layer 108, And the material of the protective layer 110 can be any one of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, etc.; the material of the semiconductor active layer 105 can be single crystal silicon, amorphous silicon , polysilicon, and metal oxide semiconductor, and in this embodiment, preferably, amorphous silicon is converted into polysilicon through a subsequent ELA process.

Based on the above description, the thin film transistor 10 provided by the present exemplary embodiment can be fabricated by the above-mentioned fabrication method, so as to prevent the second gate insulating layer 108 from being excessively thinned by hydrofluoric acid etching, thereby improving the second gate insulating layer The surface damage of the layer 108 can further ensure the electrical performance of the thin film transistor 10 and improve the stability of the subsequent process.

The present exemplary embodiment also provides an array substrate including the above-mentioned thin film transistor 10 .

Wherein, the array substrate can be applied to an LCD (Liquid Crystal Display, liquid crystal display), and is assembled with a color filter substrate to form an LCD panel.

Alternatively, the array substrate can also be applied to an OLED (Organic Light Emitting Diode, organic light emitting diode display), and is assembled with a packaging substrate to form an OLED panel.

Based on this, the present exemplary embodiment further provides a display panel including the above-mentioned thin film transistor 10 or the above-mentioned array substrate.

Since the thin film transistor 10 provided in this embodiment has stable electrical properties, a display panel using the thin film transistor 10 can also obtain a good display effect.

The present exemplary embodiment also provides a display device including the above-mentioned display panel.

The display device may include, for example, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, which is not specifically limited in the present disclosure.

Other embodiments of the present disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or techniques in the technical field not disclosed by the present disclosure . The specification and examples are to be regarded as exemplary only, with the true scope and spirit of the disclosure being indicated by the appended claims.

It is to be understood that the present disclosure is not limited to the precise structures described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (7)

1. a preparation method of a top gate type thin film transistor, is characterized in that, comprises: A second gate insulating layer is prepared on the substrate formed with the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode, and an etching protection layer is formed over the second gate insulating layer , the etching protection layer directly contacts the second gate insulating layer, and at least covers all the top surfaces and all the climbing parts of the second gate insulating layer; The substrate on which the second gate insulating layer and the etching protection layer are formed is placed in a hydrofluoric acid cleaning device for oxidation treatment and hydrofluoric acid cleaning, so as to remove the etching protective layer; A second gate electrode is prepared on the substrate after the hydrofluoric acid cleaning; wherein, Forming an etch protection layer over the second gate insulating layer includes: An amorphous silicon film is formed over the second gate insulating layer. 2 . The preparation method according to claim 1 , wherein placing the substrate on which the second gate insulating layer and the etch protection layer are formed for oxidation treatment in a hydrofluoric acid cleaning device comprises: 3 . The substrate on which the second gate insulating layer and the amorphous silicon film are formed is placed in a hydrofluoric acid cleaning device for ozone oxidation treatment, so that the amorphous silicon film is converted into a silicon oxide film. 3. The preparation method according to any one of claims 1-2, wherein the etching protection layer has a thickness of

4 . The preparation method according to claim 1 , wherein the second gate insulating layer and the etching protection layer are prepared in the same thin film deposition equipment. 5 . 5 . The preparation method according to claim 4 , wherein the second gate insulating layer is prepared on the substrate formed with the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode. 6 . include: One or more of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film are formed on the substrate on which the semiconductor active layer, the source and drain electrodes, the first gate insulating layer, and the first gate electrode are formed . 6 . The preparation method according to claim 1 , wherein the substrate formed with a semiconductor active layer, a source electrode and a drain electrode, a first gate insulating layer, and a first gate electrode comprises: 6 . substrate substrate; a source electrode and a drain electrode formed above the base substrate; a semiconductor active layer formed over the source electrode and the drain electrode; a first gate insulating layer formed over the semiconductor active layer; and, a first gate formed over the first gate insulating layer. 7. The preparation method according to claim 6, wherein the substrate formed with the semiconductor active layer, the source electrode and the drain electrode, the first gate insulating layer, and the first gate electrode further comprises: The buffer layer is formed on the side of the base substrate facing the semiconductor active layer.

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