CN107799085B - Liquid crystal panel driving circuit, liquid crystal panel and liquid crystal panel driving method - Google Patents
Liquid crystal panel driving circuit, liquid crystal panel and liquid crystal panel driving method Download PDFInfo
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- CN107799085B CN107799085B CN201711168181.9A CN201711168181A CN107799085B CN 107799085 B CN107799085 B CN 107799085B CN 201711168181 A CN201711168181 A CN 201711168181A CN 107799085 B CN107799085 B CN 107799085B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/04—Display protection
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Abstract
The invention provides a liquid crystal panel driving circuit, a liquid crystal panel and a liquid crystal panel driving method. The liquid crystal panel driving circuit comprises a comparator (1), an AND gate (2), a time sequence controller (3) and a power management integrated module (4); the positive input end of the comparator (1) is connected with an external input Voltage (VIN), the negative input end of the comparator is connected with a low-voltage turn-off voltage (UVLO) of the power management integrated module (4), and the output end of the comparator is electrically connected with a first input end (A) of the AND gate (2); and a second input end (B) of the AND gate (2) is connected to a power supply Voltage (VDD) output by the power supply management integrated module (4), and an output end (K) is electrically connected with a reset pin (31) of the time schedule controller (3). The liquid crystal panel driving circuit can enable the time sequence controller (3) to still be normally reset and normally output under the condition that external input Voltage (VIN) fluctuates.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a liquid crystal panel driving circuit, a liquid crystal panel and a liquid crystal panel driving method.
Background
Liquid Crystal Display (LCD) has many advantages such as thin body, power saving, no radiation, and is widely used, for example: liquid crystal televisions, smart phones, digital cameras, tablet computers, computer screens, or notebook computer screens, etc., are dominant in the field of flat panel displays.
The Liquid Crystal panel is mainly composed of a Thin Film Transistor Array Substrate (TFT Array Substrate), a Color Filter Substrate (CF), and a Liquid Crystal Layer (Liquid Crystal Layer) disposed between the two substrates, and the Liquid Crystal panel has an operation principle that a driving circuit provides a driving voltage and applies the driving voltage to the two substrates to control the rotation of Liquid Crystal molecules of the Liquid Crystal Layer, so as to refract light of the backlight module to generate a picture.
A Timing Controller (TCON), also called a logic board or a central control board, is a key component in the liquid crystal panel driving circuit, and is used to convert the LVDS signals sent from the main board into gate driving signals and source driving signals required by the display of the liquid crystal panel, complete the conversion output from the LVDS to the MINI-LVDS, and output various control timing sequences required by the gate driving and the source driving.
A Power Management Integrated Circuit (PMIC) is also a key component in the lcd panel driving circuit. The PMIC has a low voltage shutdown (UVLO) voltage, when the voltage of the input PMIC is higher than the UVLO voltage, the PMIC works normally, and when the voltage of the input PMIC is lower than the UVLO voltage, the PMIC is closed, the output voltage is stopped, and therefore the PMIC is prevented from being damaged when the power supply voltage is insufficient.
When a user uses a liquid crystal panel (such as a television), unstable external input voltage is avoided, voltage dip is caused and then recovered, and because the voltage dip is too short, the PMIC is just turned off instantly and then turned on again, and all output voltages cannot be completely discharged. The requirement of the Reset (Reset) pin of the time schedule controller on the voltage is stricter, under the condition that the voltage is suddenly dropped and then recovered, if the power supply Voltage (VDD) and the kernel voltage (Vcore) output by the PMIC are not completely discharged, the power supply is restarted, the voltage of the Reset pin of the time schedule controller can not completely drop below 0.9V, the Reset action can not be completed, the work of the time schedule controller is abnormal, the output is abnormal, the picture abnormality can correspondingly occur on the liquid crystal panel, even the irreversible damage can occur on the liquid crystal panel, and the user experience is seriously influenced.
Disclosure of Invention
The invention aims to provide a liquid crystal panel driving circuit, which can enable a time schedule controller to be normally reset and normally output under the condition of external input voltage fluctuation.
Another object of the present invention is to provide a liquid crystal panel, in which a timing controller can be normally reset without being affected by fluctuation of an external input voltage.
The invention also aims to provide a liquid crystal panel driving method which can solve the problem that a time schedule controller cannot be reset due to external input voltage fluctuation.
In order to achieve the above object, the present invention first provides a liquid crystal panel driving circuit, which includes a comparator, an and gate, a timing controller and a power management integrated module;
the positive input end of the comparator is connected with an external input voltage, the negative input end of the comparator is connected with the low-voltage turn-off voltage of the power management integrated module, and the output end of the comparator is electrically connected with the first input end of the AND gate; and the second input end of the AND gate is connected with the power supply voltage output by the power supply management integrated module through an RC circuit, and the output end of the AND gate is electrically connected with a reset pin of the time schedule controller.
The second input end of the AND gate is connected to the power supply voltage output by the power supply management integrated module through an RC circuit;
the RC circuit comprises a resistor and a capacitor which are connected in series; one end of the resistor is connected to the power supply voltage output by the power supply management integrated module, and the other end of the resistor is electrically connected with the first polar plate of the capacitor; the second plate of the capacitor is grounded;
and the second input end of the AND gate is electrically connected with the other end of the resistor and the first polar plate of the capacitor.
When the external input voltage is normal, the external input voltage is higher than the low-voltage turn-off voltage of the power management integrated module, and the power voltage normally output by the power management integrated module is high level.
The invention also provides a liquid crystal panel, which comprises a liquid crystal panel driving circuit, wherein the liquid crystal panel driving circuit comprises a comparator, an AND gate, a time schedule controller and a power management integrated module;
the positive input end of the comparator is connected with an external input voltage, the negative input end of the comparator is connected with the low-voltage turn-off voltage of the power management integrated module, and the output end of the comparator is electrically connected with the first input end of the AND gate; and the second input end of the AND gate is connected with the power supply voltage output by the power supply management integrated module through an RC circuit, and the output end of the AND gate is electrically connected with a reset pin of the time schedule controller.
The second input end of the AND gate is connected to the power supply voltage output by the power supply management integrated module through an RC circuit;
the RC circuit comprises a resistor and a capacitor which are connected in series; one end of the resistor is connected to the power supply voltage output by the power supply management integrated module, and the other end of the resistor is electrically connected with the first polar plate of the capacitor; the second plate of the capacitor is grounded;
and the second input end of the AND gate is electrically connected with the other end of the resistor and the first polar plate of the capacitor.
When the external input voltage is normal, the external input voltage is higher than the low-voltage turn-off voltage of the power management integrated module, and the power voltage normally output by the power management integrated module is high level.
The invention also provides a liquid crystal panel driving method, which comprises the following steps:
comparing the external input voltage with the low-voltage turn-off voltage of the power management integrated module to obtain a comparison result;
outputting a digital signal according to the comparison result;
performing logic operation on the digital signal and the voltage between a resistor and a capacitor in the RC circuit;
and outputting the result of the logic operation to a reset pin of a time schedule controller, and executing reset action by the time schedule controller when the result of the logic operation is high level.
Wherein the step of outputting a digital signal according to the comparison result specifically comprises:
when the comparison result shows that the external input voltage is higher than the low-voltage turn-off voltage of the power management integrated module, outputting a high-level signal;
and outputting a low-level signal when the comparison result shows that the external input voltage is lower than or equal to the low-voltage turn-off voltage of the power management integrated module.
Wherein comparing the external input voltage with a low-voltage turn-off voltage of the power management integrated module is performed by a comparator.
The step of performing logic operation on the digital signal and the voltage between the resistor and the capacitor in the RC circuit specifically includes:
and logically ANDing the digital signal with a voltage between a resistor and a capacitor in the RC circuit.
The invention has the beneficial effects that: the invention provides a liquid crystal panel driving circuit and a liquid crystal panel.A positive input end of a comparator is connected with an external input voltage, a negative input end of the comparator is connected with a low-voltage turn-off voltage of a power management integrated module, an output end of the comparator is electrically connected with a first input end of an AND gate, a second input end of the AND gate is connected with a power voltage output by the power management integrated module through an RC circuit, and an output end of the AND gate is electrically connected with a reset pin of a time schedule controller; when the external input voltage is suddenly reduced to be lower than or equal to the low-voltage turn-off voltage of the power management integrated module, the output end of the comparator outputs a low level, the output end of the AND gate outputs a low level to the reset pin of the time schedule controller, and when the external input voltage is recovered to be higher than the low-voltage turn-off voltage of the power management integrated module, the output end of the comparator outputs a high level, the output end of the AND gate outputs a high level to the reset pin of the time schedule controller, so that the time schedule controller can still normally reset and normally output under the condition of external input voltage fluctuation. According to the liquid crystal panel driving method provided by the invention, the level of the reset pin of the time schedule controller is low when the external input voltage is lower than or equal to the low-voltage turn-off voltage of the power management integrated module, and is high when the external input voltage is recovered to be higher than the low-voltage turn-off voltage of the power management integrated module by comparing the external input voltage with the low-voltage turn-off voltage of the power management integrated module, so that the problem that the time schedule controller cannot be reset due to the fluctuation of the external input voltage can be solved.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a circuit diagram of a liquid crystal panel driving circuit according to the present invention;
FIG. 2 is a flow chart of a driving method of a liquid crystal panel according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 1, the present invention first provides a liquid crystal panel driving circuit, which includes a comparator 1, an and gate 2, a timing controller 3, a power management integrated module 4 and an RC circuit 5.
The RC circuit 5 comprises a resistor R and a capacitor C which are connected in series; one end of the resistor R is connected to a power supply voltage VDD output by the power supply management integrated module 4, and the other end of the resistor R is electrically connected with a first polar plate of the capacitor C; the second plate of the capacitor C is grounded.
The positive input end of the comparator 1 is connected with an external input voltage VIN, the negative input end of the comparator is connected with a low-voltage turn-off voltage UVLO of the power management integrated module 4, and the output end of the comparator is electrically connected with the first input end a of the and gate 2.
The second input end B of the and gate 2 is electrically connected to the other end of the resistor R and the first plate of the capacitor C to access the power voltage VDD output by the power management integrated module 4, and the output end K is electrically connected to the reset pin 31 of the timing controller 3.
The power management integrated module 4 has a characteristic that: when the external input voltage VIN input to the power management module 4 is higher than the low-voltage turn-off voltage UVLO thereof, the power management integrated module 4 supplies power normally, and outputs a high-level power voltage VDD, which is usually 3.3V; when the external input voltage VIN is lower than or equal to the low-voltage turn-off voltage UVLO, the power management integrated module 4 is turned off, and the output of the power voltage VDD is stopped, so that the power management module 4 is not damaged when the supply voltage is insufficient.
Under normal conditions: the external input voltage VIN is higher than the low-voltage turn-off voltage UVLO of the power management integrated module 4, and the output end of the comparator 1 outputs a high level to the first input end a of the and gate 2; the power supply voltage VDD output by the power supply management integrated module 4 is a high level of 3.3V, and charges the capacitor C, so that the second input terminal B of the and gate 2 is also a high level; because the first input end a and the second input end B of the and gate 2 are both high level, the output end K of the and gate 2 correspondingly outputs high level to the reset pin 31 of the timing controller 3, and the timing controller 3 performs normal reset action and normal output.
When the external input voltage VIN drops suddenly to be lower than or equal to the low-voltage turn-off voltage UVLO of the power management integrated module 4, the output terminal of the comparator 1 outputs a low level to the first input terminal a of the and gate 2; the power management integrated module 4 is turned off to stop outputting the power voltage VDD, but since the capacitor C in the RC circuit 5 discharges slowly, the capacitor C cannot discharge completely within a short time of sudden drop of the external input voltage VIN, so that the second input terminal B of the and gate 2 is still at a high level; since the first input terminal a of the and gate 2 is at a low level and the second input terminal B is at a high level, the output terminal K of the and gate 2 outputs the low level to the reset pin 31 of the timing controller 3.
After the external input voltage VIN undergoes a short sudden drop, the external input voltage VIN is rapidly restored to be higher than the low-voltage turn-off voltage UVLO of the power management integrated module 4, at this time, the output end of the comparator 1 outputs a high level to the first input end a of the and gate 2, the power management integrated module 4 is restarted, the output power voltage VDD is restored to be a high level of 3.3V, and the capacitor C is charged, so that the second input end B of the and gate 2 keeps a high level; because the first input end a and the second input end B of the and gate 2 are both high level, the output end K of the and gate 2 outputs high level to the reset pin 31 of the timing controller 3, so that the timing controller 3 is normally reset and normally outputs.
The present invention also provides a liquid crystal panel, comprising the liquid crystal panel driving circuit as shown in fig. 1, wherein the timing controller 3 can be normally reset without being affected by the fluctuation of the external input voltage VIN, and the liquid crystal panel driving circuit will not be described repeatedly herein.
Referring to fig. 2, with reference to fig. 1, based on the liquid crystal panel driving circuit, the present invention also provides a liquid crystal panel driving method, including the following steps:
step S1, comparing the external input voltage VIN with the low-voltage turn-off voltage UVLO of the power management integrated module 4 to obtain a comparison result.
Specifically, the step S1 is executed by the comparator 1 in the liquid crystal panel driving circuit to compare the external input voltage VIN with the low-voltage turn-off voltage UVLO of the power management integrated module 4.
And step S2, outputting a digital signal according to the comparison result.
Specifically, in this step S2, the comparator 1 in the liquid crystal panel driving circuit outputs a corresponding digital signal according to the comparison result: when the comparison result is that the external input voltage VIN is higher than the low-voltage turn-off voltage UVLO of the power management integrated module 4, the comparator 1 outputs a high-level signal; and when the external input voltage VIN is lower than or equal to the low-voltage shutdown voltage UVLO of the power management integrated module 4, the comparator 1 outputs a low-level signal.
Step S3, performing a logic operation on the digital signal and the voltage between the resistor R and the capacitor C in the RC circuit 5.
Specifically, this step S3 logically and-operates the digital signal with the voltage between the resistor R and the capacitor C in the RC circuit 5 through the and gate 2 in the liquid crystal panel driving circuit.
Further, under normal conditions: the external input voltage VIN is higher than the low-voltage turn-off voltage UVLO of the power management integrated module 4, and the output end of the comparator 1 outputs a high-level signal to the first input end a of the and gate 2; the power management integrated module 4 normally outputs a power voltage VDD of a high level of 3.3V and charges the capacitor C, so that the second input terminal B of the and gate 2 is also at a high level; since the first input end a and the second input end B of the and gate 2 are both at high level, the result of the logical and operation performed by the and gate 2 is at high level.
When the external input voltage VIN drops suddenly to be lower than or equal to the low-voltage turn-off voltage UVLO of the power management integrated module 4, the output terminal of the comparator 1 outputs a low-level signal to the first input terminal a of the and gate 2; the power management integrated module 4 is turned off to stop outputting the power voltage VDD, but since the capacitor C in the RC circuit 5 discharges slowly, the capacitor C cannot discharge completely within a short time of sudden drop of the external input voltage VIN, so that the second input terminal B of the and gate 2 is still at a high level; since the first input end a of the and gate 2 is at a low level and the second input end B is at a high level, the result of the and gate 2 performing the logical and operation is at a low level.
After the external input voltage VIN undergoes a short sudden drop, the external input voltage VIN is rapidly restored to be higher than the low-voltage turn-off voltage UVLO of the power management integrated module 4, at this time, the output end of the comparator 1 outputs a high-level signal to the first input end a of the and gate 2, the power management integrated module 4 is restarted, the output power voltage VDD is restored to be a high level of 3.3V, and the capacitor C is charged, so that the second input end B of the and gate 2 keeps a high level; because the first input end A and the second input end B of the AND gate 2 are both high level, the result of the logical AND operation of the AND gate 2 is changed into high level.
Step S4 is to output the result of the logic operation to the reset pin 31 of the timing controller 3, and when the result of the logic operation is high level, the timing controller 3 performs a reset operation.
Specifically, in this step S4, the output terminal K of the and gate 2 in the liquid crystal panel driving circuit outputs the result of the logical and operation to the reset pin 31 of the timing controller 3, so that the timing controller 3 can not only normally perform the reset operation under the normal condition that the external input voltage VIN is higher than the low-voltage shutdown voltage UVLO of the power management integrated module 4, but also perform the reset operation under the condition that the external input voltage VIN fluctuates, i.e., the external input voltage VIN is rapidly and suddenly dropped and then rapidly recovers to a voltage higher than the low-voltage shutdown voltage UVLO of the power management integrated module 4.
According to the liquid crystal panel driving method, the level of the reset pin 31 of the timing controller 3 is low when the external input voltage VIN is lower than or equal to the low-voltage turn-off voltage UVLO of the power management integrated module 4 and is high when the external input voltage VIN is restored to be higher than the low-voltage turn-off voltage UVLO of the power management integrated module 4 by comparing the external input voltage VIN with the low-voltage turn-off voltage UVLO of the power management integrated module 4, and the problem that the timing controller 3 cannot be reset due to fluctuation of the external input voltage VIN can be solved.
In summary, in the liquid crystal panel driving circuit and the liquid crystal panel of the present invention, the positive input terminal of the comparator is connected to the external input voltage, the negative input terminal is connected to the low-voltage turn-off voltage of the power management integrated module, the output terminal is electrically connected to the first input terminal of the and gate, the second input terminal of the and gate is connected to the power voltage output by the power management integrated module through an RC circuit, and the output terminal is electrically connected to the reset pin of the timing controller; when the external input voltage is suddenly reduced to be lower than or equal to the low-voltage turn-off voltage of the power management integrated module, the output end of the comparator outputs a low level, the output end of the AND gate outputs a low level to the reset pin of the time schedule controller, and when the external input voltage is recovered to be higher than the low-voltage turn-off voltage of the power management integrated module, the output end of the comparator outputs a high level, the output end of the AND gate outputs a high level to the reset pin of the time schedule controller, so that the time schedule controller can still normally reset and normally output under the condition of external input voltage fluctuation. According to the liquid crystal panel driving method, the level of the reset pin of the time schedule controller is low when the external input voltage is lower than or equal to the low-voltage turn-off voltage of the power management integrated module, and is high when the external input voltage is recovered to be higher than the low-voltage turn-off voltage of the power management integrated module by comparing the external input voltage with the low-voltage turn-off voltage of the power management integrated module, so that the problem that the time schedule controller cannot be reset due to fluctuation of the external input voltage can be solved.
As described above, it will be apparent to those skilled in the art that various other changes and modifications can be made based on the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the appended claims.
Claims (10)
1. The liquid crystal panel driving circuit is characterized by comprising a comparator (1), an AND gate (2), a time schedule controller (3) and a power management integrated module (4);
the positive input end of the comparator (1) is connected with an external input Voltage (VIN), the negative input end of the comparator is connected with a low-voltage turn-off voltage (UVLO) of the power management integrated module (4), and the output end of the comparator is electrically connected with a first input end (A) of the AND gate (2); and a second input end (B) of the AND gate (2) is connected to a power supply Voltage (VDD) output by the power supply management integrated module (4) through an RC circuit (5), and an output end (K) is electrically connected with a reset pin (31) of the time schedule controller (3).
2. The liquid crystal panel driving circuit according to claim 1, wherein the RC circuit (5) comprises a resistor (R) and a capacitor (C) connected in series; one end of the resistor (R) is connected to a power supply Voltage (VDD) output by the power supply management integrated module (4), and the other end of the resistor (R) is electrically connected with a first polar plate of the capacitor (C); the second plate of the capacitor (C) is grounded;
and a second input end (B) of the AND gate (2) is electrically connected with the other end of the resistor (R) and the first polar plate of the capacitor (C).
3. The liquid crystal panel driving circuit according to claim 1, wherein the external input Voltage (VIN) is normally higher than a low voltage shutdown voltage (UVLO) of the power management integrated module (4), and the power management integrated module (4) normally outputs a high level of the power supply Voltage (VDD).
4. The liquid crystal panel is characterized by comprising a liquid crystal panel driving circuit, wherein the liquid crystal panel driving circuit comprises a comparator (1), an AND gate (2), a time schedule controller (3) and a power management integrated module (4);
the positive input end of the comparator (1) is connected with an external input Voltage (VIN), the negative input end of the comparator is connected with a low-voltage turn-off voltage (UVLO) of the power management integrated module (4), and the output end of the comparator is electrically connected with a first input end (A) of the AND gate (2); and a second input end (B) of the AND gate (2) is connected to a power supply Voltage (VDD) output by the power supply management integrated module (4) through an RC circuit (5), and an output end (K) is electrically connected with a reset pin (31) of the time schedule controller (3).
5. The liquid crystal panel according to claim 4, wherein the RC circuit (5) comprises a resistor (R) and a capacitor (C) connected in series; one end of the resistor (R) is connected to a power supply Voltage (VDD) output by the power supply management integrated module (4), and the other end of the resistor (R) is electrically connected with a first polar plate of the capacitor (C); the second plate of the capacitor (C) is grounded;
and a second input end (B) of the AND gate (2) is electrically connected with the other end of the resistor (R) and the first polar plate of the capacitor (C).
6. The liquid crystal panel according to claim 4, wherein the external input Voltage (VIN) is normally higher than the low voltage shutdown voltage (UVLO) of the power management integrated module (4), and the power supply Voltage (VDD) normally output by the power management integrated module (4) is high.
7. A liquid crystal panel driving method, comprising:
comparing the external input Voltage (VIN) with the low-voltage turn-off voltage (UVLO) of the power management integrated module (4) to obtain a comparison result;
outputting a digital signal according to the comparison result;
performing a logical operation on the digital signal and a voltage between a resistor (R) and a capacitor (C) in an RC circuit (5);
and outputting the result of the logic operation to a reset pin (31) of the time schedule controller (3), and executing reset action by the time schedule controller (3) when the result of the logic operation is high level.
8. The method according to claim 7, wherein the step of outputting a digital signal according to the comparison result comprises:
when the comparison result is that the external input Voltage (VIN) is higher than a low-voltage turn-off voltage (UVLO) of the power management integrated module (4), outputting a high-level signal;
and outputting a low-level signal when the external input Voltage (VIN) is lower than or equal to a low-voltage shutdown voltage (UVLO) of the power management integrated module (4) as a comparison result.
9. The liquid crystal panel driving method according to claim 7,
comparing the external input Voltage (VIN) with the low voltage turn-off voltage (UVLO) of the power management integrated module (4) is performed by a comparator (1).
10. The method for driving a liquid crystal panel according to claim 7, wherein the step of logically operating the digital signal with the voltage between the resistor (R) and the capacitor (C) in the RC circuit (5) specifically comprises:
and logically ANDing the digital signal with a voltage between a resistor (R) and a capacitor (C) in an RC circuit (5).
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| CN201711168181.9A CN107799085B (en) | 2017-11-21 | 2017-11-21 | Liquid crystal panel driving circuit, liquid crystal panel and liquid crystal panel driving method |
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| CN201711168181.9A CN107799085B (en) | 2017-11-21 | 2017-11-21 | Liquid crystal panel driving circuit, liquid crystal panel and liquid crystal panel driving method |
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| CN107799085B true CN107799085B (en) | 2020-06-30 |
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| CN109036302B (en) * | 2018-07-20 | 2019-12-24 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display device with a light guide plate |
| CN109003590B (en) * | 2018-08-30 | 2021-01-29 | 京东方科技集团股份有限公司 | Discharge circuit and display device |
| CN109119042B (en) * | 2018-09-27 | 2020-04-28 | 深圳市华星光电技术有限公司 | Driving circuit |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101782641B1 (en) * | 2010-12-08 | 2017-10-23 | 엘지디스플레이 주식회사 | Liquid crystal display |
| US8659271B2 (en) * | 2011-03-23 | 2014-02-25 | Grenergy Opto Inc. | Fixed-on-time controller utilizing an adaptive saw signal for discontinuous mode PFC power conversion |
| CN103295538B (en) * | 2013-07-02 | 2015-03-04 | 深圳市华星光电技术有限公司 | Backlight drive circuit and method for shortening soft starting time of backlight drive circuit |
| CN104766577B (en) * | 2015-04-08 | 2017-06-06 | 合肥京东方光电科技有限公司 | Time schedule controller and drive control method, gate driving circuit and method |
| CN105790566B (en) * | 2016-03-16 | 2018-06-22 | 深圳市华星光电技术有限公司 | the auxiliary circuit of power supply with power management chip |
| CN106782410B (en) * | 2017-02-21 | 2019-09-06 | 昆山龙腾光电有限公司 | Liquid crystal display device and its driving method |
| CN107301849B (en) * | 2017-07-19 | 2018-08-14 | 深圳市华星光电半导体显示技术有限公司 | Display driver chip and liquid crystal display device |
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2017
- 2017-11-21 CN CN201711168181.9A patent/CN107799085B/en active Active
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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