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CN107797344B - 阵列基板、显示面板及其制造方法 - Google Patents

阵列基板、显示面板及其制造方法 Download PDF

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CN107797344B
CN107797344B CN201711121403.1A CN201711121403A CN107797344B CN 107797344 B CN107797344 B CN 107797344B CN 201711121403 A CN201711121403 A CN 201711121403A CN 107797344 B CN107797344 B CN 107797344B
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layer
array substrate
pixel
data line
metal electrode
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CN107797344A (zh
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薛进进
史大为
徐海峰
杨璐
王文涛
闫雷
姚磊
司晓文
闫芳
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US16/110,190 priority patent/US20190146293A1/en
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Abstract

本发明提供一种阵列基板，所述阵列基板被划分为多个像素单元，所述阵列基板包括像素电极层和数据线层，所述像素电极层包括多个像素电极，每个所述像素单元中都设置有所述像素电极，所述数据线层包括多条数据线，其中，所述阵列基板还包括金属电极图形层，所述金属电极图形层包括与多个所述像素电极一一对应的多个漏极，所述像素电极与所述漏极电连接，所述金属电极图形层与所述数据线层在所述阵列基板的厚度方向间隔设置。本发明还提供一种显示面板和一种阵列基板的制造方法，所述阵列基板具有较高的良率。

Description

阵列基板、显示面板及其制造方法
技术领域
本发明涉及显示技术领域，具体地，涉及一种阵列基板、一种包括该阵列基板的显示面板和该阵列基板的制造方法。
背景技术
如图1所示，显示装置的阵列基板包括薄膜晶体管，每个薄膜晶体管都包括源极110和漏极120。源极110、漏极120与数据线位于同一层中，像素电极210与漏极120电连接。随着对高PPI的要求，阵列基板中的走线越来越密集，容易造成短路、开路等不良。当阵列基板中产生短路、开路等不良时，包括所述阵列基板的显示面板在显示时将出现暗点不良。
因此，如何避免阵列基板中产生短路、开路等不良成为本领域亟待解决的技术问题。
发明内容
本发明的目的在于提供一种阵列基板、一种包括该阵列基板的显示面板和所述阵列基板的制造方法。所述阵列基板具有较高的良率。
为了实现上述目的，作为本发明的一个方面，提供一种阵列基板，所述阵列基板被划分为多个像素单元，所述阵列基板包括像素电极层和数据线层，所述像素电极层包括多个像素电极，每个所述像素单元中都设置有所述像素电极，所述数据线层包括多条数据线，其中，所述阵列基板还包括金属电极图形层，所述金属电极图形层包括与多个所述像素电极一一对应的多个漏极，所述像素电极与所述漏极电连接，所述金属电极图形层与所述数据线层在所述阵列基板的厚度方向间隔设置。
优选地，所述像素单元排列为多行多列，每列像素单元对应一条数据线，所述阵列基板包括绝缘层，所述数据线层和所述金属电极图形层分别位于所述绝缘层的厚度方向的两侧，所述金属电极图形层还包括多个源极，所述源极的数量与所述漏极的数量相同，同一列像素单元中的源极与相应的数据线通过贯穿所述绝缘层的过孔电连接。
优选地，所述阵列基板包括平坦化层，所述平坦化层覆盖所述金属电极图形层，以使得所述像素电极层和所述金属电极图形层分别位于所述平坦化层厚度方向的两侧，所述像素电极层中的像素电极通过贯穿所述平坦化层的过孔与相应的漏极电连接。
优选地，所述金属电极图形层包括多个栅极，每个像素单元中均设置有所述栅极，所述阵列基板包括有源图形层，所述绝缘层包括层间绝缘层和栅绝缘层，所述层间绝缘层覆盖所述数据线层，所述有源图形层设置在所述层间绝缘层和所述栅绝缘层之间，所述金属电极图形层设置在所述栅绝缘层上，将所述源极与相应的数据线电连接的过孔包括形成为一体的第一过孔部和第二过孔部，所述第一过孔部贯穿所述栅绝缘层，所述第二过孔贯穿所述层间绝缘层，所述第一过孔部与相应的有源层接触，所述漏极通过贯穿所述栅绝缘层的过孔与相应的有源层接触。
优选地，所述阵列基板还包括光阻挡层，所述光阻挡层包括多个光阻挡件，所述光阻挡件设置在所述金属电极图形层的入光侧，且所述光阻挡件在所述金属电极图形层上的正投影与至少一个所述栅极的至少一部分重叠。
优选地，所述金属电极图形层包括多条栅线，所述栅极形成为所述栅线的一部分。
优选地，所述有源层包括两个竖直部和连接在两个竖直部之间的水平部，所述竖直部的长度方向与数据线的长度方向平行，两个所述竖直部中的一个竖直部在所述数据线层上的正投影与相应的数据线重叠，所述栅线上在所述有源图形层上的正投影于所述竖直部重叠的部分形成为所述栅极。
优选地，所述阵列基板还包括钝化层和公共电极层，所述钝化层覆盖所述像素电极层，所述公共电极层设置在所述钝化层上，以使得所述公共电极层和所述像素电极层分别位于所述钝化层厚度方向的两侧，所述公共电极层包括多个公共电极。
作为本发明的第二个方面，提供一种显示面板，所述显示面板包括阵列基板，其中，所述阵列基板为本发明所提供的上述的阵列基板。
作为本发明的第三个方面，提供所述阵列基板被划分为多个像素单元，其中，所述制造方法包括：
形成数据线层，所述数据线层包括多条数据线；
形成金属电极图形层，所述金属电极图形层包括多个漏极，所述金属电极图形层与所述数据线层在所述阵列基板的厚度方向间隔设置，每个所述像素单元中均设置有所述漏极；
形成像素电极层，所述像素电极层包括多个像素电极，每个所述像素单元中均设置有所述像素电极，所述像素电极与同一个像素单元中的漏极电连接。
在本发明中，由于金属电极图形层与数据线层不在同一层中，因此，金属电极图形层中漏极的密度较低，因此，本发明所提供的阵列基板中的漏极不像现有技术中那样容易与相邻列像素单元对应的数据线发生短路。由此可知，本发明所提供的像素电极更加容易制造，并提高了阵列基板的良率。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是现有技术中的阵列基板的局部剖视图；
图2是本发明所提供的阵列基板的局部剖视图；
图3是本发明所提供的阵列基板的局部俯视图；
图4是本发明所提供的阵列基板的制造方法的流程图。
附图标记说明
110：源极 120：漏极
130：栅极 140：栅线
210：像素电极 220：公共电极
300：有源层 400：数据线
500：绝缘层 510：层间绝缘层
520：栅绝缘层 600：衬底基板
700：平坦化层 800：光阻挡件
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
作为本发明的一个方面，提供一种阵列基板，所述阵列基板被划分为多个像素单元，所述阵列基板包括像素电极层和数据线层，如图2所示，所述像素电极层包括多个像素电极210，每个所述像素单元中都设置有像素电极210，所述数据线层包括多条数据线400，其中，所述阵列基板还包括金属电极图形层，所述金属电极图形层包括与多个像素电极210一一对应的多个漏极120，像素电极210与相应的漏极120电连接，所述金属电极图形层与所述数据线层在所述阵列基板的厚度方向间隔设置。
在本发明中，由于金属电极图形层与数据线层不在同一层中，因此，金属电极图形层中漏极的密度较低，因此，本发明所提供的阵列基板中的漏极不像现有技术中那样容易与相邻列像素单元对应的数据线发生短路。由此可知，本发明所提供的像素电极更加容易制造，并提高了阵列基板的良率。
在阵列基板良率提高的前提下，显示面板中的暗点缺陷也相应减少。
在本发明中，对如何将漏极与像素电极电连接并没有特殊的要求。例如，可以将漏极与像素电极直接搭接。在图2中所示的优选实施方式中，所述阵列基板包括平坦化层700，该平坦化层700覆盖金属电极图形层，像素电极层位于平坦化层700上，使得像素电极层和金属电极图形层分别位于平坦化层700的厚度方向的两侧。像素电极210通过贯穿平坦化层700的过孔与相应的漏极120电连接。
如上所述，漏极与数据线400位于不同层中，因此，在金属电极层中，导电图形的密度较低，从而可以将漏极120设置为具有较大的表面积。换言之，与图1中所示的阵列基板相比，相同PPI的情况下，本发明所提供的阵列基板中的漏极120的表面积可以更大。由于漏极120面积较大，降低了连接漏极120和像素电极210的过孔的精度要求，从而可以使得该过孔在金属电极图形层中的正投影完全位于漏极120上，即，过孔不会发生错位，过孔与漏极120电连接的部分不会产生台阶，从而确保了位于过孔中的透明电极膜不会发生断裂。由此可知，本发明所提供的阵列基板更容易实现高PPI。
作为一种具体实施方式，所述像素单元排列为多行多列，每列像素单元对应一条数据线400。如图2所示，所述阵列基板包括绝缘层500，所述数据线层和所述金属电极图形层分别位于绝缘层500的厚度方向的两侧。
在本发明中，对如何设置源极并不做特殊的规定。为了减少掩膜工艺的步数，优选地，如图2所示，所述金属电极图形层还包括多个源极110，源极110的数量与漏极120的数量相同，同一列像素单元中的源极110与相应的数据线通过贯穿绝缘层500的过孔电连接。
为了进一步减少掩膜工艺的步数，优选地，如图2所示，所述金属电极图形层还包括多个栅极130，每个像素单元中均设置有栅极130。
本领域技术人员容易理解的是，每个阵列基板都包括多个薄膜晶体管。同一个像素单元中的源极、漏极、栅极、有源层组成一个薄膜晶体管。在本发明中，对像素单元中薄膜晶体管的结构并不做特殊的限制，例如，所述薄膜晶体管可以具有顶栅结构，也可以具有底栅结构。在图2中所示的具体实施方式中，薄膜晶体管具有顶栅结构。具体地，所述阵列基板包括有源图形层，所述有源图形层包括多个有源层300，每个所述像素单元中均设置有有源层300，绝缘层500包括层间绝缘层510和栅绝缘层520，层间绝缘层510覆盖所述数据线层，所述有源图形层设置在层间绝缘层510和栅绝缘层520之间。
所述金属电极图形层设置在栅绝缘层520上，连接源极110以及和该源极110对应的数据线的过孔包括形成为一体的第一过孔部分和第二过孔部分，所述第一过孔部分贯穿栅绝缘层520，所述第二过孔部分贯穿层间绝缘层510，并且，第一过孔部分与有源层300相接触。连接漏极120与有源层300的过孔贯穿栅绝缘层520。
所述阵列基板应用于显示装置中。作为一种实施方式，所述阵列基板应用于液晶显示装置中。因此，可以在阵列基板的入光侧设置背光源。为了防止薄膜晶体管的有源层在长期光照下发生老化，优选地，所述阵列基板可以包括光阻挡层，所述阻挡层包括多个光阻挡件800。如图2中所示，光阻挡层位于栅极的入光侧，并且光阻挡件800的位置与栅极向对应。由于在栅极加电后，有源层中与栅极向对应的位置形成沟道，因此，在于栅极对应的位置设置光阻挡层500可以有效地避免沟道老化。此处所述的光阻挡件的位置栅极相对应是指，光阻挡件800在金属电极图形层的正投影与栅极至少部分重叠。优选地，光阻挡件800在金属电极图形层的正投影与栅极完全重叠。
为了简化形成金属电极图形的掩膜板，优选地，所述金属电极图形层包括多条栅线，所述栅极形成为所述栅线的一部分。
薄膜晶体管可以具有单栅结构(即，一个薄膜晶体管包括一个栅极)，也可以具有双栅结构(即，一个薄膜晶体管包括两个栅极)。双栅的薄膜晶体管具有良好的开关性能，在图2和图3中所示的阵列基板中，薄膜晶体管具有双栅结构。
在本发明中，可以通过设置有源层的结构来实现双栅薄膜晶体管。在图3中所示的实施方式中，有源层300包括两个竖直部310和连接在两个竖直部310之间的水平部320，如图3所示，竖直部310的长度方向与数据线400的长度方向平行，其中一个竖直部310在数据线层的正投影与相应的数据线400重叠，另一个竖直部310在数据线层的正投影与相应的数据线400间隔。
如图3所示，栅线140上在所述金属电极图形层上的正投影与竖直部310重叠的部分形成为栅极130。
在图2中所示的具体实施方式中，所述阵列基板还包括钝化层和公共电极层，沿阵列基板的厚度方向上，像素电极层、像素电极层和公共电极层依次层叠设置。如图中所示，公共电极层包括公共电极220。公共电极220和像素电极210均采用透明电极材料制成。
如图2所示，阵列基板还包括衬底基板600。为了防止衬底基板中的杂质扩散进入薄膜晶体管中，优选地，可以在衬底基板600上设置缓冲层。
作为本发明的第二个方面，提供一种显示面板，所述显示面板包括阵列基板，其中，所述阵列基板为本发明所提供的上述的阵列基板。如上文中所述，所述阵列基板具有较高的良率，因此，所述显示面板也具有较高的良率。
作为一种具体实施方式，所述显示面板为液晶显示面板，因此，所述显示面板还包括与所述阵列基板对盒设置的对盒基板以及设置在所述阵列基板与所述对盒基板之间的液晶材料层。
作为本发明的第三个方面，提供一种阵列基板的制造方法，所述阵列基板被划分为多个像素单元，其中，如图4所示，所述制造方法包括：
在步骤S410，形成数据线层，所述数据线层包括多条数据线；
在步骤S420中，形成金属电极图形层，所述金属电极图形层包括多个漏极，所述金属电极图形层与所述数据线层在所述阵列基板的厚度方向间隔设置，每个所述像素单元中均设置有所述漏极；
在步骤S430中，形成像素电极层，所述像素电极层包括多个像素电极，每个所述像素单元中均设置有所述像素电极，所述像素电极与同一个像素单元中的漏极电连接。
利用所述制造方法制得的阵列基板具有较高的良率。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (9)

1.一种阵列基板，所述阵列基板被划分为多个像素单元，所述阵列基板包括像素电极层和数据线层，所述像素电极层包括多个像素电极，每个所述像素单元中都设置有所述像素电极，所述数据线层包括多条数据线，其特征在于，所述阵列基板还包括金属电极图形层，所述金属电极图形层包括与多个所述像素电极一一对应的多个漏极，所述像素电极与所述漏极电连接，所述金属电极图形层与所述数据线层在所述阵列基板的厚度方向间隔设置；
所述像素单元排列为多行多列，每列像素单元对应一条数据线，所述阵列基板包括绝缘层，所述数据线层和所述金属电极图形层分别位于所述绝缘层的厚度方向的两侧，所述金属电极图形层还包括多个源极，所述源极的数量与所述漏极的数量相同，同一列像素单元中的源极与相应的数据线通过贯穿所述绝缘层的过孔电连接；
所述金属电极图形层包括多个栅极，每个像素单元中均设置有所述栅极，所述阵列基板包括有源图形层，所述绝缘层包括层间绝缘层和栅绝缘层，所述层间绝缘层覆盖所述数据线层，所述有源图形层设置在所述层间绝缘层和所述栅绝缘层之间，所述金属电极图形层设置在所述栅绝缘层上。
2.根据权利要求1所述的阵列基板，其特征在于，所述阵列基板包括平坦化层，所述平坦化层覆盖所述金属电极图形层，以使得所述像素电极层和所述金属电极图形层分别位于所述平坦化层厚度方向的两侧，所述像素电极层中的像素电极通过贯穿所述平坦化层的过孔与相应的漏极电连接。
3.根据权利要求1所述的阵列基板，其特征在于，将所述源极与相应的数据线电连接的过孔包括形成为一体的第一过孔部和第二过孔部，所述第一过孔部贯穿所述栅绝缘层，所述第二过孔贯穿所述层间绝缘层，所述第一过孔部与相应的有源层接触，所述漏极通过贯穿所述栅绝缘层的过孔与相应的有源层接触。
4.根据权利要求3所述的阵列基板，其特征在于，所述阵列基板还包括光阻挡层，所述光阻挡层包括多个光阻挡件，所述光阻挡件设置在所述金属电极图形层的入光侧，且所述光阻挡件在所述金属电极图形层上的正投影与至少一个所述栅极的至少一部分重叠。
5.根据权利要求3所述的阵列基板，其特征在于，所述金属电极图形层包括多条栅线，所述栅极形成为所述栅线的一部分。
6.根据权利要求5所述的阵列基板，其特征在于，所述有源层包括两个竖直部和连接在两个竖直部之间的水平部，所述竖直部的长度方向与数据线的长度方向平行，两个所述竖直部中的一个竖直部在所述数据线层上的正投影与相应的数据线重叠，所述栅线上在所述有源图形层上的正投影于所述竖直部重叠的部分形成为所述栅极。
7.根据权利要求1至6中任意一项所述的阵列基板，其特征在于，所述阵列基板还包括钝化层和公共电极层，所述钝化层覆盖所述像素电极层，所述公共电极层设置在所述钝化层上，以使得所述公共电极层和所述像素电极层分别位于所述钝化层厚度方向的两侧，所述公共电极层包括多个公共电极。
8.一种显示面板，所述显示面板包括阵列基板，其特征在于，所述阵列基板为权利要求1至7中任意一项所述的阵列基板。
9.一种用于制造权利要求1至7中任意一项所述的阵列基板的制造方法，所述阵列基板被划分为多个像素单元，其特征在于，所述制造方法包括：
形成数据线层，所述数据线层包括多条数据线；
形成金属电极图形层，所述金属电极图形层包括多个漏极，所述金属电极图形层与所述数据线层在所述阵列基板的厚度方向间隔设置，每个所述像素单元中均设置有所述漏极；
形成像素电极层，所述像素电极层包括多个像素电极，每个所述像素单元中均设置有所述像素电极，所述像素电极与同一个像素单元中的漏极电连接。
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