CN107785419B - A kind of fin field effect transistor and its manufacturing method - Google Patents

Abstract

The present invention provides a fin field effect transistor and a manufacturing method thereof. The method includes: providing a semiconductor substrate; forming a first isolation layer on a first region of the semiconductor substrate; A second isolation layer is formed on the two regions, and the density of the second isolation layer is lower than that of the first isolation layer; the first isolation layer and the second isolation layer are etched to form the first isolation layer defining the fins a trench and a second trench, the width of the second trench is greater than the width of the first trench; filling the first trench and the second trench to form the first fin and the second fin piece. According to the manufacturing method of the fin field effect transistor proposed in the present invention, fins with different widths and effective heights can be obtained.

Description

A kind of fin field effect transistor and its manufacturing method

technical field

The present invention relates to a semiconductor manufacturing process, in particular to a fin field effect transistor and a manufacturing method thereof.

Background technique

The continuous shrinking of the size of semiconductor devices is a major factor driving improvements in integrated circuit manufacturing technology. Due to the limitations of adjusting the thickness of the gate oxide layer and the depth of the source/drain junction, it is difficult to scale conventional planar MOSFET devices to processes below 32 nm, therefore, multi-gate field effect transistors have been developed.

A typical multi-gate field effect transistor is the fin field effect transistor (FinFET), which enables smaller device size and higher performance. The fin field effect transistor includes a fin perpendicular to the substrate, a conductive channel is formed in the fin, and a gate is surrounded on and on both sides of the fin. Compared with the traditional planar structure, the fin field effect transistor realizes a fully depleted working mode, and the gate electrode controls the conduction channel from the three sides of the vertical fin structure, so the fin field effect transistor has better channel control ability and Better sub-threshold slope can provide smaller leakage current, smaller gate delay and greater current drive capability.

Although fin field effect transistors offer improved performance over planar structure field effect transistors, they also present some design challenges. Specifically, conventional MOSFETs are essentially unlimited for device width, while FinFET fins are generally fixed in width and height, so for a given transistor length, the saturation current of the FinFET is fixed of. However, in high performance integrated circuits, transistors with different drive capabilities are often required, such as SRAM (Static Random Access Memory) cells. SRAM is generally composed of 6 MOSs, which need to have different drive currents in order to achieve the best performance of the SRAM cell. However, for the fin field effect transistor, the method can only be achieved by changing the number of fins connected in parallel.

Therefore, it is necessary to provide a method for manufacturing a fin field effect transistor, which can obtain fins with different widths and effective heights.

SUMMARY OF THE INVENTION

In view of the deficiencies of the prior art, the present invention provides a novel method for fabricating a fin field effect transistor, including:

provide semiconductor substrates;

forming a first isolation layer on the first region of the semiconductor substrate;

forming a second isolation layer on the second region of the semiconductor substrate, the second isolation layer having a lower density than the first isolation layer;

etching the first isolation layer and the second isolation layer to form a first trench and a second trench defining a fin, and the width of the second trench is larger than that of the first trench;

The first and second trenches are filled to form first and second fins.

Exemplarily, the method further includes the step of etching back the first isolation layer and the second isolation layer to expose the first fin and the second fin to a predetermined effective height. The effective height is greater than the effective height of the first fin.

Exemplarily, the etching rate and polishing rate of the second isolation layer are greater than the etching rate and polishing rate of the first isolation layer.

Illustratively, the etching step includes forming first and second trenches defining fins by dry etching using a mask, and wet etching the first and second trenches The width of the second trench is made larger than the width of the first trench.

Exemplarily, the method for forming the first fin and the second fin is an epitaxial growth method.

Exemplarily, after the second isolation layer is formed, the step of performing a planarization process to form a stepped height between the first isolation layer and the second isolation layer is further included.

Exemplarily, the planarization process is chemical mechanical polishing.

Exemplarily, the mask used in the etching step is a mask stack.

Exemplarily, the mask stack includes a spin-on carbon layer and a dielectric anti-reflection layer.

Exemplarily, the mask stack includes a silicon antireflection layer and a bottom antireflection layer.

Exemplarily, the width difference between the first fin and the second fin is 3-5 nm.

Exemplarily, the effective height difference between the first fin and the second fin is 50-200 angstroms.

Exemplarily, the method further includes the step of forming a gate structure on the first fin and the second fin.

Exemplarily, the first isolation layer and the second isolation layer are both oxide layers.

The present invention also provides a fin field effect transistor, which is characterized by comprising:

semiconductor substrate;

a first isolation layer located on the first region of the semiconductor substrate, and a second isolation layer located on the second region of the semiconductor, the height of the second isolation layer being less than the height of the first isolation layer;

A first fin separated by the first isolation layer and a second fin separated by the second isolation layer, the width of the first fin is smaller than that of the second fin, the second fin is The height of the fins exposed outside the second isolation layer is greater than the height of the first fins exposed outside the first isolation layer.

Exemplarily, the density of the second isolation layer is less than the density of the first isolation layer.

Exemplarily, the etching rate and polishing rate of the second isolation layer are greater than the etching rate and polishing rate of the first isolation layer.

Exemplarily, a gate structure formed on the first fin and the second fin is also included.

Exemplarily, the width difference between the first fin and the second fin is 3-5 nm.

Exemplarily, the effective height difference between the first fin and the second fin is 50-200 angstroms.

Exemplarily, the first isolation layer and the second isolation layer are both oxide layers.

Compared with the prior art, according to the manufacturing method of the fin field effect transistor proposed by the present invention, fins with different widths and effective heights can be obtained.

Description of drawings

The following drawings of the present invention are incorporated herein as a part of the present invention for understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and their description, which serve to explain the principles of the present invention.

In the attached picture:

FIG. 1 is a schematic cross-sectional view of a device obtained by sequentially performing steps in a method for fabricating a fin field effect transistor in the prior art.

Figure 2 is a flow chart of the steps carried out in sequence in the method according to the invention.

3-11 are schematic cross-sectional views of devices obtained by sequentially implementing the steps of the method according to the present invention;

Detailed ways

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid obscuring the present invention.

It should be understood that the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

1 is a schematic diagram of a method for fabricating a fin field effect transistor using a self-aligned double patterning technique in the prior art: first, a semiconductor substrate 101 is provided, and a hard mask 102 is formed on the semiconductor substrate; selectivity The semiconductor substrate 101 and the hard mask 102 are etched to form fins with shallow trenches formed on both sides of the fins and the top surface of which is still covered with the hard mask 102; Forming a liner isolation layer 103 on the sidewalls and bottoms, and the hard mask 102; filling the shallow trenches with an isolation layer 104 covering the hard mask 102 on top of the fins; performing Annealing treatment; using an etch-back process to remove the hard mask 102 and part of the isolation layer to expose the fins to a predetermined height. However, since the heights of all fins are defined by the same polishing process, all fins in FETs fabricated using this method have the same height, and the width of the fins faces a similar situation.

In order to solve the above problems, the present invention provides a method for fabricating a fin field effect transistor, comprising:

provide semiconductor substrates;

forming a first isolation layer on the first region of the semiconductor substrate;

forming a second isolation layer on the second region of the semiconductor substrate, the density of the second isolation layer is lower than the density of the first isolation layer;

etching the first isolation layer and the second isolation layer to form a first trench and a second trench defining a fin, and the width of the second trench is greater than the width of the first trench;

The first and second trenches are filled to form first and second fins.

It also includes the step of etching back the first isolation layer and the second isolation layer to expose the fins to a predetermined effective height, and the effective height of the second fins is greater than the effective height of the first fins. high.

The etching rate and polishing rate of the second isolation layer are greater than the etching rate and polishing rate of the first isolation layer.

The etching step includes forming first trenches and second trenches defining fins by dry etching using a mask, and making the first trenches and second trenches wet by etching the first trenches and the second trenches. The width of the second trench is greater than the width of the first trench.

The formation method of the fins is an epitaxial growth method.

After the second isolation layer is formed, the step of performing a planarization process to form a stepped height between the first isolation layer and the second isolation layer is further included. The planarization process is a chemical mechanical polishing method.

The mask used in the dry etching step is a mask stack. The mask stack includes a spin-on carbon layer and a dielectric anti-reflection layer or includes a silicon anti-reflection layer and a bottom anti-reflection layer.

The width difference between the first fin and the second fin is 3-5 nm. The effective height difference between the first fin and the second fin is 50-200 angstroms.

Also included is the step of forming a gate structure on the fin.

The first isolation layer and the second isolation layer are both oxide layers.

Compared with the prior art, the present invention provides a method for manufacturing a fin field effect transistor, which can obtain fins with different widths and effective heights.

For a thorough understanding of the present invention, detailed structures and/or steps will be presented in the following description, so as to explain the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions. [Exemplary Embodiment 1]

A method for fabricating a fin field effect transistor according to an embodiment of the present invention will be described in detail below with reference to FIGS. 2 to 11 .

First, step 201 is performed to provide a semiconductor substrate 301 .

Specifically, the semiconductor substrate in the present invention may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (SSOI) -SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

Next, step 202 is performed to form a first isolation layer 302 on the first region of the semiconductor substrate 301 , as shown in FIG. 3 . Exemplarily, the material of the first isolation layer 302 includes oxide, such as silicon oxide. The formation process of the first isolation layer 302 can be chemical vapor deposition, high-density plasma CVD, atomic layer deposition, plasma enhanced atomic layer deposition, pulsed laser deposition or other suitable methods, preferably chemical vapor deposition. deposition method. When the material of the semiconductor substrate 301 is silicon, the formation process of the first isolation layer 302 may also be a thermal oxidation method. Next, as shown in FIG. 4 , a patterned hard mask layer is formed on the surface of the first isolation layer, and the first isolation layer 302 is etched to cover the first region of the semiconductor substrate.

Next, step 203 is performed, as shown in FIG. 5 , a second isolation layer 303 is formed on the second region of the semiconductor substrate, and the density of the second isolation layer is lower than that of the first isolation layer 302 . The formation process of the second isolation layer 303 is similar to that of the first isolation layer. After the second isolation layer 303 is deposited, the first isolation layer 302 and the second isolation layer 303 are planarized, and the planarization process is CMP (Chemical Mechanical Polishing). Illustratively, CMP is performed using a slurry of metal _oxide particles, such as _SiO2 , _Al2O3 , _CeO2 , and the like. The table speed was in the range from 30 rpm to 110 rpm, the down force was in the range from 0.5 psi to 5 psi, and the slurry flow rate was in the range from 50 ml/min to 500 ml/min. Since the density of the second isolation layer material 303 is lower than that of the first isolation layer 302 and its polishing rate is lower than that of the first isolation layer 302 , the first isolation layer 302 and the second isolation layer 303 will be formed after planarization is performed. stepped height.

Next, step 204 is performed to etch the first isolation layer 302 and the second isolation layer 303 to form a first trench 309 and a second trench 310 that define fins, and the width of the second trench 310 is greater than the width of the first trench 309. Since the stepped height of the isolation layer will cause trochoidal effects in the photolithography process, which affects the photolithography effect, in this embodiment, a mask stack including an anti-reflection layer is used to etch the isolation layer. In one embodiment, as shown in FIG. 6a, a spin-coated carbon layer 304 and a dielectric anti-reflection layer (DARC) 305 are formed on the surfaces of the first isolation layer 302 and the second isolation layer 303 in sequence. The spin-on carbon layer 304 can serve as a planarizing film formed in a region with a step difference, an anti-reflection film, and a mask with etch selectivity to the underlying material sheet. The spin-on carbon layer 304 preferably includes a carbon-rich polymer, wherein the carbon element accounts for 85 wt % to 90 wt % of the total molecular weight. The DARC layer 305 may be a silicon oxynitride layer (SiON), and the thickness may be 20 nm to 60 nm. A photoresist 306 is formed on the DARC layer 305, and the photoresist is exposed and developed to form a patterned photoresist. Using the patterned photoresist as a mask, the anti-reflection layer is etched, and the anti-reflection layer is used as a hard mask to etch the isolation layer to form a first trench 309 and a second fin defining a fin. The depths of the trenches 310, the first trenches 309 and the second trenches 310 are 2000 angstroms to 3000 angstroms, as shown in FIG. 7 .

In another embodiment, as shown in FIG. 6b, a silicon anti-reflection layer 307, a bottom anti-reflection layer (BARC) 308 and a photoresist layer 306 are sequentially formed on the surfaces of the first isolation layer 302 and the second isolation layer 303 . First, a silicon anti-reflection layer 307, such as silicon oxynitride or silicon nitride, is spin-coated on the surfaces of the first isolation layer 302 and the second isolation layer 303, and then a layer of BARC 308, such as polyimide or polyimide, is formed thereon. Sulfones. Illustratively, the BARC is formed by spin-coating a substrate with a monomer-containing solution and initiating a polymerization reaction, and the thickness of the formed BARC ranges from 300 angstroms to 5000 angstroms. Baking is performed at a temperature ranging from 100°C to 500°C to crosslink the BARC. A photoresist 306 is formed on the BARC, and the photoresist is exposed and developed to form a patterned photoresist. Using the patterned photoresist as a mask, the anti-reflection layer is etched, and the anti-reflection layer is used as a hard mask to etch the isolation layer to form a first trench 309 and a second fin defining a fin. The depths of the trenches 310, the first trenches 309 and the second trenches 310 are 2000 angstroms to 3000 angstroms, as shown in FIG. 7 .

Next, a second step of etching is performed on the trenches by wet etching, as shown in FIG. 8 . The solution used in the wet etching includes a hydrofluoric acid solution, a hydrofluoric acid solution, and the like. Since the wet etching rate of the second isolation layer material is higher than that of the first isolation layer, the width of the second trench 310 after wet etching is greater than the width of the first trench 309 . Exemplarily, the difference between the widths of the first trench and the second trench is 3-5 nm.

Next, step 205 is performed, as shown in FIG. 9 , the first trenches 309 and the second trenches 310 are filled to form the first fins 311 and the second fins 312 . Specifically, silicon or polysilicon is epitaxially grown in the trench to fill the trench. The silicon or polysilicon can be selected from decompression epitaxy, low temperature epitaxy, selective epitaxy, liquid phase epitaxy, heteroepitaxy, molecular beam epitaxy, and the like. The epitaxy process may use gaseous and/or liquid precursors. The fins may also be silicon germanium (SiGe) formed by a silicon germanium epitaxial deposition process. The semiconductor material may be doped by adding impurities to the starting material of the epitaxy process during the growth of the fin or subsequently adding impurities to the growth process of the semiconductor material by an ion implantation process. Next, a chemical mechanical polishing (CMP) process is performed to planarize the first fins 311 and the second fins 312 .

Next, step 206 is performed, as shown in FIG. 10 , the first isolation layer 302 and the second isolation layer 303 are etched back to expose the first fins 311 and the second fins 312 to a predetermined effective height , the effective height of the second fins 312 is greater than the effective height of the first fins 311 . Since the thickness of the first isolation layer 302 is greater than the thickness of the second isolation layer 303 , the effective height of the first fins 311 is smaller than the effective height of the second fins 312 . Exemplarily, the effective height difference between the first fin and the second fin is 50-200 angstroms. The etch-back process may be a dry etching process, a wet etching process, other etching processes, or a combination thereof. In an example, plasma etching is used, the source gas for the etching uses a mixture of HBr, Cl2, and _O2 , and the flow rate of the source gas ranges from ₅ ml/min to 1000 ml/min. The pressure is in the range of 1 mTorr to 100 mTorr. The radio frequency (RF) bias power for the etching process may be about 30W to about 400W. In another embodiment, the isolation layer may also be etched back using dilute hydrofluoric acid (DHF). Exemplarily, the concentration volume percentage of the diluted hydrofluoric acid (DHF) is 1:50˜1:1000.

Next, a gate structure 313 is formed on the fin, as shown in FIG. 11 . The gate structure 313 may include a gate dielectric layer and a gate electrode. The gate dielectric layer includes dielectric materials such as silicon oxide, high-k dielectric materials, other suitable dielectric materials, or combinations thereof. Examples of high-k dielectric materials include HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, and the like. The gate electrode includes polysilicon and/or metals including Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof thing. The gate structure may include many other layers such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. The gate structure is formed by suitable processes such as deposition, photolithographic patterning and etching processes. Deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like. Photolithographic patterning processes include photoresist coating (eg, spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, cleaning, drying (eg, hard bake), other suitable processes, or its combination. Alternatively, the lithographic exposure process may be implemented or replaced by other methods such as maskless lithography, e-beam writing, or ion beam writing. Etching processes include dry etching, wet etching, and/or other etching methods.

It should be noted that this embodiment also includes the steps of forming low-doped source/drain (LDD) at both ends of the fin, and then forming heavily-doped source/drain (not shown). Back end of line (BEOL) processing can also be performed. For example, a layer of insulating material may be formed on the structure by deposition and chemical mechanical polishing, contact holes may be formed in the insulating layer by photoresist masking and etching processes, the contact holes may be filled, metal interconnections and the like may be formed for electrical connections structure, etc.

So far, the process steps implemented by the method according to the first exemplary embodiment of the present invention are completed. It can be understood that, the method for fabricating a semiconductor device in this embodiment not only includes the above steps, but may also include other required steps before, during or after the above steps, which are all included in the scope of the fabrication method in this embodiment.

Compared with the prior art, the manufacturing method of the fin field effect transistor proposed by the present invention can obtain fins with different widths and effective heights.

[Exemplary Embodiment 2]

Referring to FIG. 11 , there is shown a schematic cross-sectional view of the fin field effect transistor of the device obtained according to the manufacturing method provided by the present invention. The fin field effect transistor provided by the present invention includes: a semiconductor substrate 301 , a first isolation layer 302 , a second isolation layer 303 , a first fin 311 , a second fin 312 , and a gate structure 313 .

The semiconductor substrate 301 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon germanium-on-insulator (S-SiGeOI) , silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).

The first isolation layer 302 is located in a first region on the semiconductor substrate. Exemplarily, the material of the first isolation layer 302 includes oxide, such as silicon oxide. The formation process of the first isolation layer 302 can be chemical vapor deposition, high-density plasma CVD, atomic layer deposition, plasma enhanced atomic layer deposition, pulsed laser deposition or other suitable methods, preferably chemical vapor deposition. deposition method. When the material of the semiconductor substrate 301 is silicon, the formation process of the first isolation layer 302 may also be a thermal oxidation method.

The second isolation layer 303 is located in a second region on the semiconductor substrate. Exemplarily, the material of the second isolation layer 303 includes oxide, such as silicon oxide, and the formation process thereof is similar to that of the first isolation layer. The density of the material of the second isolation layer is lower than that of the first isolation layer 302, and its etching rate and polishing rate are higher than those of the first isolation layer 302. Therefore, after the planarization process is performed, the second isolation layer 303 is smaller than the thickness of the first isolation layer 302 .

The first fins 311 and the second fins 312 are respectively formed in the first isolation layer 302 and the second isolation layer 303 . Specifically, first trenches 309 and second trenches 310 defining fins are formed in the first isolation layer 302 and the second isolation layer 303 by dry etching and wet etching, respectively. The wet etching rate of the second isolation layer 303 is higher than that of the first isolation layer 302, so the width of the second trench 310 is larger than that of the first trench 309; then the trench is filled by epitaxial growth to form The first fins 311 and the second fins 312 are planarized to make the upper surfaces of the first fins 311 and the second fins 312 flush; then the first isolation layer 302 and all the The second isolation layer 303 exposes the first fins 311 and the second fins 312 to a predetermined height. Since the width of the second trench 310 is greater than that of the first trench 309, the width of the second fin 312 is greater than that of the first fin 311; The upper surfaces of the two fins 312 are flush, and the thickness of the first isolation layer 302 is greater than that of the second isolation layer 303 , so the effective height of the second fins 312 is greater than that of the first fins 311 . The width difference between the first fin and the second fin is 3-5 nm, and the effective height difference between the first fin and the second fin is 50-200 angstroms.

The gate structure 313 includes a gate dielectric layer formed on the isolation layer and the fins, a gate dielectric layer across the fins, and a gate electrode formed on the gate dielectric layer. The gate dielectric layer includes dielectric materials such as silicon oxide, high-k dielectric materials, other suitable dielectric materials, or combinations thereof. Examples of high-k dielectric materials include HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, and the like. The gate electrode includes polysilicon and/or metals including Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof thing. The gate structure 313 may include many other layers such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. The gate structure 313 is formed by suitable processes such as deposition, photolithographic patterning, and etching processes.

Compared with the prior art, the fin field effect transistor proposed by the present invention has fins with different widths and effective heights.

The present invention has been described by the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can also be made according to the teachings of the present invention, and these variations and modifications all fall within the protection claimed in the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (20)

1. a manufacturing method of a fin field effect transistor, is characterized in that, comprises: provide semiconductor substrates; forming a first isolation layer on the first region of the semiconductor substrate; A second isolation layer is formed on the second region of the semiconductor substrate, the density of the second isolation layer is lower than that of the first isolation layer, and the etching rate of the second isolation layer is higher than that of the first isolation layer an etch rate of the isolation layer; etching the first isolation layer and the second isolation layer to form a first trench and a second trench defining a fin, and the width of the second trench is greater than the width of the first trench; The first and second trenches are filled to form first and second fins. 2. The method of claim 1, further comprising etching back the first isolation layer and the second isolation layer to expose the first fin and the second fin for a predetermined effective In the step of height, the effective height of the second fin is greater than the effective height of the first fin. 3. The method of claim 1, wherein the polishing rate of the second isolation layer is greater than the polishing rate of the first isolation layer. 4. The method of claim 1, wherein the etching step comprises forming first and second trenches defining fins by dry etching using a mask, and wet etching The first trench and the second trench are such that the width of the second trench is larger than the width of the first trench. 5 . The method of claim 1 , wherein the first fin and the second fin are formed by an epitaxial growth method. 6 . 6 . The method according to claim 3 , wherein after forming the second isolation layer, further comprising performing a planarization process, so that the first isolation layer and the second isolation layer form a stepped height. 7 . step. 7. The method of claim 6, wherein the planarization process is a chemical mechanical polishing method. 8. The method according to claim 4, wherein the mask used in the etching step is a mask stack. 9. The method of claim 8, wherein the mask stack comprises a spin-on carbon layer and a dielectric anti-reflection layer. 10. The method of claim 8, wherein the mask stack comprises a silicon anti-reflection layer and a bottom anti-reflection layer. 11 . The method of claim 1 , wherein a difference in width between the first fin and the second fin is 3-5 nm. 12 . 12. The method of claim 2, wherein an effective height difference between the first fin and the second fin is 50-200 angstroms. 13. The method of claim 1, further comprising the step of forming a gate structure on the first fin and the second fin. 14. The method of claim 1, wherein the first isolation layer and the second isolation layer are both oxide layers. 15. A fin field effect transistor prepared by the method of one of claims 1-14, characterized in that, comprising: semiconductor substrate; a first isolation layer on a first region of the semiconductor substrate, and a second isolation layer on a second region of the semiconductor substrate, the height of the second isolation layer being less than the height of the first isolation layer , the density of the second isolation layer is smaller than the density of the first isolation layer, and the etching rate of the second isolation layer is greater than the etching rate of the first isolation layer; A first fin separated by the first isolation layer and a second fin separated by the second isolation layer, the width of the first fin is smaller than that of the second fin, the second fin is The height of the fins exposed outside the second isolation layer is greater than the height of the first fins exposed outside the first isolation layer. 16 . The fin field effect transistor of claim 15 , wherein a polishing rate of the second isolation layer is greater than a polishing rate of the first isolation layer. 17 . 17. The fin field effect transistor of claim 15, further comprising a gate structure formed on the first fin and the second fin. 18 . The fin field effect transistor of claim 15 , wherein a difference in width between the first fin and the second fin is 3-5 nm. 19 . 19 . The fin field effect transistor of claim 15 , wherein an effective height difference between the first fin and the second fin is 50-200 angstroms. 20 . 20 . The fin field effect transistor of claim 15 , wherein the first isolation layer and the second isolation layer are oxide layers. 21 .

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