CN107785246B - Method for ion implantation of substrate - Google Patents
Method for ion implantation of substrate Download PDFInfo
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- CN107785246B CN107785246B CN201610762277.7A CN201610762277A CN107785246B CN 107785246 B CN107785246 B CN 107785246B CN 201610762277 A CN201610762277 A CN 201610762277A CN 107785246 B CN107785246 B CN 107785246B
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- substrate
- material layer
- ion implantation
- layer
- photoresist layer
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- 239000000758 substrate Substances 0.000 title claims abstract description 69
- 238000005468 ion implantation Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 50
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 41
- 239000002253 acid Substances 0.000 claims description 28
- 239000003513 alkali Substances 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 4
- 239000011358 absorbing material Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000002791 soaking Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 73
- 239000002585 base Substances 0.000 description 18
- 239000000126 substance Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
The invention discloses a method for carrying out ion implantation on a substrate, which comprises the steps of firstly providing a substrate, then forming a material layer on the substrate, wherein the thickness of the material layer is between 100 angstroms and 200 angstroms, then forming a patterned photoresist layer on the material layer, and carrying out an ion implantation step on the substrate.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing processes, in particular to a method for improving the yield of an ion implantation manufacturing process.
Background
In a semiconductor manufacturing process, an ion implantation manufacturing process is very commonly applied. Such as forming the source/drain of a transistor, or forming an n-well, a p-well, etc. in a substrate, it is necessary to implant ions of a specific species into the substrate. Therefore, the quality of the ion implantation process will affect the yield of the subsequent semiconductor devices. Various possible problems encountered in ion implantation also need to be overcome by finding suitable methods.
Disclosure of Invention
The invention provides a method for carrying out ion implantation on a substrate, which comprises the steps of firstly providing a substrate, then forming a material layer on the substrate, wherein the thickness of the material layer is between 100 and 200 angstroms, then forming a patterned photoresist layer on the material layer, and carrying out an ion implantation step on the substrate.
The invention is characterized in that a material layer is additionally formed on the substrate and covers the substrate, when the substrate has some residues (such as acid or alkali remained after cleaning, or the substrate has the characteristics of acid or alkali), the material layer can cover the residues, the stripping or the residue of the photoresist layer caused by the direct contact of acid/alkali substances and the photoresist layer is avoided, and the thickness of the material layer is only 100 to 200 angstroms, so the subsequent exposure, development and ion implantation steps are not influenced.
Drawings
FIG. 1 is a schematic view of a semiconductor structure of the present invention including acid/base material on a substrate;
FIG. 2 is a schematic view of a semiconductor structure of the present invention forming a material layer and a photoresist layer on a substrate;
FIG. 3 is a schematic diagram of the semiconductor structure after a developing step and then an ion implantation step.
Description of the main elements
10. Substrate
12. Acid/base material
14. Material layer
16. Photoresist layer
16' photoresist layer
P1 ion implantation step
Detailed Description
In order to make the present invention more comprehensible to those skilled in the art, preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.
For convenience of explanation, the drawings are only schematic to facilitate understanding of the present invention, and the detailed proportions thereof may be adjusted according to design requirements. The above and below relationships between elements in the figures are understood by those skilled in the art to refer to the relative positions of the objects, and therefore all the elements can be turned over to present the same elements, and all the elements should be included in the scope of the disclosure.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating an acid/alkali substance contained on a substrate according to the present invention. A substrate 10 is provided, and the substrate 10 may include a silicon substrate, a sapphire substrate, a silicon oxide layer, a silicon nitride layer, etc. In the present invention, it is contemplated that an ion implantation step be performed on the substrate 10, and that the substrate 10 include a portion of the acid/base species 12. The acid/base material 12 comprises an acid material or a base material and is typically not thick, less than about 100 angstroms. Applicants have found that these acid/base species 12 are generally derived from the nature of the substrate itself, i.e., having an acid/base character (e.g., sapphire substrates, which are inherently rich in acid/base species, or silicon nitride, which is inherently more basic, and silicon oxide, which is inherently more acidic). Or when the substrate is subjected to a cleaning step, the cleaning step usually comprises the step of soaking the substrate in sulfuric acid and hydrogen peroxide, which may result in residual acid or alkali on the surface of the substrate after the cleaning step. These acid/base species or acid/base residues will have an impact on the subsequent exposure and development steps. For example, when the acid/base substance 12 includes an acid value, if the photoresist layer directly contacts the acid value and directly covers the acid value, the photoresist layer may be peeled off, thereby affecting the accuracy and yield of the ion implantation step (where part of the photoresist layer is peeled off as a mask) when the photoresist layer is formed on the substrate. On the contrary, if the acid/base substance 12 contains base numbers, when the photoresist layer covers the base numbers and is patterned, the base numbers directly contact the photoresist layer, may react with the photoresist layer and remain on the substrate, so that the patterned photoresist layer left on the substrate will be different from the originally expected patterned photoresist layer, which also affects the accuracy and yield of the ion implantation step.
To avoid this, please refer to fig. 2, which illustrates a schematic diagram of forming a material layer and a photoresist layer on a substrate according to the present invention. As shown in fig. 2, a material layer 14 and a photoresist layer 16 are formed on the substrate 10. Of particular note, but not limiting, is that the material layer 14, which is in direct contact with the substrate 10, comprises an Organic Dielectric Layer (ODL), and more particularly, may be selected from the ODL series products available from Shinatsu corporation, or the sopa 30-301 products available from nissan Chemical corporation. The material layer 14 of the present invention mainly includes two characteristics, one of which is a thickness of only 100 angstroms (angstroms) to 200 angstroms, and can be formed on the substrate 10 by spin coating or the like. Another feature is that the material layer does not contain a light absorbing material, and thus the material layer 14, unlike the photoresist layer 16, is not removed in a subsequent development step of the photoresist layer 16. The material layer 14 is formed on the substrate 10 and completely covers the acid/base substance 12, so that the photoresist layer 16 formed next does not directly contact the acid/base substance 12. The above-mentioned problems caused by direct contact of the photoresist layer to an acid value or a base value can also be avoided.
Next, as shown in FIG. 3, a developing step is performed to pattern the photoresist layer to form a photoresist layer 16', and then an ion implantation step P1 is performed on the substrate 10. As described above, since the material layer 14 does not include the light absorbing material, it is not affected by the developing step and is removed. The substrate 10 is then subjected to an ion implantation step P1 to implant specific ions into the substrate, such as source/drain regions of transistors, or n-type wells, P-type wells, etc., for example, but the invention is not limited thereto. It is noted that the thickness of the material layer 14 mentioned above is only 100 to 200 angstroms, and the applicant has found that the thickness is thin enough so that the material layer 14 remains on the substrate 10 even when the ion implantation step P1 is performed, and the result of the ion implantation step P1 is not affected. In other words, the required ions can be implanted into the substrate smoothly to form the device to be formed. The photoresist layer 16' and the material layer 14 may be removed by plasma in a subsequent step after the ion implantation step is completed.
The material layer 14 of the present invention mainly includes an Organic Dielectric Layer (ODL) or other similar materials. However, the material layer of the present invention is different from the Organic Dielectric Layer (ODL) used in the multi-layer photoresist in the general semiconductor manufacturing process in the following ways: first, the above-mentioned thicknesses are only 100 to 200 angstroms, and the ODL generally used for a multi-layer photoresist layer has a thickness of at least more than 500 angstroms. A larger thickness may not be desirable, and the material layer is thin enough to not affect the characteristics of the subsequent ion implantation step. The material layer does not contain light-absorbing material, so the material layer is not removed in the developing step, thereby achieving the purpose of protecting the photoresist layer from direct contact with acid/alkali substances.
It is also important that the ion implantation step be performed immediately after the patterned photoresist layer is formed on the substrate. Therefore, the subsequent fabrication processes are different from those of the ODL generally applied to the multi-layer photoresist. More specifically, the substrate provided by the present invention is not suitable for performing an etching step on the substrate in the previous or subsequent steps, which would otherwise damage the electrical properties of the implanted ion regions (e.g., damage the electrical properties of the source/drain regions, etc.), if the substrate is intended to be used in the subsequent ion implantation step. The subsequent steps of the ODL layer applied to the multi-layer photoresist are usually to pattern the photoresist, and to perform an etching step on the underlying substrate or other material layers with the patterned multi-layer photoresist as a protective layer, in which case the substrate is usually not suitable for the ion implantation step. In other words, the present invention performs an ion implantation step after forming the material layer and patterning the photoresist layer. Therefore, no etching step is performed on the substrate after the material layer is formed, and no other steps are performed between the step of performing the ion implantation after the photoresist layer is patterned.
The invention is characterized in that a material layer is additionally formed on the substrate, the material layer covers the substrate, when the substrate has some residues (such as acid or alkali remained after the cleaning step is carried out, or the substrate has the characteristics of acid or alkali), the material layer can cover the residues, the stripping or the residue of the photoresist layer caused by the direct contact of acid/alkali substances and the photoresist layer is avoided, and the thickness of the material layer is only 100 to 200 angstroms, so the subsequent exposure development and ion implantation steps are not influenced.
The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.
Claims (8)
1. A method of ion implanting a substrate, comprising:
providing a substrate;
carrying out a cleaning step on the substrate, wherein after the cleaning step is carried out, at least one residue is formed on the substrate, and the residue comprises a residual acid or a residual alkali;
forming a material layer on the substrate, wherein the material layer comprises an organic dielectric layer and has a thickness of 100 to 200 angstroms;
forming a patterned photoresist layer on the material layer, the material layer directly contacting the substrate and the patterned photoresist layer; and
performing an ion implantation step on the substrate, wherein a portion of the material layer exposed by the patterned photoresist layer remains on the substrate during the ion implantation step, wherein no etching step is performed on the substrate after the material layer is formed on the substrate.
2. The method of claim 1, wherein the material layer does not comprise a light absorbing material.
3. The method of claim 1, wherein the ion implantation step is performed while the material layer remains on the substrate.
4. The method of claim 1, wherein the substrate material comprises silicon oxide or silicon nitride.
5. The method of claim 1, wherein the substrate comprises a sapphire substrate.
6. The method of claim 1, wherein the step of performing the ion implantation after the forming of the patterned photoresist layer comprises performing no other steps.
7. The method of claim 1, wherein the material layer completely covers the residue.
8. The method of claim 1, wherein the cleaning step comprises a step of soaking in a solution of sulfuric acid and hydrogen peroxide.
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CN201610762277.7A CN107785246B (en) | 2016-08-30 | 2016-08-30 | Method for ion implantation of substrate |
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CN201610762277.7A CN107785246B (en) | 2016-08-30 | 2016-08-30 | Method for ion implantation of substrate |
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CN107785246B true CN107785246B (en) | 2022-10-14 |
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CN108470677A (en) * | 2018-03-29 | 2018-08-31 | 上海华力集成电路制造有限公司 | The photoetching technological method of HKMG technique intermediate ion implanted layers |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5372914A (en) * | 1992-03-24 | 1994-12-13 | Kabushiki Kaisha Toshiba | Pattern forming method |
TW472303B (en) * | 2001-02-26 | 2002-01-11 | United Microelectronics Corp | Ion implantation method |
CN101794071A (en) * | 2008-09-22 | 2010-08-04 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
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JPH10207072A (en) * | 1997-01-20 | 1998-08-07 | Sony Corp | Lithography method |
KR100265014B1 (en) * | 1997-12-31 | 2000-11-01 | 김영환 | Manufacturing Method of Semiconductor Device |
JP2001110013A (en) * | 1999-10-05 | 2001-04-20 | Fujitsu Ltd | Method for manufacturing thin film magnetic head |
TW527699B (en) * | 2002-04-16 | 2003-04-11 | Macronix Int Co Ltd | Method for manufacturing a semiconductor device |
JP2004014841A (en) * | 2002-06-07 | 2004-01-15 | Fujitsu Ltd | Semiconductor device and manufacturing method thereof |
US7030031B2 (en) * | 2003-06-24 | 2006-04-18 | International Business Machines Corporation | Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material |
JP2007214318A (en) * | 2006-02-09 | 2007-08-23 | Casio Comput Co Ltd | Wiring formation method |
CN101207027B (en) * | 2006-12-22 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device grids |
KR20090125422A (en) * | 2008-06-02 | 2009-12-07 | 주식회사 동부하이텍 | Manufacturing Method of Semiconductor Device |
CN101673674B (en) * | 2008-09-10 | 2012-02-29 | 中芯国际集成电路制造(北京)有限公司 | Polysilicon pre-doping method |
CN101740334B (en) * | 2008-11-13 | 2012-10-03 | 中芯国际集成电路制造(北京)有限公司 | Photoetching pretreating method and photoetching method |
KR101094332B1 (en) * | 2009-11-24 | 2011-12-19 | 주식회사 에스앤에스텍 | Blank mask, method of manufacturing the same and photomask manufacturing method using the same |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5372914A (en) * | 1992-03-24 | 1994-12-13 | Kabushiki Kaisha Toshiba | Pattern forming method |
TW472303B (en) * | 2001-02-26 | 2002-01-11 | United Microelectronics Corp | Ion implantation method |
CN101794071A (en) * | 2008-09-22 | 2010-08-04 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
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