CN107768254A - A kind of reduced graphene electrode MoS2The preparation method of field-effect transistor - Google Patents

Abstract

The purpose of the present invention is to provide a method for large-scale preparation of high-performance hybrid structure graphene electrode MoS2 field effect transistor, the method directly CVD grows MoS2 on _SiO2 /Si substrate and carries out MoS2 pattern etching, utilizes thermal The scanning probe technology directly writes the size and shape of the graphene oxide (GO) pattern, and the graphene electrode is obtained by spin-coating GO and performing thermal reduction to form a large-scale graphene electrode MoS2 field effect transistor. This method uses a thermal scanning probe to directly write the shape and size of spin-coated GO, and uses thermally reduced GO as an electrode to improve the contact resistance and mobility of MoS2 field effect transistors. Single-layer MoS2 has many excellent electrical properties, such as a large band gap (1.8eV) and a large on-off ratio (~10 ⁸ ). The use of graphene electrodes increases charge injection and improves the electrical performance of MoS2 field effect transistors. The graphene electrode MoS2 field effect transistor prepared by the method has simple process and good performance, and can be applied in large-scale integrated logic circuits. Because this method has a huge market prospect, it can promote its commercial application.

Description

A kind of preparation method of reduced graphene electrode MoS2 field effect transistor

technical field

The invention relates to a method for large-scale preparation of high-performance MoS2 field-effect transistors in micro-nano electronics manufacturing.

Background technique

In the past ten years, the key to the development of digital logic circuits is to manufacture smaller metal-oxide-semiconductor transistors. When the gate length of traditional transistors is less than 10nm, the stability of transistors manufactured by traditional silicon processes will deteriorate (short channel quantum effect), and 10nm will become the limit of silicon-based transistors. Since the discovery of graphene by Geim et al. in 2004, two-dimensional materials with excellent performance have attracted the attention of researchers from all over the world. Single-layer MoS2 has a bandgap of 1.8eV and an on-off ratio close to 10 ⁸ , making it a potential channel material for high-performance field-effect transistors. Due to the mismatch between the electron affinity of MoS2 and the metal work function and the lack of dangling bonds on the surface of MoS2 with atomic thickness, large contact resistance will appear when directly depositing commonly used metal electrodes, which will affect the performance. In order to better improve the electrical performance of MoS2 field effect transistors, it is necessary to use certain methods to improve the contact resistance between MoS2 and electrodes.

At present, the methods for improving contact resistance mainly include selecting low work function metals as electrodes, chemical doping, and graphene electrode methods. However, these methods all have certain deficiencies. Using low work function metals as electrodes can reduce the Schottky barrier between metal electrodes and MoS2 to a certain extent, thereby reducing contact resistance. However, since the monolayer MoS2 surface does not have dangling bonds, it is difficult to form covalent bonds between the metal electrode and the atomically thick channel material, thereby degrading the electrical performance. In addition, the Schottky barrier cannot be completely eliminated due to the incomplete matching of the work function. Chemical doping is an effective way to reduce the contact resistance of conventional bulk transistors, but the application on atomic-scale MoS2 requires strictly controlled conditions to prevent damage to the channel material properties. Due to the unique relationship between the linear dispersion of graphene and the finite density of states, the work function and Fermi level of graphene can be adjusted by the gate voltage to achieve a good match with MoS2. Graphene electrodes have also become recognized as an excellent method for improving contact resistance. However, since the cleanliness of the interface between graphene and MoS2 will directly affect the performance of the device, traditional photolithography technology is difficult to apply to the preparation of high-performance MoS2 field effect transistors due to the problem of photoresist residue. The currently used dry transfer method can obtain high-performance graphene electrode MoS2 field effect transistors, but it is only suitable for theoretical research and not suitable for large-scale preparation.

Contents of the invention

For the current preparation of high-performance MoS2 field effect transistors, the preparation process is complicated and not suitable for large-scale manufacturing. The invention proposes a method for preparing graphene electrodes by patterned GO thermal reduction.

By using thermal scanning probe direct writing technology, MoS2 is directly grown on SiO ₂ /Si substrate and patterned and etched. The shape and size of patterned GO were directly written by thermal nanoprobe processing technology, and large-scale graphene electrodes were prepared by thermal reduction method. The invention solves the problem of resist residue when graphene is patterned by traditional photolithography technology, and simultaneously proposes a simple and efficient process for preparing MoS2 field effect transistors from graphene electrodes.

Description of drawings

Fig.1 Schematic diagram of CVD growth of MoS2 on SiO ₂ /Si substrate and patterned etching

Figure 2 Schematic diagram of thermally reduced graphene oxide electrode

Figure 3 Schematic diagram of evaporation Au/Ti electrode

In the figure: 1—SiO ₂ /Si substrate; 2—few layer MoS2; 3—single layer graphene; 4—Au/Ti electrode.

Detailed ways

The substantive features and remarkable progress of the present invention will be further described below through specific implementation, but the present invention is by no means limited to the described embodiments.

The specific implementation steps are as follows:

1. Place 0.03g MoO ₃ powder and 0.01g S powder in different quartz cups in the tube furnace. The distance between MoO ₃ and S powder is kept at 18-20cm. Place the _SiO2 /Si substrate above the _MoO3 powdered quartz cup. Heat the tube furnace to 650° C. and pass Ar gas (10-20 sccm) into the tube furnace for 30-60 min to obtain a single layer of MoS2.

2. On the prepared MoS2 sample, deposit PPA/SiO ₂ /PPA (20nm/3nm/9nm) respectively, and use a thermal scanning probe to directly write the size and shape of the desired MoS2 channel. The 9nm PPA is thinned by O ₂ /N ₂ reactive ion etching method, then the SiO ₂ layer is etched by CHF ₃ reactive ion etching, and finally the 20nm PPA layer and MoS2 are etched by O ₂ reactive ion etching to obtain the required MoS2 ditch. As shown in Figure 1.

3. Deposit 20nm PPA on the surface of the patterned MoS2 channel, and use a thermal scanning probe to directly write the size and shape of the graphene oxide spin-coated region. Spin-coat 0.5 μL GO solution (0.5 mg/ml) on the substrate, and homogenize the gel at 1000-1500 r/min for 1 min. as shown in picture 2.

4. Apply a load force of 100nF on the tip of the probe, and adjust the temperature of the tip to 250-300°C at the same time, and perform scanning thermal reduction on the surface of GO.

5. Deposit 100-200nm polymethylcycloheximide (PMGI) and 20nm phenylpropanolamine hydrochloride (PPA) on the SiO ₂ /Si substrate respectively, and use thermal scanning probe nanofabrication technology to directly write electrodes Graphics, vapor-deposited Au/Ti electrodes with a thickness of 60/20nm. As shown in Figure 3.

Claims (5)

1. a kind of reduction graphene electrode MoS The preparation method of field effect transistor is characterized in adopting following steps: (1) Directly grow few-layer MoS2 material on SiO ₂ /Si substrate, and use thermal scanning probe nanofabrication technology to directly write the shape and size of MoS2 channel required. (2) Using thermal scanning probe technology to directly write the graphene electrode pattern and spin-coat GO. (3) Thermal reduction of GO using a thermal scanning probe to obtain patterned graphene. 2. by a kind of reduced graphene electrode MoS2 described in claim 1 The preparation method of field effect transistor is characterized in that: in step (1), CVD grows MoS2 condition is: MoO3 powder 0.03g, _S powder 0.01g, MoO The distance between ₃ and S powder is 18-20 cm, and the SiO ₂ /Si substrate is placed above the MoO ₃ powder quartz cup. Introduce Ar gas (10-20 sccm) at a temperature of 650°C for 30-60 minutes. 3. by a kind of reduction graphene electrode MoS2 described in claim 1 The preparation method of field effect transistor is characterized in that: in the step (1) MoS is etched The condition of channel is: deposition PPA/SiO ₂ /PPA (20nm /3nm/9nm), and use a thermal scanning probe to directly write the size and shape of the desired MoS2 channel. The 9nm PPA is thinned by O ₂ /N ₂ reactive ion etching method, then the SiO ₂ layer is etched by CHF ₃ reactive ion etching, and finally the 20nm PPA layer and MoS2 are etched by O ₂ reactive ion etching to obtain the required MoS2 ditch. 4. a kind of reduced graphene electrode MoS by claim 1 The preparation method of field effect transistor is characterized in that: in the step (2), spin-coating condition is: the GO solution of 0.5 μ L (GO content 0.5mg/ml) , uniform glue at 1000~1500r/min for 1min. 5. The method for preparing a MoS2 field-effect transistor with a reduced graphene electrode according to claim 1, wherein the thermal reduction conditions in step (3) are: probe load force 100nF, needle tip temperature 200-250°C.