CN107766282B - A design method of an eight-way server backplane and a double-deck interconnection system - Google Patents
A design method of an eight-way server backplane and a double-deck interconnection system Download PDFInfo
- Publication number
- CN107766282B CN107766282B CN201711022364.XA CN201711022364A CN107766282B CN 107766282 B CN107766282 B CN 107766282B CN 201711022364 A CN201711022364 A CN 201711022364A CN 107766282 B CN107766282 B CN 107766282B
- Authority
- CN
- China
- Prior art keywords
- computing
- boards
- upi
- signals
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000005192 partition Methods 0.000 claims description 7
- 238000000638 solvent extraction Methods 0.000 abstract 1
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000003993 interaction Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Abstract
本发明公开一种八路服务器背板与双扣板互联系统的设计方法，涉及服务器板卡设计技术领域；基于NUMA的多物理层分区，利用中背板及两块UPI扣板将两个4s系统的计算板互联组成8S系统，其中中背板位于计算板前，与两个计算板互联，交互UPI信号、Misc信号、时序信号、管理信号，并且通过中背板的连接器分别连接位于两个计算板前方的CPU，实现两个计算板的前方CPU间的互联；两块UPI扣板分别位于两个计算板后，与计算板交互UPI信号、Misc信号、时序信号，并且通过UPI扣板的连接器分别连接位于两个计算板后方的CPU，实现两个计算板的后方CPU间的互联。
The invention discloses a design method of an eight-way server backplane and a double-duck board interconnection system, and relates to the technical field of server board design; NUMA-based multi-physical layer partitioning uses a mid-backplane and two UPI boards to connect two 4s systems The computing boards are interconnected to form an 8S system, in which the middle backplane is located in front of the computing board, interconnected with the two computing boards, interacting with UPI signals, Misc signals, timing signals, and management signals, and is connected to the two computing boards through the connectors on the middle backplane. The CPU in front of the board realizes the interconnection between the front CPUs of the two computing boards; the two UPI boards are located behind the two computing boards, respectively, and exchange UPI signals, Misc signals, and timing signals with the computing boards, and are connected through the UPI board. The controllers are respectively connected to the CPUs located behind the two computing boards to realize the interconnection between the rear CPUs of the two computing boards.
Description
Technical Field
The invention discloses a design method of an eight-path server backboard and double-buckle-board interconnection system, and relates to the technical field of server board design.
Background
The multiple processors and IO resources of the computer system may be physically divided, so that a multiprocessor computer system is divided into multiple independent multiprocessor systems, and these divided computer systems may also be coupled into a complete computer system. At present, there is an 8-way server system, which is characterized by comprising 2 independent computing nodes, wherein each computing node is completely the same, and each computing node is provided with 4 CPUs. At present, two interconnection modes are mainly adopted, one mode is interconnected by using a single backboard, and the scheme needs 4 CPUs to be totally close to one side of the backboard, so that the UPI wiring distance is ensured to meet the SPEC requirement. The design mode reduces the use amount of the memory, and the full-allocation memory mode cannot be used; and the other scheme of using a back plate and a front buckle plate is adopted, and the intel purley platform limits that the memory needs to be arranged on two sides of the CPU. The size of the board card is required to be made to be large by using the UPI buckle plate for interconnection, new problems are easily introduced, the design difficulty is increased in the aspect of structure, the reliability is poor, the buckle plate can block the air duct in the aspect of heat dissipation, and the heat dissipation requirement cannot be met. The invention provides a design method of an eight-path server back plate and double-buckle plate interconnection system, wherein the back plate is interconnected with two UPI buckle plates during use, convenient board wiring and 8S system interconnection are realized, 8S and 4S switching is facilitated, cost is saved, the size of the UPI buckle plate is extremely small, reliability is stable, a radiating air duct is not influenced, and PCB wiring outgoing is facilitated.
8s,8 sockets, 8 servers, 8 CPUs.
UPI, all named Intel Ultra Path Interconnect.
Non-uniform memory access (NUMA) is a computer memory design for multiple processors that allows multiple servers to behave as a single system while retaining the ease of programming and management of small systems.
Disclosure of Invention
Aiming at the requirements and the defects of the prior art development, the invention provides a design method of an eight-path server back plate and double-buckle-plate interconnection system, wherein the back plate is interconnected with two UPI buckle plates during use, the convenient interconnection of board card wiring and an 8S system is realized, the 8S and 4S switching is convenient, the cost is saved, the UPI buckle plate is extremely small in size and stable in reliability, a heat dissipation air duct is not influenced, and the PCB wiring is convenient to be led out.
A design method of an eight-path server back plate and double-buckle plate interconnection system is characterized in that NUMA-based multi-physical-layer partitions are used, a middle back plate and two UPI buckle plates are used for interconnecting two 4S computing boards to form an 8S system, wherein the middle back plate is positioned in front of the computing boards and is interconnected with the two computing boards, UPI signals, Misc signals, time sequence signals and management signals are interacted, and the middle back plate is connected with CPUs positioned in front of the two computing boards through connectors of the middle back plate respectively, so that interconnection between CPUs in front of the two computing boards is realized; the two UPI buckle plates are respectively positioned behind the two computing boards and interact with the computing boards to form UPI signals, Misc signals and time sequence signals, and the connectors of the UPI buckle plates are respectively connected with the CPUs positioned behind the two computing boards to realize interconnection between the CPUs behind the two computing boards.
In the method, the back plate contains ID information, and the computing board detects the ID information by using a logic editing device and then judges master nodes and slave nodes on the computing board.
In the method, the time sequence switching control is realized by judging required computing nodes by using a logic editing device in a computing board.
An eight-path server backboard and double-buckle interconnection system comprises two 4S system computing boards, a middle backboard and two UPI buckles, wherein the NUMA-based multi-physical-layer partition is adopted, the two 4S system computing boards are interconnected by the middle backboard and the two UPI buckles to form an 8S system, the middle backboard is positioned in front of the computing boards and is interconnected with the two computing boards, UPI signals, Misc signals, time sequence signals and management signals are interacted, and the CPU positioned in front of the two computing boards is respectively connected through a connector of the middle backboard, so that interconnection between the front CPUs of the two computing boards is realized; the two UPI buckle plates are respectively positioned behind the two computing boards and interact with the computing boards to form UPI signals, Misc signals and time sequence signals, and the connectors of the UPI buckle plates are respectively connected with the CPUs positioned behind the two computing boards to realize interconnection between the CPUs behind the two computing boards.
The back plate in the system contains ID information, and the computing board utilizes a logic editing device to detect the ID information and then judges master nodes and slave nodes on the computing board.
In the system, a calculation board judges required calculation nodes by using a logic editing device to realize time sequence switching control.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a design method of an eight-path server back plate and double-buckle plate interconnection system, which is based on NUMA multi-physical-layer partition, wherein a middle back plate and two UPI buckle plates are used for interconnecting two 4S systems of computing plates to form an 8S system, and the front end and the rear end of the computing plates can be interconnected in 3 directions through 3 plate outgoing lines, so that the interconnection of UPI, Misc signals, time sequence signals, management interconnection signals and the like of the 8S system is realized, convenient plate routing is realized, 8S and 4S switching is facilitated, the cost is saved, the size of the UPI buckle plate is extremely small, the reliability is stable, a radiating air duct is not influenced, and the PCB routing outgoing lines are facilitated.
Drawings
FIG. 1 is a 8s system interconnection topology of the present invention;
FIG. 2 is a backplane interconnect topology of the present invention;
FIG. 3 is a topological diagram of the UPI buckle plate interconnection of the present invention.
Detailed Description
The invention provides a design method of an eight-path server back plate and double-buckle plate interconnection system, which is characterized in that based on NUMA multi-physical-layer partition, a middle back plate and two UPI buckle plates are utilized to interconnect two 4S system computing plates to form an 8S system, wherein the middle back plate is positioned in front of the computing plates and is interconnected with the two computing plates, UPI signals, Misc signals, time sequence signals and management signals are interacted, and the middle back plate is respectively connected with CPUs positioned in front of the two computing plates through connectors of the middle back plate, so that interconnection between front CPUs of the two computing plates is realized; the two UPI buckle plates are respectively positioned behind the two computing boards and interact with the computing boards to form UPI signals, Misc signals and time sequence signals, and the connectors of the UPI buckle plates are respectively connected with the CPUs positioned behind the two computing boards to realize interconnection between the CPUs behind the two computing boards.
And simultaneously provides a corresponding eight-path server backboard and double-buckle-board interconnection system.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to specific embodiments below.
By using the method of the invention and the NUMA-based multi-physical layer partition, the middle backboard is positioned in front of the computing boards and is interconnected with the two computing boards, the UPI signal, the Misc signal, the time sequence signal and the management signal are interacted, and are respectively connected with the CPUs positioned in front of the two computing boards through the connectors of the middle backboard, referring to figure 1, the middle backboard in figure 1 is connected with the CPU1 and the CPU0 of the first computing Board CPU Board 0, and is connected with the CPU5 and the CPU4 of the second computing Board CPU Board 1,
wherein the middle backboard contains ID information, the CPLD in the computing board can be used for detecting the ID information and then judging the master node and the slave node on the computing board,
the CPLD can judge the required computing nodes when the 8s system is applied, and the time sequence switching control of the computing nodes is realized;
and each UPI buckle plate comprises two 6X10 high-speed connectors, the two UPI buckle plates respectively realize the interconnection of CPUs 3-7 UPI and the interconnection of CPUs 2-6 UPI in the two computing boards, and the interaction of UPI signals, Misc signals and time sequence signals of the computing boards is realized.
When the 8S system selects the dual 4S mode, only the midplane can be used for signal interaction.
By using the method, the outgoing lines in three directions in the board card are realized by adding 2 UPI pinch plates on the middle back plate, the size of the UPI pinch plates is extremely small, the reliability is stable, the radiating air duct is not influenced, and the 8S and 4S switching of the system is facilitated. The PCB is convenient to line and lead out, the cost is saved, and the interconnection of the 8S system is very convenient.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711022364.XA CN107766282B (en) | 2017-10-27 | 2017-10-27 | A design method of an eight-way server backplane and a double-deck interconnection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711022364.XA CN107766282B (en) | 2017-10-27 | 2017-10-27 | A design method of an eight-way server backplane and a double-deck interconnection system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107766282A CN107766282A (en) | 2018-03-06 |
| CN107766282B true CN107766282B (en) | 2021-04-27 |
Family
ID=61270798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711022364.XA Active CN107766282B (en) | 2017-10-27 | 2017-10-27 | A design method of an eight-way server backplane and a double-deck interconnection system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107766282B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108762819B (en) * | 2018-06-11 | 2021-01-22 | 山东超越数控电子股份有限公司 | Method for realizing two-way server mainboard on backboard |
| US10489341B1 (en) * | 2018-06-25 | 2019-11-26 | Quanta Computer Inc. | Flexible interconnect port connection |
| CN109358710B (en) * | 2018-09-25 | 2022-02-18 | 郑州云海信息技术有限公司 | Interconnection device and interconnection method of signal boards |
| US10803008B2 (en) * | 2018-09-26 | 2020-10-13 | Quanta Computer Inc. | Flexible coupling of processor modules |
| CN113626370B (en) * | 2021-07-29 | 2023-07-14 | 苏州浪潮智能科技有限公司 | A multi-channel CPU interconnection system |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4509827B2 (en) * | 2005-03-04 | 2010-07-21 | 富士通株式会社 | Computer system using serial connect bus and method of connecting multiple CPU units by serial connect bus |
| TW200712841A (en) * | 2005-09-30 | 2007-04-01 | Tyan Computer Corp | Processor configuration architecture of multi-processor system |
| CN1979460A (en) * | 2005-11-29 | 2007-06-13 | 泰安电脑科技（上海）有限公司 | Processor configuration frame of multi-processor system |
| US7764511B2 (en) * | 2006-08-16 | 2010-07-27 | Mitac International Corp. | Multidirectional configurable architecture for multi-processor system |
| US20080114918A1 (en) * | 2006-11-09 | 2008-05-15 | Advanced Micro Devices, Inc. | Configurable computer system |
| CN103744479B (en) * | 2013-12-30 | 2017-10-24 | 杭州华为数字技术有限公司 | A kind of eight processor system and server |
| CN103901976B (en) * | 2014-04-10 | 2017-07-28 | 华为技术有限公司 | A kind of eight processor system and server |
| CN104408014A (en) * | 2014-12-23 | 2015-03-11 | 浪潮电子信息产业股份有限公司 | System and method for interconnecting processing units of calculation systems |
| CN104899179A (en) * | 2015-04-03 | 2015-09-09 | 浪潮电子信息产业股份有限公司 | Design method of multi-path server QPI buckle card based on fusion framework |
| CN105022715A (en) * | 2015-07-08 | 2015-11-04 | 浪潮(北京)电子信息产业有限公司 | Server backplane interconnection method and system |
| CN105760340B (en) * | 2016-02-03 | 2019-03-15 | 浪潮(北京)电子信息产业有限公司 | An Eight-way Server Based on Connector Via Design |
| CN105808499A (en) * | 2016-04-01 | 2016-07-27 | 浪潮电子信息产业股份有限公司 | CPU interconnection device and multichannel server CPU interconnection topological structure |
-
2017
- 2017-10-27 CN CN201711022364.XA patent/CN107766282B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107766282A (en) | 2018-03-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107766282B (en) | A design method of an eight-way server backplane and a double-deck interconnection system | |
| US9280504B2 (en) | Methods and apparatus for sharing a network interface controller | |
| Plana et al. | A GALS infrastructure for a massively parallel multiprocessor | |
| US9261897B2 (en) | Scalable, common reference-clocking architecture using a separate, single clock source for blade and rack servers | |
| US8159973B2 (en) | Ultra-scalable supercomputer based on MPU architecture | |
| CN101794268B (en) | Processing module capable of reconstructing signals based on VPX bus | |
| US8769458B2 (en) | Prototype verification system and verification method for high-end fault-tolerant computer | |
| KR20190112626A (en) | Mechanism to autonomously manage ssds in an array | |
| JP2017199368A (en) | Computer-readable storage device, system and method for reducing management port of multiple node chassis system | |
| CN106776457B (en) | A control system and method for sharing signals across boards of a server | |
| CN114661099B (en) | Main board, processor board and computing system | |
| CN117978759B (en) | Interconnection device, high-performance exchange device and large-model all-in-one machine | |
| CN107436860A (en) | A kind of 8 road server UPI interconnection topology devices | |
| CN111488308A (en) | System and method for supporting multi-processor expansion of different architectures | |
| CN116225177B (en) | Memory system, memory resource adjusting method and device, electronic equipment and medium | |
| CN104750581A (en) | Redundant interconnected memory sharing server system | |
| Sharma | Novel composable and scaleout architectures using compute express link | |
| CN107396586A (en) | A kind of UPI interconnection systems for reducing backboard stacking | |
| CN216352292U (en) | Server mainboard and server | |
| CN113434445B (en) | A management system and server for accessing DIMM by I3C | |
| CN109992060B (en) | Stacked multi-path server system and server | |
| CN117111693A (en) | A server chassis system, server chassis system design method and equipment | |
| US20070226456A1 (en) | System and method for employing multiple processors in a computer system | |
| CN107122268B (en) | NUMA-based multi-physical-layer partition processing system | |
| US9514076B2 (en) | Optimized two-socket/four-socket server architecture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |