CN107741727B - Book Automatic Sorting Control System - Google Patents

Abstract

an automatic book sorting control system comprises a controller unit, a book type information identification unit, a book transmission driving unit, a book transmission speed conversion unit, a counting pulse acquisition unit and a sorting driving unit, wherein the counting pulse acquisition unit and the sorting driving unit correspond to each other in a plurality of sorting subsections. The automatic book sorting control system adopts a regular inspection method to classify and sort books, and judges whether books enter or pass through related sorting subsections or not by using the change of the counting value; narrow interference pulses in the counting pulses can be automatically filtered, the accuracy of judging the counting value is guaranteed, and the programming of the controller unit is easy to realize.

Description

Book Automatic Sorting Control System

technical field

The invention relates to the field of automatic sorting, in particular to an automatic sorting control system for books.

Background technique

In the work of book management, library staff need to classify and put the returned scattered books on the shelves. At this time, it is usually necessary to manually classify and separate the books, which is very difficult and time-consuming. Existing book sorting equipment usually uses electronic tag identification technology (RFID). The principle is that when the book runs to a sorting port, the reader installed on the sorting port reads the information in the book to judge the book. Whether it is sorted to this sorting port, if it is not the book flowing to the next sorting port, use the same method to judge. The disadvantage of this method is that each sorting port must be installed with a reader-writer. When there are as many sorting ports in a sorting line, as many readers will be installed. The hardware cost is high, and at the same time due to multiple The communication between the reader and the central control unit will make expansion and maintenance difficult when the number is large.

Books that need to be sorted are returned by readers, and their shapes are different, and there are corners, deformations, etc. When the book passes through the photoelectric switch, it may generate jitter interference narrow pulses at the leading and trailing edges of the counting pulse. When such counting pulses are input to the PLC, or when the single-chip microcomputer directly performs counting and other processing, counting errors will occur, or mishandling will occur. operate.

Contents of the invention

In order to solve the problems existing in the existing book sorting equipment, the present invention provides a book automatic sorting control system, including a controller unit, a book category information identification unit, a book transmission drive unit, a book transmission speed conversion unit, an M There are a number of counting pulse acquisition units and M sorting inspection drive units, and there is a one-to-one correspondence between the M count pulse acquisition units and the M sorting inspection drive units. The M is an integer greater than or equal to 2.

The book category information identification unit outputs the book category information to the controller unit, and the M count pulse acquisition units output book count pulses to the controller unit respectively; the controller unit outputs transmission control information to the book transmission drive unit, and the book transmission motor is Control; the controller unit outputs M sorting drive control signals according to the book category information, respectively drives M sorting drive units to perform book sorting; the book transmission speed conversion unit converts the book transmission motor speed into a frequency control voltage, and the frequency control voltage It is sent to M counting pulse acquisition units.

The M sorting drive units are all composed of a book baffle driver and a book sorting push driver; the M sorting drive control signals are all composed of a book baffle control signal and a book sorting push cylinder control signal. The controller unit is a programmable controller, or a single-chip microcomputer, or an ARM controller. The book category information identification unit is an electronic tag reader, or a barcode scanner, or a two-dimensional code scanner.

The M counting pulse acquisition units are all composed of a counting pulse generating circuit and an interference pulse filtering circuit. In the same counting pulse acquisition unit, the output of the counting pulse generating circuit is connected to the anti-interference input pulse terminal of the corresponding interference pulse filtering circuit, and the anti-interference output pulse output by the interference pulse filtering circuit is the book counting pulse of the counting pulse generating circuit.

The interference pulse filtering circuit includes a shift register, a sample value 1 counter, a sample value 0 counter, a comparison threshold setter, a first numerical comparator, a second numerical comparator, an RS flip-flop, controlled oscillator.

The input of the shift register is an anti-jamming input pulse and a sampling clock pulse, and the output is N-bit sequence data; the shift register obtains N-bit sequence data by sampling the anti-jamming input pulse at the edge of the sampling clock pulse; the sampled value is a counting device The input is N-bit sequence data, and the output is the statistical value of 1 sampling value; the input of the sampling value 0 counting device is N-bit sequence data, and the output is the statistical value of 0 sampling value; the output of the comparison threshold setter For comparing the threshold; the input of the first numerical comparator is the statistical value of sampling value 1 and the comparison threshold, and the output is the first setting signal; the input of the second numerical comparator is the statistical value of sampling value 0 and the comparison threshold, The output is the second set signal; the input signal of the RS flip-flop is the first set signal and the second set signal, and the output is the anti-jamming output pulse; the input of the voltage-controlled oscillator is the frequency control voltage, and the output is the sampling clock pulse . The N is an integer greater than or equal to 2, and the N-bit sequence data is the latest N sampling values of the anti-jamming input pulse; the sampling value is binary data 0 or 1; the comparison threshold is greater than N/2( N divided by 2) and an integer less than or equal to N.

The function of the 1 number statistic device of the sampled value is that the 1 number statistic value of the output sampled value is the number of "1" in the input N-bit sequence data; the function of the 0 number statistic device of the sampled value is, The statistical value of the output sampling value 0 count is the number of "0" in the input N-bit sequence data.

The function of the first numerical comparator is that when the statistic value of one sampled value is greater than or equal to the comparison threshold, the first set signal output is valid, otherwise it is invalid; the function of the second numerical comparator is that when the sampling value When the statistical value of the value 0 is greater than or equal to the comparison threshold, the output second set signal is valid, otherwise it is invalid.

The first set signal is the set signal of the RS flip-flop, and the second set signal is the reset signal of the RS flip-flop; the anti-jamming output pulse is output from the non-inverting output terminal of the RS flip-flop, and the anti-jamming output pulse or from the RS flip-flop The inverting output of the output.

When the speed of the book transmission motor increases, the frequency control voltage output by the book transmission speed conversion unit controls the frequency of the sampling clock pulse output by the voltage-controlled oscillator to increase; when the speed of the book transmission motor decreases, the frequency of the output of the book transmission speed conversion unit The frequency of the sampling clock pulses output by the control voltage control voltage controlled oscillator is reduced.

The counting pulse generating circuit is a through-beam photoelectric switch.

The beneficial effects of the present invention are: only one electronic label reader, barcode scanner, two-dimensional code scanner and other book category information identifiers can complete the sorting of books at multiple sorting ports, and the sorting speed of books It can be changed; the method of regular inspection is used to classify and sort books, and the change of count value is used to judge whether there are books entering or passing through the relevant sorting branch; it can automatically filter out the narrow interference pulse in the counting pulse, filter out The width of the narrow interference pulse can change with the change of the transmission speed of sorting books, which ensures the accuracy of counting value judgment and is easy to realize the programming of the controller.

Description of drawings

Fig. 1 is a schematic example of a book sorting device;

Fig. 2 is the embodiment block diagram of book automatic sorting control system;

Fig. 3 is an embodiment of the first sorting drive unit;

Fig. 4 is the embodiment of the first counting pulse acquisition unit;

Fig. 5 is the embodiment of the first counting pulse generation circuit;

Fig. 6 is the embodiment of interference pulse filter circuit;

Fig. 7 is the shift register embodiment when N=5;

When Fig. 8 is N=5, sampling value 1 number statistic device embodiment;

When Fig. 9 is N=5, sampled value 0 number counter embodiment;

Fig. 10 compares the embodiment of threshold value setter and first numerical value comparator when N=5;

Fig. 11 is the embodiment of RS flip-flop;

Fig. 12 is the embodiment of voltage controlled oscillator;

Fig. 13 is the embodiment of the speed conversion unit of the book transmission motor;

Figure 14 is a schematic diagram of the anti-interference effect of the interference pulse filter circuit when N=5;

Fig. 15 is the automatic sorting process of the embodiment of the book automatic sorting control system.

Detailed ways

Hereinafter, the present invention will be further described by taking the embodiment in which M is equal to 3 in conjunction with the accompanying drawings.

Figure 1 is a schematic example of a book sorting device. The book sorting device in FIG. 1 includes a transmission subsection 1 , a book classification subsection 2 , a first sorting subsection 3 , a second sorting subsection 4 and a third sorting subsection 5 . The book classification branch 2 is used to collect books, identify the classification information of the collected books, and transmit the books to the first sorting branch 3 through the transmission branch 1, or the second sorting branch 4, or The third inspection division 5. The transmission section 1 is the book transmission belt and its related transmission and conveying devices.

Fig. 2 is a block diagram of an embodiment of the book automatic sorting control system, including a controller unit 10, a book category information identification unit 11, a book transmission drive unit 18 and a book transmission speed conversion unit 19; and a one-to-one corresponding first counting pulse acquisition unit 12 and the first sorting driving unit 15, the second counting pulse acquiring unit 13 and the second sorting driving unit 16, the third counting pulse acquiring unit 14 and the third sorting driving unit 17; the first counting pulse acquiring unit 12, The second counting pulse acquisition unit 13 and the third counting pulse acquisition unit 14 are respectively installed in the first, second and third sorting divisions. The book category information identification unit 11 outputs the book category information J1 to the controller unit 10, and the three counting pulse acquisition units respectively output the book counting pulses P11, P21, P31 to the controller unit 10; the controller unit 10 outputs the transmission control information K0 to the book The transmission drive unit 18 controls the book transmission motor in the book transmission drive unit 18; the controller unit 10 outputs three sorting drive control signals K1, K2, and K3 according to the book category information J1, and drives the three sorting drive units respectively Carry out book sorting; the book transmission speed conversion unit 19 converts the book transmission motor speed n into the frequency control voltage UK, and the frequency control voltage UK is sent to the three counting pulse acquisition units.

Each sorting branch includes a book baffle driven by the sorting drive unit and a book sorting push cylinder, as well as a collection vehicle or collection basket that collects books in this branch. Figure 3 shows the layout of the first sorting branch. Embodiment of the first sorting drive unit. In Fig. 3, YA1 is the electromagnet coil driving the book baffle, K11 is the control signal of the book baffle; YV1 is the solenoid valve driving the book sorting and pushing cylinder, and K12 is the control signal of the book sorting and pushing cylinder; K11 and K12 are jointly composed The sorting drive control signal K1 of the first sorting drive unit. In FIG. 3 , the output form of K11 and K12 from the controller unit 10 is an open-collector output of an NPN triode. The output form of K11 and K12 from the controller unit 10 may also be one end of the relay output, and at this time, the other end of the relay output is grounded. The controller unit can also use other output forms to perform the above-mentioned driving. The circuit and structure of the second sorting driving unit of the second sorting subsection and the third sorting driving unit of the third sorting subsection are the same as the first sorting driving unit of the first sorting subsection.

In the embodiment, the book category information identification unit 11 adopts an RFID electronic tag reader. The book category information identification unit 11 is installed in the book classification branch 2, when the book transmission passes through the book category information identification unit 11, the RFID electronic tag reader/writer reads the relevant book category information recorded in the RFID electronic tag on the book, And use the RS485 communication interface to send the acquired book category information J1 of the relevant books to the controller unit 10 . When the book category information identification unit adopts the RFID electronic tag reader-writer, it is more convenient to read the relevant book category information of the book. When the book passes through the RFID electronic tag reader-writer, there are not many requirements for the placement state of the book. The book category information identification unit can also use a barcode scanner or a two-dimensional code scanner. , there are requirements for the position where the barcode or two-dimensional code is pasted on the book, and the placement state of the book when it passes through the barcode scanner or two-dimensional code scanner.

The running speed of the book conveyor belt varies between 0.1m/s and 0.5m/s. In the embodiment, the book transmission drive unit 18 uses a frequency converter to drive the book transmission motor to adjust the speed to control the operating speed of the book transmission belt. The controller unit 10 uses the RS485 communication interface to send the transmission control information K0 to the book transmission drive unit 18, and the transmission control Information K0 includes information for controlling the start, stop and speed regulation of the book transport motor. The book transmission drive unit 18 can also control the frequency converter by means of terminal control.

Fig. 4 is an embodiment of the first counting pulse acquisition unit. Among Fig. 4, Pin is the input end of the anti-interference input pulse of the first interference pulse filter circuit 32, Pout is the output end of the anti-interference output pulse of the first interference pulse filter circuit 32, and the count output by the first count pulse generation circuit 31 The initial pulse P10 is connected to Pin of the first disturbance pulse filter circuit 32 , and after being filtered by the first disturbance pulse filter circuit 32 , the book counting pulse P11 is output from Pout of the first disturbance pulse filter circuit 32 .

Figure 5 is an embodiment of the first counting pulse generating circuit, which adopts the Omron through-beam photoelectric switch, the model of the light projector 201 is E3ZG-T61-S; the model of the light receiver 202 is E3ZG-T61-S, and its output terminal OUT1 adopts an NPN transistor Open-collector output, the resistor R201 is its collector resistance, and the counting initial pulse P10 of the first counting pulse generating circuit 31 is output from the OUT1 terminal of the light receiver 202 . In Figure 5, +VCC is the power supply of the photoelectric switch, and GND is the common ground. The first counting pulse generation circuit can also use other through-beam photoelectric switches and reflective photoelectric switches, and the pulse output form of the photoelectric switch can also be other output types. The first count pulse generating circuit is installed at the first sorting subsection. The circuit and structure of the second counting pulse generating circuit and the third counting pulse generating circuit are the same as the first counting pulse generating circuit, and they are respectively installed in the places where the second sorting branch and the third sorting branch are located.

In the embodiment, both the second count pulse acquisition unit 13 and the third count pulse acquisition unit 14 have the same interference pulse filter circuit as the first interference pulse filter circuit 32 in the first count pulse acquisition unit 12 . Figure 6 shows an embodiment of the interference pulse filtering circuit. In Fig. 6, the shift register 101 includes a serial input end, an N-bit parallel output end, and a sampling clock pulse input end, the anti-interference input pulse Pin is input from the serial input end of the shift register 101, and the sampling clock pulse CLK is input from the shift register 101. The sampling clock pulse input terminal of the register 101 is input, and the N-bit parallel output terminal of the shift register 101 outputs N-bit sequence data X1; the input of the sampled value 1 number counter 102 is the N-bit sequence data X1, and the output is 1 sampled value Number statistical value Y1; The input of sampling value 0 number counter 103 is N-bit sequence data X2, and the output is sampling value 0 Number statistical value Y2; The output of comparison threshold value setter 104 is comparison threshold Y0; The first numerical value comparison The input of the device 105 is the statistical value Y1 of sampled value 1 and the comparison threshold Y0, and the output is the first set signal SE1; the input of the second numerical comparator 106 is the statistical value Y2 of the sampled value 0 and the comparison threshold Y0, and the output It is the second setting signal RE1; the input of the RS flip-flop 107 is the first setting signal SE1 and the second setting signal RE1, and the output is the anti-interference output pulse Pout of the interference pulse filter circuit; the input of the voltage-controlled oscillator 108 is The frequency control voltage UK is output as the sampling clock pulse CPK. In the embodiment of the interference pulse filtering circuit, N=5.

FIG. 7 is an embodiment of a shift register when N=5. In Figure 7, five D flip-flops FF1, FF2, FF3, FF4, and FF5 form a 5-bit serial shift register, and the input terminal D of FF1 is the serial input terminal of the shift register, which is connected to the anti-interference input pulse Pin; After the clock input terminals CLK of FF1, FF2, FF3, FF4, and FF5 are connected in parallel, they form the shift pulse input terminal of the shift register, that is, the sampling clock pulse input terminal of the shift register, and are connected to the sampling clock pulse CPK; FF1, FF2 , FF3, FF4, and FF5 output Q are respectively x11, x12, x13, x14, x15. In FIG. 7, the N-bit sequence data X1 is composed of x11, x12, x13, x14, x15. The N-bit sequence data X1 is the latest N sampling values of the anti-interference input pulse Pin of the shift register at the rising edge of the sampling clock pulse CPK.

When N is other values, the number of D flip-flops in FIG. 7 can be increased or decreased to realize the function of an N-bit shift register. The D flip-flops in FIG. 7 can be replaced by other flip-flops, for example, N JK flip-flops are used to realize the function of an N-bit shift register. The N-bit shift register can also be realized by single or multiple dedicated multi-bit shift registers. For example, a 74HC164 or a 74HC595 can realize the function of no more than 8-bit shift register. Multi-chip 74HC164 or multi-chip 74HC595 can realize the function of shift register with more than 8 bits.

Fig. 8 is an embodiment of a statistic device for one sampling value when N=5. The function of the 1-sample count counter is that the output 1-sample count statistic value Y1 is the quantity value of the number of "1"s in the input N-bit sequence data X1. In Fig. 8, 1 count counter of sampled value is made up of 1 full adder FA1, FA2, FA3, and 1 full adder in Fig. 8 all includes 1 addend input end A, 1 addend input end B. Carry input terminal Ci, 1-bit result output terminal S, and 1-bit carry output terminal Co. The 1-bit full adder FA1 realizes the statistics of the number of "1" in x11, x12, and x13, and n2, n1 are the 2-bit binary statistics output of FA1. Two 1-bit full adders FA2 and FA3 form a 2-bit binary adder. FA2 and FA3 use n2 and n1 as an addend, x14 as another addend, and x15 as a low-order carry to obtain a 3-bit binary Output y13, y12, y11, y13, y12, y11 is the statistical value Y1 of sampling value 1; when x14 is used as another addend, the high bit of another addend input from terminal B of FA3 is 0. When connected to the input terminal of the sampling value 1 counter, the connection positions of x11, x12, x13, x14, and x15 can be interchanged arbitrarily. The N-bit sequence data X1 is N-bit binary data, and the number counter of sampled value 1 is actually a statistical adder for counting the number of "1" in the N-bit binary data.

The sampling value 0 counting device is composed of a statistical adder and an N-bit inverter having the same structure and composition as the sampling value 1 counting device; the input of the N-bit inverter is N-bit sequence data X1, and the output is N Bit reverse sequence data. FIG. 9 is an embodiment of a statistic device for sampling value 0 when N=5. The function of the sample value 0 count counter is that the output sample value 0 count value Y2 is the quantity value of the number of "0"s in the input N-bit sequence data X1. In Fig. 9, the statistic device for sampling value 0 includes a 5-bit inverter composed of 5 inverters FN1, FN2, FN3, FN4, FN5 and three 1-bit full adders FA4, FA5, FA6. The function of the adder and the 5-bit inverter is to invert x11, x12, x13, x14, and x15 of the 5-bit sequence data X1 one by one, and convert the statistics of the number of "0" into the number of "1". number for statistics. The 1-bit full adder in FIG. 9 also includes a 1-bit addend input terminal A, a 1-bit addend input terminal B, a carry input terminal Ci, a 1-bit result output terminal S, and a 1-bit carry output terminal Co. The 1-bit full adder FA4 realizes the statistics of the number of "0" in x11, x12, and x13, and m2 and m1 are the 2-bit binary statistics output of FA4. Two 1-bit full adders FA5 and FA6 form a 2-bit binary adder. FA5 and FA6 use m2 and m1 as an addend, and x14 as another addend. As a low-order carry, it is added to obtain 3-bit binary output y23, y22, y21, y23, y22, y21 are the statistical value Y2 of the sampling value 0; As another addend, the high bit of another addend input from the B terminal of FA6 is 0. When connected to the input terminal of the sampling value 0 counter, the connection positions of x11, x12, x13, x14, and x15 can be interchanged arbitrarily.

Other circuit forms can also be used to realize the 1-bit adder function in the sampled value 1 count counter and the sampled value 0 count counter function, for example, use the look-ahead carry integrated 4-bit adder 74HC283, or 4 Bit binary parallel carry full adder CD4008, or 3-bit serial adder CD4032, or a combinational logic circuit composed of gate circuits replaces all or part of the 1-bit adder in Fig. 8 and Fig. 9 .

Figure 10 is an embodiment of the comparison threshold setter and the first numerical comparator when N=5. In Figure 10, the comparison threshold setter is made up of 3 binary dial switches SW1, +VCC is the power supply, and GND is the common Specifically, its 3-bit binary output y03, y02, y01 constitutes the comparison threshold Y0. Since N=5, Y0 can only take values among 3, 4, and 5. In this embodiment, the comparison threshold Y0 takes a value of 4, that is, the values of y03, y02, and y01 are 1, 0, and 0. The comparison threshold setter can be composed of multi-digit binary dial switches, or BCD dial switches, or multiple ordinary switches plus pull-up resistors, or multiple pull-up resistors and circuit short contacts for controlling 0 and 1 outputs. And other circuits capable of outputting multi-bit binary set values.

In Fig. 10, the first numerical comparator is composed of a four-bit binary numerical comparator FC1 and an OR gate FO1, and the model of FC1 is 74HC85. The 3-bit binary output y13, y12, y11 of the statistical value Y1 of the sampling value 1 is respectively connected to the A2, A1, A0 input terminals of FC1, and the 3-bit binary output y03, y02, y01 of the comparison threshold Y0 are respectively connected to the B2 of FC1 , B1, B0 input terminals, input terminals A3, B3 are all connected to 0. The input terminals A>B IN and A<B IN of FC1 are both connected to 0, and the input terminal A=B IN is connected to 1. The output terminals A>BOUT and A=B OUT of FC1 are respectively connected to the input terminals of the OR gate FO1, and the output terminal of the OR gate FO1 is the first set signal SE1. The function realized by the first numerical comparator in FIG. 10 is that when the statistical value Y1 of the sampling value 1 is greater than or equal to the comparison threshold Y0, the output SE1 is high level, otherwise SE1 is low level. In Figure 10, SE1 is active at high level; if the OR gate FO1 is changed to a NOR gate, SE1 is active at low level.

When the value of N is large, you can choose two or more pieces of 74HC85 to form a multi-bit binary value comparator to realize the function of the first value comparator; you can also use one or more pieces of four-bit binary value comparator CD4063 to realize the first value The function of the comparator, or use other combinational logic circuits to realize the function of the first numerical comparator. The implementation principle of the second numerical comparator is the same as that of the first numerical comparator, and its function is that when the statistical value Y2 of the sampling value 0 is greater than or equal to the comparison threshold Y0, the output RE1 is high level, otherwise RE1 is low level; RE1 is active high. RE1 can also be selected to be active low.

Figure 11 is an embodiment of the RS flip-flop. In FIG. 11 , the NOR gates FO2 and FO3 form an RS flip-flop, and both the first set signal SE1 and the second set signal RE1 are active high. When SE1 is valid and RE1 is invalid, set the anti-jamming output pulse Pout output from the non-inverting output terminal FO3 to 1; when SE1 is invalid and RE1 is valid, set the anti-jamming output pulse Pout to 0; when both SE1 and RE1 are invalid, The state of the anti-jamming output pulse Pout remains unchanged. The RS flip-flop can also adopt other forms of RS flip-flops.

In FIG. 11 , the anti-jamming output pulse Pout and the anti-jamming input pulse Pin are in-phase. If the anti-jamming output pulse Pout is changed to be output from the inverting output terminal FO2 of the NOR gate, the function is changed to, when SE1 is valid and RE1 is invalid, the anti-jamming output pulse Pout is set to 0; when SE1 is invalid and RE1 is valid, Set the anti-jamming output pulse Pout to 1; when both SE1 and RE1 are invalid, the state of the anti-jamming output pulse Pout remains unchanged; at this time, the relationship between the anti-jamming output pulse Pout and the anti-jamming input pulse Pin is inverse.

Fig. 12 is an embodiment of a voltage controlled oscillator. In Figure 12, CMOS NOT gates FN6 and FN7, resistors R91, resistors R92, capacitor C91, and capacitor C92 form a voltage-controlled multivibrator; the NOT gate FN8 plays the role of output pulse shaping, and the sampling clock pulse CPK is output from the output terminal of FN8. The basic frequency of CPK can be changed by the value of resistor R91, resistor R92, capacitor C91, and capacitor C92. At the same time, the oscillation frequency of CPK will be adjusted adaptively according to the input frequency control voltage UK. When UK increases, it passes through the resistor R91 and resistor R92 charge and discharge capacitor C91 and capacitor C92 faster, and CPK frequency increases; when UK decreases, the resistor R91 and resistor R92 charge and discharge capacitor C91 and capacitor C92 slower, and CPK frequency decreases . The voltage-controlled oscillator can also be realized by using other types of multivibrator voltage-controlled oscillators.

Fig. 13 is an embodiment of the speed conversion unit of the book transmission motor. The speed conversion unit of the book transmission motor converts the speed n of the book transmission motor into the frequency control voltage UK. In Fig. 13, F71 is a transmission speed sensor, and F71 converts the speed n of the book transmission motor into a voltage Un for output. The operational amplifier F72 and the resistors R76, R77, R78 and R79 form a zero value adjustment circuit, and the frequency control voltage UK is output from the output terminal of the operational amplifier F72. One of the functions of the zero value adjustment circuit is to adjust the frequency control voltage UK corresponding to the minimum speed (usually 0) of the book transmission motor speed n to a non-zero value by changing the input zero value adjustment voltage VREF. 12. When the circuit controls the oscillation frequency, the minimum voltage value of UK must be greater than the input threshold voltage of the NOT gates FN6 and FN7; the second is to improve the driving ability of the frequency control voltage UK. The frequency control voltage UK range corresponding to the speed n range of the book transmission motor is adjusted by adjusting the parameters of the transmission speed sensor F71, the zero value adjustment circuit parameters and the zero value adjustment voltage VREF. In the embodiment of Figure 13, when the book transmission motor speed n increases, the output frequency control voltage UK increases, and the output CPK frequency in Figure 12 is controlled to increase; when the book transmission motor speed n decreases, the output frequency control voltage UK Decrease, control the output CPK frequency in Figure 12 to decrease. The speed n of the book transmission motor is proportional to the running speed of the book transmission belt. The transmission speed sensor can choose a DC speed measuring motor, or choose other speed detection methods that can output DC voltage, for example, using the F-V method, using the Hall element to convert the speed into a frequency signal proportional to the speed, and then convert the pulse frequency into DC voltage output.

In the above embodiment of the interference pulse filtering circuit with N=5, the comparison threshold Y0 takes a value of 4. When the statistical value Y1 of the sampling value 1 is greater than or equal to 4, the output SE1 is high level, and the anti-interference output pulse Pout is set to 1. The essence is that when the number of "1" in the 5-bit sequence data X1 is greater than or equal to 4, the output SE1 is high level, and the anti-interference output pulse Pout is set to 1; when the sampling value is 0 and the statistical value Y2 is greater than or equal to 4, the output RE1 is high level, and the anti-interference output pulse Pout is set to 0 , its essence is that when the number of "0" in the 5-bit sequence data X1 is greater than or equal to 4, the output RE1 is high level, and the anti-jamming output pulse Pout is set to 0. Since the comparison threshold Y0 is an integer greater than N/2 and less than or equal to N, the first set signal SE1 and the second set signal RE1 cannot be valid at the same time, therefore, the output of the RS flip-flop will not have an uncertain logic state .

FIG. 14 is a schematic diagram of the anti-interference effect of the interference pulse filter circuit when N=5. Fig. 14 shows the sampling results of 15 sampling clock pulses CPK anti-jamming input pulse Pin and the obtained anti-jamming output pulse Pout. Assume that the sampling values of the five sequence data X1 obtained before the sampling point 1 of CPK in Fig. 14 are all 0, and the anti-jamming output pulse Pout is 0. In Figure 14, the anti-jamming input pulse Pin has a positive pulse interference before sampling point 3 of CPK and after sampling point 4, resulting in X1 sampling at sampling point 3 and sampling point 4 to obtain the interference sampling value 1; the anti-jamming input pulse Pin is at Positive narrow pulse interference appears between sampling point 5 and sampling point 6 of CPK, but the positive narrow pulse width is less than the sampling period and is between two sampling points, which does not affect the sampling result of sequence data X1, that is, the sampling process automatically filters Except for this positive narrow pulse interference. The anti-interference input pulse Pin starts to change from 0 to 1 after sampling point 8 of CPK, and there are 2 edge jitters in the process of changing from 0 to 1, and the second positive narrow pulse jitter interference is automatically filtered out by the sampling process, and the sampling point 9. The values of sampling point 10 are 1 and 0 respectively. In FIG. 14 , the sampled values obtained by the sequence data X1 at the sampling point 1 to the sampling point 15 of the clock pulse CPK are 0 0 1 1 0 0 0 0 1 0 1 1 1 1 1. Set the value of Y0 to 4, and observe the situation of several sampling points. At sampling point 3, Y1 is equal to 1, Y2 is equal to 4, RE1 is valid, and Pout is 0; at sampling point 4, Y1 is equal to 2, Y2 is equal to 3, SE1, RE1 is invalid, and Pout remains at 0; at sampling point 5, Y1 is equal to 2, Y2 is equal to 3, SE1 and RE1 are both invalid, and Pout remains at 0; at sampling point 6, Y1 is equal to 2, Y2 is equal to 3, and SE1 and RE1 are both Invalid, Pout remains at 0; at sampling point 7, Y1 is equal to 2, Y2 is equal to 3, SE1 and RE1 are invalid, and Pout remains at 0; at sampling point 8, Y1 is equal to 1, Y2 is equal to 4, RE1 is valid, and Pout is 0 ; At sampling point 12, Y1 is equal to 3, Y2 is equal to 2, SE1 and RE1 are invalid, and Pout remains 0; at sampling point 13, Y1 is equal to 4, Y2 is equal to 1, SE1 is valid, and Pout is 1; obviously, in continuous Among the 5 sequence data X1 values, until the sampling point 13 in Figure 14, the condition that the number of "1" in the 5-bit sequence data X1 is greater than or equal to 4 is satisfied, the first set signal SE1 is valid, and the anti-jamming output pulse Pout is set by 0 becomes 1. From sampling point 14 to sampling point 15, the condition that the number of “1” in X1 is greater than or equal to 4 is satisfied, and the first set signal SE1 remains valid.

Figure 14 shows the anti-positive pulse interference effect of the interference pulse filter circuit when the anti-interference input pulse Pin is 0, and the conditions and process for the anti-interference input pulse Pin to change from 0 to 1. Due to the symmetry of the circuit, the anti-negative pulse interference effect of the interference pulse filter circuit when the anti-interference input pulse Pin is 1, and the conditions and process of the anti-interference input pulse Pin changing from 1 to 0 are the same as the anti-interference input pulse Pin is 0 The anti-positive pulse interference effect, and the conditions for the anti-interference input pulse Pin to change from 0 to 1 are the same as the process. Assuming that the five sampling values of the CPK anti-jamming input pulse Pin before the sampling point 31 of the sampling clock pulse CPK are all 1, the anti-jamming output pulse Pout is 1; the N-bit sequence data X1 obtained by sampling from the sampling point 31 to the sampling point 45, The statistical value Y1 of sampling value 1 and the anti-jamming output pulse Pout are shown in Table 1, and the statistical value Y2 of sampling value 0 is equal to 5-Y1 (5 minus Y1).

Table 1 N-bit sequence data X1 of sampling points 31-45, statistical value Y1 of sampling value 1 and anti-interference output pulse Pout

Observe the sampling points in Table 1. At sampling points 31-32, Y1 is greater than or equal to Y0, SE1 is valid, RE1 is invalid, and the anti-interference output pulse Pout is set to 1; at sampling points 33-41, Y1 is less than Y0 and Y2 is less than Y0, SE1, and RE1 are all invalid, and the anti-jamming output pulse Pout remains 1; at sampling points 42-45, Y2 is greater than or equal to Y0, RE1 is valid, SE1 is invalid, and the anti-jamming output pulse Pout is set to 0.

Taking the anti-jamming output pulse Pout and the anti-jamming input pulse Pin as an example as an example for further description. The working process of the interference pulse filter circuit is that when Y1≥Y0, that is, when the number of "1" in the N-bit sequence data X1 is greater than or equal to Y0, the anti-interference output pulse Pout is set to 1; when Y2≥Y0, that is, the N-bit When the number of "0" in the sequence data X1 is greater than or equal to Y0, the anti-jamming output pulse Pout is set to 0. Since the comparison threshold Y0 is an integer greater than N/2 and less than or equal to N, the number of "1"s in the N-bit sequence data X1 is greater than or equal to Y0 and the number of "0"s in the N-bit sequence data X1 is greater than or equal to Y0 The 2 conditions will not be met at the same time. When the anti-jamming input pulse Pin and the anti-jamming output pulse Pout are both 0, in consecutive N times of sampling, as long as the sampling result formed by single or multiple positive pulse interference does not cause the number of "1" in the N-bit sequence data X1 to be greater than Equal to Y0, the anti-jamming output pulse Pout will not become 1; when the anti-jamming input pulse Pin and anti-jamming output pulse Pout are both 1, in N consecutive sampling, as long as the sampling result formed by single or multiple negative pulse interference If the number of "0"s in the N-bit sequence data X1 is not greater than or equal to Y0, the anti-jamming output pulse Pout will not become 0. When both Pin and Pout are at low level, as long as the positive pulse appearing in the Pin makes Y0 out of the N continuous Pin sampling values be 1, the positive pulse corresponding to the positive pulse in the Pin can be output from Pout; When both Pin and Pout are at high level, as long as the negative pulse that appears in the Pin makes Y0 out of the consecutive N pin sampling values be 0, the negative pulse corresponding to the negative pulse in the Pin can be output from Pout . When the anti-jamming input pulse Pin has changed from 0 to 1, or from 1 to 0, the anti-jamming output pulse Pout needs to have the number of "1" in the N-bit sequence data X1 greater than or equal to Y0, or an N-bit sequence After the number of "0" in the data X1 is greater than or equal to the Y0 condition, the anti-jamming output pulse Pout is changed from 0 to 1, or the anti-jamming output pulse Pout is changed from 1 to 0, and there is a delay of several sampling pulse periods. When the value of Y0 becomes larger within the value range, the interference pulse filter circuit changes the anti-interference output pulse Pout from 0 to 1, and the conditions for changing from 1 to 0 are more stringent, and the anti-interference effect is better, but the anti-interference output pulse Pout The greater the delay time relative to the anti-interference input pulse Pin; when the value of Y0 becomes smaller within the value range, the interference pulse filtering circuit will change the anti-interference output pulse Pout from 0 to 1, and the conditions from 1 to 0 will be widened, The anti-jamming effect becomes smaller, but the delay time of the anti-jamming output pulse Pout relative to the anti-jamming input pulse Pin becomes smaller. When the value of N becomes larger, the interference pulse filter circuit will change the anti-interference output pulse Pout from 0 to 1, and the condition from 1 to 0 will become stricter, and the anti-interference effect will become better, but the anti-interference output pulse Pout is relatively weaker than the anti-interference The delay time of the input pulse Pin becomes longer; when the value of N becomes smaller, the interference pulse filter circuit will change the anti-interference output pulse Pout from 0 to 1, and the condition from 1 to 0 will be wider, and the anti-interference effect will become smaller, but the anti-interference The delay time of the disturbance output pulse Pout relative to the anti-disturbance input pulse Pin becomes smaller.

The period of the sampling clock pulse shall be determined according to the pulse width of the anti-interference input pulse Pin, the change speed and the width of the interference pulse. Due to the different shapes of the returned books, and there are bending angles and deformations, when passing through the photoelectric switch, a narrow pulse of jitter interference may be generated at the leading edge and trailing edge of the counting pulse; the running speed of the book conveyor belt is between 0.2m/s and 1.2 The m/s varies, and the effective counting pulse width formed is from 10ms to 100ms, while the narrow interference pulse generated is less than one-tenth of the corresponding effective counting pulse width. Therefore, the period of the sampling clock pulse selected by the voltage-controlled oscillator varies between 1 ms and 10 ms, and N takes a value in the range of 3 to 7.

There are interference pulse filtering circuits in the M counting pulse acquisition units, and all the shift registers in the interference pulse filtering circuits, the counting device for sampling value 1, the counting device for sampling value 0, the comparison threshold value setter, and the first numerical value All or some of the functions of the comparator, the second numerical comparator, the RS flip-flop, and the voltage-controlled oscillator can be realized by PAL, GAL, CPLD, FPGA, or other programmable logic devices and logic units.

FIG. 15 is the automatic sorting process of the embodiment of the automatic book sorting control system, which is realized by the program in the controller unit 10 . The controller unit 10 of the embodiment is a programmable controller. The steps of embodiment book automatic sorting method are:

Step 1, initialization; including the initialization of the relevant functional parts of the controller unit 10, sending the transmission control information K0 to the book transmission drive unit 18, controlling the operation of the book transmission belt at a specified speed, etc.;

Step 2, read and according to the information sent by the book category information identification unit 11, judge whether the book classification branch 2 has passed the book; if there is no book passed, go to step 4; if there is a book passed, go to step 3;

Step 3. Record the book category information of the currently passed book, and record the transmission timing start time of the book;

Step 4. Determine whether the first sorting branch has counted books; if the first sorting branch has not counted books, go to step 7; if counting books, go to step 5;

Step 5. According to the transmission timing start time of all books recorded in the book classification division 2 and the relevant book category information, it is judged whether the books currently in the first sorting division belong to the first sorting division; For books in the sorting division, go to step 7; for books in the first sorting division, go to step 6;

Step 6. First, make the book baffle control signal of the first sorting branch effective, and raise the book baffle of the first sorting branch; after a short time delay, make the book sorting of the first sorting branch push When the cylinder control signal is valid, the book is pushed to the collection vehicle or collection basket of the first sorting branch; then the book baffle control signal and the book sorting push cylinder control signal of the first sorting branch are restored to be invalid;

Step 7, judging whether the second sorting branch has counted books; if the second sorting branch has not counted books, go to step 10; if counting books, go to step 8;

Step 8, according to the transmission timing start time of all books recorded in the book classification division 2 and the relevant book category information, judge whether the books currently in the second sorting division belong to the second sorting division; For books in the sorting division, go to step 10; for books in the second sorting division, go to step 9;

Step 9. First, make the book baffle control signal of the second sorting branch effective, and raise the book baffle of the second sorting branch; after a short time delay, make the book sorting of the second sorting branch push The cylinder control signal is valid, and the book is pushed to the collection vehicle or collection basket of the second sorting branch; then the book baffle control signal and the book sorting push cylinder control signal of the second sorting branch are restored to be invalid;

Step 10, judging whether the third sorting branch has counted books; if the third sorting branch has not counted books, go to step 13; if counting books, go to step 11;

Step 11, according to the transmission timing start time of all books recorded in the book classification division 2 and related book category information, determine whether the books currently in the third sorting division belong to the third sorting division; not the third For books in the sorting division, go to step 13; for books in the third sorting division, go to step 12;

Step 12. First, make the book baffle control signal of the third sorting branch effective, and raise the book baffle of the third sorting branch; after a short time delay, make the book sorting of the third sorting branch push When the cylinder control signal is valid, the book is pushed to the collection vehicle or collection basket of the third sorting branch; then the book baffle control signal and the book sorting pushing cylinder control signal of the third sorting branch are restored to be invalid;

Step 13. After a fixed time delay, go to step 2.

When the book automatic sorting control system has M sorting divisions, the steps of its book automatic sorting method are:

Step 1, initialization; including the initialization of the relevant functional parts of the controller unit, sending transmission control information to the book transmission drive unit, controlling the operation of the book transmission belt at a specified speed, etc.;

Step 2. Read and judge whether there are books in the book classification branch according to the information sent by the book category information identification unit; if there are no books, go to step 4; if there are books, go to step 3;

Step 3: Record the book category information of the currently passed book, and record the start time of the book's transmission timing;

Step 4. Determine whether the first sorting branch has counted books; if the first sorting branch has not counted books, go to step 7; if counting books, go to step 5;

Step 5. According to the start time of transmission timing of all books recorded in the book classification branch and the relevant book category information, determine whether the books currently in the first sorting branch belong to the first sorting branch; If the book is checked by the branch, go to step seven; if it is the book of the first sorting branch, go to step six;

Step 6. First, make the book baffle control signal of the first sorting branch effective, and raise the book baffle of the first sorting branch; after a short time delay, make the book sorting of the first sorting branch push When the cylinder control signal is valid, the book is pushed to the collection vehicle or collection basket of the first sorting branch; then the book baffle control signal and the book sorting push cylinder control signal of the first sorting branch are restored to be invalid;

Step 7. According to the method described in step 4 to step 6, whether the books have been counted in the second sorting branch to the Mth sorting branch in turn, and whether they are books in the corresponding sorting branch are judged and processed ;

Step 8: After a fixed time delay, go to step 2.

In addition to the programmable controller selected in the embodiment, the controller unit can also be a single-chip microcomputer or an ARM controller. According to the relevant control requirements and control methods of the book automatic sorting control system, choose a programmable logic controller, or a single-chip microcomputer, or an ARM controller.

The counting of books by the above-mentioned relevant sorting divisions is only used to judge whether there are books entering or passing through the relevant sorting divisions, not the statistical value of the number of books in the relevant divisions. The automatic sorting control system adopts the method of regular inspection to classify and sort books, and uses the change of the count value to judge whether there are books entering or passing through the relevant sorting branch, the real-time response requirements of the controller are reduced, and the difficulty of programming is reduced; It can automatically filter out the narrow interference pulses in the counting pulses, which ensures the accuracy of the counting value judgment, and is easy to realize the programming of controllers such as PLC. By counting the number of times that the book sorting push cylinder control signal is valid from each sorting branch, the count value of the books entering the exit of the sorting branch can be obtained.

In the above-mentioned step 13 or in the step eight, the fixed time of timing delay, its numerical value requires less than the pulse counting place (that is, the place where the counting pulse generation circuit is installed) of the book passing through the sorting branch on the book conveyor belt to the same sorting point. The transmission time at the book baffle of the department is related to the distance from the pulse counting place (that is, where the counting pulse generation circuit is installed) to the book baffle of the same sorting branch, and the current running speed of the book conveyor belt. The current running speed of the book transport belt is set and controlled by the controller in the above-mentioned step 1, or step 1.

In the above-mentioned step 5, step 8, step 11, and step 5, including the method of step 5 implied in step 7, each sorting branch counts the starting time of transmission timing and related books according to the recorded transmission time of all books Category information, to judge whether the book currently in the sorting branch belongs to the sorting branch, the judgment method is based on the actual transmission time required for the book from the book classification branch to the sorting branch on the book conveyor belt , to calculate the current starting time of transmission timing of books in the sorting branch; compare the calculated starting time of transmission timing with the recorded starting time of transmission timing of all books currently on the book transmission belt, according to the estimated time and the recorded It is judged whether the book currently in the sorting branch belongs to the sorting branch according to the book category information of the book matching the time. The estimated time coincides with the recorded time, which means that the error between the estimated transmission timing start time and the recorded transmission timing start time of one of the books currently on the book transmission belt is within the allowable range. The allowable range is determined according to the conditions of book transmission and detection.

The estimated start time of transmission timing for books is related to the actual transmission time of books from the book classification branch to the current sorting branch; the current time minus the actual transmission time is the estimated transmission timing start time. The actual transmission time of the book from the book classification branch to the current sorting branch is the same as the time when the book passes through the book category information identification unit in the book classification branch to the pulse counting place of the current sorting branch (that is, the counting pulse generation circuit is installed The actual transmission time of different sorting branches is calculated by the controller unit according to the relevant distance and the current running speed of the book conveyor.

In the above-mentioned step 6, step 9, step 12, and step 6, including the method of step 6 implied in step 7, the specific delay time value of the short-time delay is the book baffle of the sorting branch After being lifted, the time value for the book to reach the book baffle, this value needs to be determined according to the actual situation on site.

Due to incorrect information identification, transmission obstruction or other reasons, when the books are not sorted out in each sorting branch, they will automatically enter the collection cart or collection basket at the end of the book transmission belt, and the staff will handle them accordingly.

Except for the technical features described in the description, all are conventional techniques mastered by those skilled in the art. For example, select the controller of the controller unit, design the relevant peripheral control circuit and program to realize its function; design the corresponding drive circuit of the sorting drive unit; select the appropriate RFID electronic tag reader, or barcode scanner, or It is a two-dimensional code scanner, which meets the requirements for reading the relevant book category information; selects the appropriate frequency converter and book transmission motor according to the needs, and designs the relevant drive circuit to meet the requirements of the relevant book transmission drive and speed regulation; and according to the actual system The book automatic sorting control system may need to add a power supply unit, communication unit, and man-machine interface unit. How to select or design a power supply unit according to the demand to meet the power supply requirements of the book automatic sorting control system, and how to select or design the communication unit according to the demand. Unit, man-machine interface unit, connecting communication unit, man-machine interface unit and controller unit to realize corresponding functions; etc., are conventional technologies mastered by those skilled in the art.

Claims (6)

1. the automatic book sorting control system is characterized in that:

the book sorting and counting device comprises a controller unit, a book type information identification unit, a book transmission driving unit, a book transmission speed conversion unit, M counting pulse acquisition units and M sorting driving units; m is an integer greater than or equal to 2;

The book type information identification unit outputs book type information to the controller unit, and the M counting pulse acquisition units respectively output book counting pulses to the controller unit;

The controller unit outputs transmission control information to the book transmission driving unit to control the book transmission motor;

The controller unit outputs M sorting driving control signals according to the book category information and respectively drives M sorting driving units to sort books;

the book transmission speed conversion unit converts the speed of the book transmission motor into frequency control voltage, and the frequency control voltage is sent to the M counting pulse acquisition units;

The M counting pulse acquisition units are respectively composed of a counting pulse generating circuit and an interference pulse filtering circuit;

In the same counting pulse acquisition unit, the output of a counting pulse generation circuit is connected to an anti-interference input pulse end of a corresponding interference pulse filtering circuit, and an anti-interference output pulse output by the interference pulse filtering circuit is a book counting pulse;

The interference pulse filtering circuit comprises a shift register, a sampling value 1 number counter, a sampling value 0 number counter, a comparison threshold value setter, a first numerical comparator, a second numerical comparator, an RS trigger and a voltage-controlled oscillator;

The input of the shift register is an anti-interference input pulse and a sampling clock pulse, and the output is N-bit sequence data; the input of the sampling value 1 number statistic device is N-bit sequence data, and the output is the sampling value 1 number statistic value; the input of the sampling value 0 number statistic device is N-bit sequence data, and the output is sampling value 0 number statistic; the output of the comparison threshold value setter is a comparison threshold value; the input of the first numerical value comparator is 1 number of statistical values and comparison threshold of sampling value, the output is the first set signal; the input of the second numerical value comparator is a sampling value 0 number statistical value and a comparison threshold value, and the output is a second set signal; the input signals of the RS trigger are a first setting signal and a second setting signal, and the output signals are anti-interference output pulses; the input of the voltage-controlled oscillator is frequency control voltage, and the output is sampling clock pulse;

The N is an integer greater than or equal to 2, and the N-bit sequence data is the latest N sampling values of the anti-interference input pulse; the sampling value is binary data 0 or 1; the comparison threshold is an integer which is greater than N/2 and less than or equal to N;

The function of the 1 sampling value statistics device is that 1 output sampling value statistics value is the number of '1' in the input N-bit sequence data; the function of the sampling value 0 number statistic device is that the output sampling value 0 number statistic is the number of '0' in the input N bit sequence data;

the function of the first numerical value comparator is that when the number statistic value of the sampling value 1 is more than or equal to the comparison threshold value, the output first set signal is valid, otherwise, the output first set signal is invalid; the function of the second numerical value comparator is that when the number statistic value of the sampling values 0 is more than or equal to the comparison threshold value, the output second set signal is valid, otherwise, the output second set signal is invalid;

when the speed of the book transmission motor is increased, the frequency of a sampling clock pulse output by the book transmission speed conversion unit is controlled by the frequency control voltage-controlled oscillator to be increased; when the speed of the book transmission motor is reduced, the frequency control voltage output by the book transmission speed conversion unit controls the frequency of the sampling clock pulse output by the voltage-controlled oscillator to be reduced.

2. The automatic book sorting control system of claim 1, wherein: the M sorting driving units are respectively composed of a book baffle driver and a book sorting pushing driver; the M sorting driving control signals are composed of book baffle control signals and book sorting pushing air cylinder control signals.

3. the automatic book sorting control system of claim 1, wherein: the controller unit is a programmable controller, or a singlechip, or an ARM controller.

4. The automatic book sorting control system of claim 1, wherein: the book category information identification unit is an electronic tag reader-writer, or a bar code scanner, or a two-dimensional code scanner.

5. the automatic book sorting control system according to any one of claims 1-4, characterized in that: the first setting signal is a setting signal of the RS trigger, and the second setting signal is a reset signal of the RS trigger; the anti-interference output pulse is output from the in-phase output end of the RS trigger, and the anti-interference output pulse or the anti-phase output end of the RS trigger is output.

6. the automatic book sorting control system of claim 5, wherein: the counting pulse generating circuit is a correlation photoelectric switch.