CN107731692A - The method and integrated circuit of the Plastic Package of integrated circuit - Google Patents
The method and integrated circuit of the Plastic Package of integrated circuit Download PDFInfo
- Publication number
- CN107731692A CN107731692A CN201710953050.5A CN201710953050A CN107731692A CN 107731692 A CN107731692 A CN 107731692A CN 201710953050 A CN201710953050 A CN 201710953050A CN 107731692 A CN107731692 A CN 107731692A
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- pin
- plastic package
- lead frame
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of method and integrated circuit of the Plastic Package of integrated circuit, wherein method includes plating step, the pin of IC-components after curing molding is a part for lead frame, one end that the pin contacts with capsulation material is first end, the other end of the pin is the second end, and the plating step includes：S1, set plating area for the pin second end and the first end between region, gap is provided between the plating area and the capsulation material；S2, using electro-plating method the plating area of the pin is electroplated.The method and integrated circuit of the Plastic Package of integrated circuit provided by the invention improve integrated circuit pin and are in the problem of layering occurs after long-term temperature circulates, and are effectively improved IC-components due to caused by intrinsic product and work flow the problem of long-term reliability.
Description
Technical field
The invention belongs to microelectronics Packaging field, the method for more particularly to a kind of Plastic Package of integrated circuit and integrated electricity
Road.
Background technology
For existing general integrated circuit, 85% or so is constituted about using Plastic Package form, predominant package form has：
(nothing is drawn by PDIP (plastics dual-in-line package shell), PLCC (plastic leaded chip carrier), QFP (four-armed olfactometer), QFN
Line quad flat package), SOP (small outline packages), small thin outline package (TSOP), scaled-down version SOP (SSOP) and thin contracting
Small-sized SOP (TSSOP) etc..
The encapsulation mainly power of consideration device, weight, number of pins, size, density, electroresponse, reliability, heat dissipation etc.
Deng.Function and qualification rate for device are generally not the factor that encapsulation technology considers.
The technical process of existing Plastic Package is as follows：
1) Back grinding (thinned)：Refer to and wafer is allowed to thickness control in certain scope by back side polishing.
2) Wafer Mounting (taut film)：Taut film is mainly to paste the flexible and certain viscosity of last layer to the back side of wafer
Blue film, and be fixed on a slightly larger metal framework of diameter, in favor of processing below.Lean in order to avoid being pasted not strongly and
The film flying problem during scribing is caused, 60~80 degree of temperature is added during taut film.
3) Wafer Sawing/Dicing Saw (scribing)：The purpose of scribing is by each is independent in whole wafer
Circuit by high speed rotation diamond blade cut open come.If above bonding wafer is not firm when taut film or has gas
Bubble is present, and cuts the Die (silicon chip) come open and will fly out from blue film, referred to as film flying.
4) Die Attach/Die Bonding (bonding die)：Bonding die is to drive vacuum slot to cut by mechanical arm to complete
Die/Chip (chip) place and be welded on carrier.Different according to the encapsulated type of device, carrier is also had any different.Conventional modeling
Material encapsulation carrier used is lead frame.
5) Wire Bonding (bonding)：With metal wire by the bond pad (electric connecting point) and lead frame on silicon chip
On lead (pin) or substrate on pad connect.The metal wire of welding typically uses proof gold.
6) Molding (molding)：The step refers to using EPOXY MOLDING COMPOUND (solid epoxy resin molding materials
Material) transfer casting processing procedure.
7) Curing (solidification)：The step, which refers to, is at a certain temperature molded solid epoxy resin molding material solidification.
8) Plating (plating)：The step refers to is electroplated using electro-plating method to good device pin in package shape, with enhancing
The solderability of device.
9) Trimming Forming (Trim Molding)：The step, which refers to, cuts the device of shaping and arranges.
10) Testing/Binning (test/sorting)：Simple open-short circuit is carried out for device, encapsulation process
In ineffective part delete choosing and fall.
11) Marking (printing)：Related table mark and explanation in device surface printing.
12) Packing (packaging)：Device is packaged using specific preventive means (antistatic, protection against the tide etc.).
As the process degree and packaging technology of integrated circuit tend to complicated, in above-mentioned encapsulation process, due to Die
It is different with the hot coefficient of capsulation material, it is possible to cause the long-term reliability problems of product, this problem is for communication or army
With etc. high level use can impact.The long-term reliability of IC-components after Plastic Package is caused problem to be present,
Specific performance is exactly the phenomenon that layering occurs in device after being circulated by long-term temperature.
The content of the invention
The technical problem to be solved in the present invention is that electricity is integrated made of the Plastic Package of existing integrated circuit in order to overcome
Road device is the phenomenon that layering occurs after being circulated by long-term temperature causes reliability to reduce the defects of, there is provided one kind can have
Improve the method and integrated circuit of the Plastic Package of the integrated circuit of the long-term reliability of IC-components in effect ground.
The present invention is that solve above-mentioned technical problem by following technical proposals：
The invention provides a kind of method of the Plastic Package of integrated circuit, including plating step, its feature to be, solidification
The pin of IC-components after shaping is a part for lead frame, and one end that the pin contacts with capsulation material is the
One end, the other end of the pin is the second end, and the plating step includes：
S1, set plating area for the pin second end and the first end between region, the electroplating region
Gap is provided between domain and the capsulation material；
S2, using electro-plating method the plating area of the pin is electroplated.
In this programme, by setting gap between electroplating region and capsulation material so that for pin and plastic packaging material during plating
The part of material contact is not electroplated onto, and so as to reduce the diversity factor of the hot coefficient of the junction of lead frame and capsulation material, is entered
And improve integrated circuit pin and be in the problem of layering occurs after long-term temperature circulates.
It is preferred that the part that the lead frame contacts with the capsulation material is contact zone, methods described also includes pair
The surface of the contact zone of the lead frame carries out coarse processing.
In this programme, the place that lead frame entirety contacts with capsulation material all carries out coarse processing, to increase plastic packaging material
The phenomenon of layering occurs so as to improve device after being circulated by long-term temperature, improves with the frictional force between lead frame for material
The long-term reliability of IC-components after Plastic Package.
It is preferred that the lead frame is weld zone with the part that the silicon chip that cutting is completed is in contact, methods described is also wrapped
Include and groove is set on the periphery of the weld zone of the lead frame.
In this programme, groove is set to drop by the surrounding in the part that lead frame is in contact with the silicon chip that cutting is completed
Low stress, with reach improve Plastic Package after IC-components long-term reliability effect.
It is preferred that the groove is V grooves.
In this programme, stress is reduced by V grooves.
It is preferred that the part that the pin is in contact with the capsulation material is through hole area, methods described is additionally included in institute
State and through hole is set on the through hole area of lead frame.
In this programme, by the clamp force when increasing through hole on pin to increase temperature change, reach improvement plastic seal
The effect of the long-term reliability of IC-components after dress, the specific position for increasing through hole is that pin is in contact with capsulation material
Part.The setting of through hole improves through hole area to the adaptive faculty to be expanded with heat and contract with cold caused by temperature change, is being passed through so as to improve device
Cross after long-term temperature cycles and the phenomenon of layering occurs.
It is preferred that the through hole is shaped as bar shaped.
It is preferred that the capsulation material is G700LALA.
Use can reduce the capsulation material G700LALA of stress in this programme, and the capsulation material is by SUMITOMO CHEMICAL
(Sumitomo) company produces.
Present invention also offers a kind of integrated circuit, its feature is, using the Plastic Package of foregoing integrated circuit
Method encapsulation forms.
The positive effect of the present invention is：The method of the Plastic Package of integrated circuit provided by the invention and integrated electricity
Road by between electroplating region and capsulation material set gap can reduce lead frame and capsulation material junction hot coefficient
Diversity factor, it is same that capsulation material can be increased by the place coarse processing of progress integrally contacted to lead frame with capsulation material
Frictional force between lead frame, groove energy is set by the surrounding in the part that lead frame is in contact with the silicon chip that cutting is completed
Stress is enough reduced, by the clamp force when increasing through hole on pin to increase temperature change, is drawn so as to improve integrated circuit
Pin is in the problem of layering occurs after long-term temperature circulates, and is effectively improved IC-components due to intrinsic production
Caused by product and work flow the problem of long-term reliability.
Brief description of the drawings
Fig. 1 is the flow chart of the method for the Plastic Package of the integrated circuit of the embodiment of the present invention 1.
Fig. 2 is the flow chart of plating step in embodiment 1.
Embodiment
The present invention is further illustrated below by the mode of embodiment, but does not therefore limit the present invention to described reality
Apply among a scope.
Embodiment 1
As shown in figure 1, a kind of method of the Plastic Package of integrated circuit, the pin of the IC-components after curing molding
For a part for lead frame, one end that pin contacts with capsulation material is first end, and the other end of pin is the second end, lead
The part that framework contacts with capsulation material is contact zone, and the part that the silicon chip that lead frame is completed with cutting is in contact is welding
Area, the part that pin is in contact with capsulation material are through hole area, and wherein method comprises the following steps：
Step 101, the surface to the contact zone of lead frame carry out coarse processing, are set on the through hole area of lead frame
Strip through-hole, V grooves are set on the periphery of the weld zone of lead frame；
Step 102, plating.
As shown in Fig. 2 wherein step 102 is further comprising the steps of：
Step 1021, region of the plating area between the second end of pin and first end, plating area and plastic packaging material are set
Gap is provided between material；
Step 1022, using electro-plating method the plating area of pin is electroplated.
In the present embodiment, capsulation material uses G700LALA.
The present embodiment between electroplating region and capsulation material by setting gap so that for pin and capsulation material during plating
The part of contact is not electroplated onto, so as to reduce the diversity factor of the hot coefficient of the junction of lead frame and capsulation material, and then
Improve integrated circuit pin and be in the problem of layering occurs after long-term temperature circulates.
In the present embodiment, the place that lead frame entirety contacts with capsulation material all carries out coarse processing, to increase plastic packaging
The phenomenon of layering occurs so as to improve device after being circulated by long-term temperature, carries with the frictional force between lead frame for material
The long-term reliability of IC-components after high Plastic Package.
In the present embodiment, by the surrounding of part being in contact in lead frame with the silicon chip that cutting is completed set V grooves come
Reduce stress, with reach improve Plastic Package after IC-components long-term reliability effect.
In the present embodiment, by the clamp force when increasing some strip through-holes on pin to increase temperature change, reach
The effect of the long-term reliability of IC-components after improvement Plastic Package, the specific position for increasing through hole is pin and plastic packaging material
Expect the part being in contact.The setting of through hole improves through hole area to the adaptive faculty that is expanded with heat and contract with cold caused by temperature change, so as to change
The phenomenon of layering occurs in kind device after being circulated by long-term temperature.
The method that the present embodiment provides is by improving the packaging technology and material of Plastic Package large scale integrated circuit, effectively
Ground improves IC-components due to integrity problem caused by intrinsic product and work flow, is not changing existing design
With the performance reliably and with long-term that device is improved on the basis of packaging technology, solve the highly reliable of the very strict special product of requirement
Sex chromosome mosaicism.
Embodiment 2
A kind of integrated circuit is present embodiments provided, the integrated circuit uses the plastic seal of the integrated circuit in embodiment 1
The method encapsulation of dress forms.
Although the embodiment of the present invention is the foregoing described, it will be appreciated by those of skill in the art that this is only
For example, protection scope of the present invention is to be defined by the appended claims.Those skilled in the art without departing substantially from
On the premise of the principle and essence of the present invention, various changes or modifications can be made to these embodiments, but these changes and
Modification each falls within protection scope of the present invention.
Claims (8)
1. a kind of method of the Plastic Package of integrated circuit, including plating step, it is characterised in that the integrated electricity after curing molding
The pin of road device is a part for lead frame, and one end that the pin contacts with capsulation material is first end, the pin
The other end be the second end, the plating step includes：
S1, region of the plating area between second end of the pin and the first end, the plating area and institute are set
State and be provided with gap between capsulation material；
S2, using electro-plating method the plating area of the pin is electroplated.
2. the method for the Plastic Package of integrated circuit as claimed in claim 1, it is characterised in that the lead frame with it is described
The part of capsulation material contact is contact zone, and methods described also includes carrying out the surface of the contact zone of the lead frame
Coarse processing.
3. the method for the Plastic Package of integrated circuit as claimed in claim 1, it is characterised in that the lead frame and cutting
The part that the silicon chip of completion is in contact is weld zone, and methods described is additionally included in the periphery of the weld zone of the lead frame
Groove is set.
4. the method for the Plastic Package of integrated circuit as claimed in claim 3, it is characterised in that the groove is V grooves.
5. the method for the Plastic Package of integrated circuit as claimed in claim 1, it is characterised in that the pin and the plastic packaging
The part that material is in contact is through hole area, and methods described also includes setting through hole on the through hole area of the lead frame.
6. the method for the Plastic Package of integrated circuit as claimed in claim 5, it is characterised in that the through hole is shaped as bar
Shape.
7. the method for the Plastic Package of the integrated circuit as described in any one of claim 1 to 6, it is characterised in that the plastic packaging
Material is G700LALA.
8. a kind of integrated circuit, it is characterised in that using the Plastic Package of the integrated circuit described in any one of claim 1 to 7
Method encapsulation form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710953050.5A CN107731692A (en) | 2017-10-13 | 2017-10-13 | The method and integrated circuit of the Plastic Package of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710953050.5A CN107731692A (en) | 2017-10-13 | 2017-10-13 | The method and integrated circuit of the Plastic Package of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107731692A true CN107731692A (en) | 2018-02-23 |
Family
ID=61211242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710953050.5A Pending CN107731692A (en) | 2017-10-13 | 2017-10-13 | The method and integrated circuit of the Plastic Package of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107731692A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110528041A (en) * | 2019-08-13 | 2019-12-03 | 广州兴森快捷电路科技有限公司 | For the electroplating processing method of wafer, wafer and wiring board |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5454929A (en) * | 1994-06-16 | 1995-10-03 | National Semiconductor Corporation | Process for preparing solderable integrated circuit lead frames by plating with tin and palladium |
| US20090315159A1 (en) * | 2008-06-20 | 2009-12-24 | Donald Charles Abbott | Leadframes having both enhanced-adhesion and smooth surfaces and methods to form the same |
| CN101630644A (en) * | 2009-07-31 | 2010-01-20 | 宁波华龙电子股份有限公司 | Method for manufacturing large-scale integrated circuit lead frame |
| CN201417768Y (en) * | 2009-06-09 | 2010-03-03 | 铜陵丰山三佳微电子有限公司 | Lead frame for semi-conductor integrated circuit |
| CN201466062U (en) * | 2009-04-29 | 2010-05-12 | 深圳市矽格半导体科技有限公司 | Integrated fine-pitch pin LED drive circuit packaging structure |
| CN201829484U (en) * | 2010-10-21 | 2011-05-11 | 江阴康强电子有限公司 | Spot type electroplating triode lead frame |
-
2017
- 2017-10-13 CN CN201710953050.5A patent/CN107731692A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5454929A (en) * | 1994-06-16 | 1995-10-03 | National Semiconductor Corporation | Process for preparing solderable integrated circuit lead frames by plating with tin and palladium |
| US20090315159A1 (en) * | 2008-06-20 | 2009-12-24 | Donald Charles Abbott | Leadframes having both enhanced-adhesion and smooth surfaces and methods to form the same |
| CN201466062U (en) * | 2009-04-29 | 2010-05-12 | 深圳市矽格半导体科技有限公司 | Integrated fine-pitch pin LED drive circuit packaging structure |
| CN201417768Y (en) * | 2009-06-09 | 2010-03-03 | 铜陵丰山三佳微电子有限公司 | Lead frame for semi-conductor integrated circuit |
| CN101630644A (en) * | 2009-07-31 | 2010-01-20 | 宁波华龙电子股份有限公司 | Method for manufacturing large-scale integrated circuit lead frame |
| CN201829484U (en) * | 2010-10-21 | 2011-05-11 | 江阴康强电子有限公司 | Spot type electroplating triode lead frame |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110528041A (en) * | 2019-08-13 | 2019-12-03 | 广州兴森快捷电路科技有限公司 | For the electroplating processing method of wafer, wafer and wiring board |
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| PB01 | Publication | ||
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Application publication date: 20180223 |