CN107728707B

CN107728707B - Method for realizing vectored VDS L2 service in VDS L2 system

Info

Publication number: CN107728707B
Application number: CN201710888620.7A
Authority: CN
Inventors: 王瑞波; 张前进
Original assignee: Fiberhome Telecommunication Technologies Co Ltd
Current assignee: Fiberhome Telecommunication Technologies Co Ltd
Priority date: 2017-09-27
Filing date: 2017-09-27
Publication date: 2020-08-04
Anticipated expiration: 2037-09-27
Also published as: CN107728707A

Abstract

The invention discloses a method for realizing vectored VDS L service in a VDS L system, which comprises the steps of respectively allocating a clock circuit and a clock control circuit to each VD32 service machine disk, wherein the number of the VD32 service machine disks is one or two, setting a DSP module as a vectored processor, sending clock receiving control signals to the clock control circuits of different service machine disks through the clock control circuit of the same service machine disk by the DSP module, controlling the corresponding clock circuits to receive clock signals, and sending clock sending control signals to the clock circuit of the same service machine disk, sending clock signals to other DSP modules through the clock circuit of the service machine disk by the vectored processor, receiving the clock signals through the clock circuits on the service machine disk by other DSP modules, and realizing the clock synchronization of all the DSP modules in the system.

Description

Method for realizing vectored VDS L2 service in VDS L2 system

Technical Field

The invention relates to the field of VDS L with vector operation, in particular to a method for realizing vectored VDS L2 service in a VDS L2 system.

Background

In recent years, along with the advance of broadband speed-raising engineering, a plurality of cells are reformed by copper entering and exiting, but through practice, people find that the difficulty of the whole reforming and the cost of more than 75 percent are in the section of entering the home of an optical cable in old cells accessed by a plurality of copper cables due to the problems of property coordination, unwilling change of home decoration of users and the like, and according to statistics, the cells which are not suitable for light reforming account for more than 50 percent of the total amount of the reformed cells, while in the current network stock of the domestic copper cables, the years of 82.6 percent of the copper cables are less than or equal to 20 years, wherein 70 percent of the copper cables are less than or equal to 1000 meters in length and the use state and the environment are good, so that the original copper wire network is utilized, the innovative copper wire technology is adopted to realize broadband speed raising of the old cells, and obviously has more advantages than re-laying of the optical cables in the north, L2 effectively solves the last problem through ten high-cost-performance mixed optical fibers to the home, and currently, VDS L2 current network business breaks through million wires, covers the communication in China, 20 and more than ten-ten.

The Vectoring is used as an enhanced technology of the VDS L2, 100M access can be realized within 500M by means of a mode of canceling crosstalk through superposition of vector matrixes, 150M access can be supported within 300M, long-term targets of family personal broadband access are met, the Vectoring VDS L2 home entry is comparable to the bandwidth capacity of FTTH, compared with the construction mode of FTTH, cables do not need to be transformed, engineering is simple, service distribution is fast, software upgrading is only needed for most of VDS L terminals distributed recently, hardware cost is not increased, and absolute cost advantage is achieved.

A remote ONU device (e.g. a beacon AN5006-20 plug-in MDU) supporting both the conventional 32 VDS L2 services and the vectored VDS L2 services can support 4 VD32 service disks, each VD32 service disk includes 2 DSP chips, each DSP chip can provide 16 VDS L signal access capabilities conforming to the 17A template, wherein the DSP chip is used as a core device of each chassis and mainly performs processing of a coding/decoding algorithm and a vectored algorithm, and in order to open the vectored VDS L services of the 4 VD32 service disks, a central vector operation disk needs to be installed above a main control disk of the remote ONU device, and vector calculation for processing the 128 vectored VDS L services of the 4 VD32 service disks is higher, so the central vector operation disk needs to be powerful in function and correspondingly consume power.

In most engineering application scenarios, one remote ONU device only assembles 2 or 1 VD32 service disks, but in order to open vectoring VDs L service, a central vector operation disk must be configured, and in this case, the device cost and power consumption increase, considering that in the actual engineering at the present stage, vectoring VDs L service needs to be opened, and the device application number that only assembles 2 or 1 VD32 service disks is large, which causes a large energy waste, runs counter to the policy of energy conservation and emission reduction advocated by the country, and does not meet the goal of energy conservation and emission reduction of three telecommunication operators.

Disclosure of Invention

The technical problem to be solved by the invention is that in a VDS L2 device which simultaneously supports the traditional 32-path VDS L2 service and vectorngVDS L2 service, even if a vectorring VDS L service is to be opened under the condition that only 2 or 1 VD32 service chassis is assembled, a central vector operation disk must be configured to process the vector calculation of vectorring VDS L services of all chassis.

In order to solve the above technical problem, the technical solution adopted by the present invention is to provide a method for implementing a vectored VDS L2 service in a VDS L2 system, comprising the following steps:

each VD32 service machine disk is provided with a clock circuit and a clock control circuit, and the number of VD32 service machine disks is one or two;

a first DSP module in the previous VD32 service machine disk is set as a vectored processor, and the DSP module sends a clock receiving control signal to clock control circuits of different VD32 service machine disks through a clock control circuit of the VD32 service machine disk, and controls a corresponding clock circuit to receive a clock signal; and sending a clock sending control signal to a clock circuit of the same VD32 service machine disk;

the DSP module set as the vectored processor sends a synchronous clock signal to the DSP module on the same VD32 service machine disk, and sends a synchronous clock signal to the DSP modules on other VD32 service machine disks in the system through the clock circuit of the service machine disk, and the DSP modules on other VD32 service machine disks receive the synchronous clock signal through the clock circuit on the VD32 service machine disk, so that the clock synchronization of all the DSP modules in the system is realized.

In the method, the logic control circuit of the clock circuit is composed of a first logic gate and a second logic gate;

the input end of the first logic gate is a single-ended clock sending end, and the enabling control end is a sending enabling control end; the output end of the second logic gate is a single-ended clock receiving end, and the enabling control end is a receiving enabling control end;

the first output end of the first logic gate is connected with the second input end of the second logic gate, and outputs or inputs a first electric signal; the third output end of the first logic gate is connected with the fourth input end of the second logic gate, and outputs or inputs a second electric signal; the first electrical signal and the second electrical signal constitute a clock signal;

the third output end is an inverted output, and the fourth input end is an inverted input.

In the above method, the logic control of the clock circuit specifically includes:

in the clock signal reception direction:

when the receiving enabling control end is at a low level, the input clock signal is at the low level, and the single-ended clock receiving end outputs the low level; when the receiving enabling control end is at a low level, the input clock signal is at a high level, and the single-ended clock receiving end outputs the high level; when the receiving enabling control end is at a high level, the clock circuit is in a sending state, and the single-ended clock receiving end is always in a high-resistance state; the input clock signal is obtained by subtracting the second electrical signal input by the fourth input end from the first electrical signal input by the second input end;

in the clock signal transmission direction:

when the sending enable control end is at a high level, the single-ended clock sending end inputs a low level, the first output end outputs a low level, and the third output end outputs a high level; when the sending enable control end is at a high level, the single-ended clock sending end inputs the high level, the first output end outputs the high level, and the third output end outputs the low level; when the transmission enabling control end is at a low level, the receiving state of the clock circuit is closed, and the first output end and the third output end are always in a high-resistance state.

In the method, the core chip of the clock circuit adopts an SN65M L VD205ADR clock chip.

In the method, the number of VD32 service machine disks in the VDS L2 system is two, namely a first VD32 service machine disk and a second VD32 service machine disk, wherein,

the first VD32 service machine disk comprises a first DSP module, a third DSP module, a first clock circuit and a first clock control circuit;

the second VD32 service machine disk comprises a second DSP module, a fourth DSP module, a second clock circuit and a second clock control circuit;

the first DSP module is the first DSP module of the first VD32 server disk located in front,

the first DSP module sends a synchronous clock signal to the third DSP module; the first clock control circuit controls the first clock circuit to open a synchronous clock channel sent to the backboard, close a receiving channel and send a receiving control signal to the second clock control circuit; the second clock control circuit controls a back plate synchronous clock receiving channel of the second clock circuit to be opened and closes a sending channel according to the receiving control signal; the first DSP module sends a synchronous clock signal to a synchronous clock channel of the back plate through the first clock circuit, and the second DSP module and the fourth DSP module receive the synchronous clock signal through a back plate synchronous clock receiving channel of the second clock circuit.

In the method, under the condition that the vectored VDS L2 service is not enabled, the first and second clock control circuits default to turn off the first and second clock circuits, set the receive enable to a high level, set the transmit enable to a low level, and set the clock signal output and input terminals to a high impedance state.

In the above method, under the condition that the vectored VDS L2 service is enabled, the clock synchronization of all DSP modules in the system specifically includes the following steps:

when the first DSP block is selected to be the vectored processor,

step S10, the first clock control circuit sets the transmission enable of the first clock circuit to high, the transmission state of the clock circuit is on, and the reception direction remains in a high impedance state;

step S20, the first clock control circuit sends a clock reception control signal to the second clock control circuit, which controls the second clock circuit to receive;

step S30, the second clock control circuit closes the sending state of the clock circuit and opens the receiving state according to the clock receiving control signal;

step S40, the first DSP module directly sends a synchronous clock signal to the third DSP module, and sends a synchronous clock signal to the second DSP module and the fourth DSP module through the first clock circuit;

step S50, the second clock circuit receives the clock signal through the backboard;

step S60, the second clock circuit sends the received clock signal to the second and fourth DSP modules to realize the clock synchronization between the disks;

when the second VD32 service disk is the previous service disk, the first DSP module of the second VD32 service disk is selected as the vectored processor, and the processing manner is the same as the above principle.

In the invention, under the application scene of only assembling 1 or 2 VD32 service disks, one DSP chip is selected to complete Vectoring operation of the whole system, a central vector operation disk is reduced, and each VD32 service disk is provided with a clock circuit and a clock control circuit respectively, so that the transmission of clock signals between disks and the change of the transmission direction are realized, the clock synchronization between the disks is completed, and finally the function of realizing board-level vectored VDS L is completed, thereby reducing the manufacturing cost and the whole power consumption of a VDS L2 system (such as AN5006-20 system) which simultaneously supports the traditional 32-channel VDS L2 service and the vectored VDS L2 service, reducing energy waste and realizing green energy-saving communication.

Drawings

Fig. 1 is a schematic diagram of an implementation structure of a method for implementing a vectored VDS L2 service in a VDS L2 system when the number of VD32 service disks is two according to the present invention;

fig. 2 is a flowchart of a method for implementing vectored VDS L2 service in a VDS L2 system according to the present invention when the number of VD32 service disks is two;

FIG. 3 is a schematic diagram of a logic control circuit of the clock circuit of the present invention.

Detailed Description

In a VDS L2 system supporting a conventional 32-way VDS L2 service and a vectored VDS L2 service at the same time, since the vectored processor in each DSP chip can perform vectored operation processing on 64-way VDS L2 service at the same time in two DSP chips included in each VD32 service disk, in an application scenario where only 1 or 2 VD32 service disks are assembled, the vectored operation of the whole system can be completed only by selecting one DSP chip, a central vector operation disk is omitted, and the purposes of saving energy and reducing power consumption are achieved.

In order to implement the above scheme, it is necessary to ensure clock synchronization of 4 DSP chips of two VD32 service disks, that is, when one DSP chip in one of the VD32 service disks is selected as a vectoring processor, the DSP chip needs to output a clock signal to the outside, and the remaining three DSP chips receive the synchronized clock signal; when another VD32 service machine disk is selected as the vectorring processor, the transmission direction of the clock signal is opposite.

The invention is described in detail below with reference to the figures and specific examples.

The invention provides a method for realizing a vectored VDS L2 service in a VDS L2 system, which comprises the following specific steps:

in a VDS L2 system with one or two VD32 service disks, each VD32 service disk is provided with a clock circuit and a clock control circuit respectively to realize the transmission of clock signals between the disks and the change of the transmission direction;

a user sets a first DSP module (DSP chip) in a previous VD32 service machine disk as a vectored processor according to requirements; the DSP module sends a clock receiving control signal to clock control circuits of different VD32 service machine discs through the clock control circuit of the VD32 service machine disc, and controls a corresponding clock circuit (on a VD32 service machine disc different from a vectored processor) to receive a clock signal; and sending a clock sending control signal to a clock circuit of the same D32 service machine disk;

the DSP module set as the vectored processor sends a synchronous clock signal to the DSP module on the same VD32 service machine disk, sends the synchronous clock signal to the DSP modules on other VD32 service machine disks in the system through the clock circuit on the VD32 service machine disk where the DSP module is located, and receives the synchronous clock signal through the clock circuit on the VD32 service machine disk where the DSP module on other VD32 service machine disks are located, so that the clock synchronization of all the DSP modules in the system is realized.

The following describes in detail the implementation process of the present invention by taking a VDs L2 system with two VD32 service disks as a specific embodiment, as shown in fig. 1, this embodiment includes a first VD32 service disk 10 and a second VD32 service disk 20, where the first VD32 service disk 10 includes a first DSP module 11, a third DSP module 12, a first clock circuit 13 and a first clock control circuit 14, the second VD32 service disk 20 includes a second DSP module 21, a fourth DSP module 22, a second clock circuit 23 and a second clock control circuit 24, for the VDs L2 systems of the two VD32 service disks, only the first DSP module of the previous service disk can be selected as a clock source, and the second DSP of each VD32 disk cannot be used as a clock source.

The first DSP module 11 is used as the first DSP module of the first VD32 service machine disk 10 of the previous service machine disk, and the first DSP module 11 directly sends a synchronous clock signal to the third DSP module 12; the first clock control circuit 14 controls the first clock circuit 13 to open the synchronous clock channel to the backplane, closes the receiving channel, and sends corresponding control information to the second clock control circuit 24; the second clock control circuit 24 controls the back board synchronous clock receiving channel of the second clock circuit 23 to open and close the sending channel according to the corresponding control information, so as to realize that the second clock circuit 23 of the second VD32 service disk 20 keeps clock signal synchronization with the first VD32 service disk 10; the first DSP module 11 sends a synchronous clock signal to the synchronous clock channel of the backplane through the first clock circuit 13; the second DSP module 21 and the fourth DSP module 22 receive the synchronous clock signal sent by the first DSP module 11 through the backplane synchronous clock receiving channel of the second clock circuit 23.

(1) Under the condition that the vectored VDS L2 service is not enabled, no clock transmission is needed between the VD32 service disks, at this time, the first clock control circuit and the second clock control circuit default to close the first clock circuit and the second clock circuit, the receiving enable is set to be high level, the sending enable is set to be low level, and at this time, the differential clock output is in a high impedance state.

(2) Under the condition that the vectored VDS L2 service is enabled, when the first DSP module is selected as the vectored processor, as shown in fig. 2, implementing clock synchronization of all DSP modules in the system specifically includes the following steps:

in step S10, the first clock control circuit of the first VD32 service disk sets the transmission enable of the first clock circuit to high, the transmission state of the clock circuit is turned on, and the reception direction remains in a high impedance state.

In step S20, the first clock control circuit transmits a clock reception control signal for controlling the second clock circuit to receive, to the second clock control circuit.

In step S30, the second clock control circuit turns off the transmission state of the clock circuit and turns on the reception state according to the clock reception control signal.

Step S40, the first DSP module sends the synchronous clock signal directly to the third DSP module, and sends the synchronous clock signal to the other DSP modules (the second DSP module and the fourth DSP module) through the first clock circuit.

Step S50, the second clock circuit of the second VD32 service disk receives the clock signal sent from the opposite end (the first clock circuit) through the backplane.

And step S60, the second clock circuit sends the received clock signal to the second DSP module and the fourth DSP module to realize the clock synchronization between the disks.

When the second VD32 service disk is the previous service disk, the first DSP module of the second VD32 service disk is selected as the vector processor, the processing mode is the same as the above principle, and is not described herein again.

As shown in fig. 3, a schematic diagram of a logic control circuit of a clock circuit according to the present invention is shown, the logic control circuit of the clock circuit is composed of a first logic gate S1 and a second logic gate S2, an input end of the first logic gate S1 is a single-ended clock sending end D, an enable control end is a sending enable control end DE, when the sending enable control end DE is at a high level, the clock circuit is in an open sending state, an output end of the second logic gate S2 is a single-ended clock receiving end R, the enable control end is a receiving enable control end, when the receiving enable control end is at a low level, the clock circuit is in an open receiving state, a first output end Y of the first logic gate S1 is connected to a second input end a of the second logic gate S2 to output or input a first electrical signal, a third output end Z of the first logic gate S1 is connected to a fourth input end B of the second logic gate S2 to output or input a second electrical signal, the first electrical signal and the second electrical signal form a differential clock signal L (the third clock signal, the third output end Z is an inverted input end, and the fourth input end B is an.

The specific logic control of the clock circuit is (as shown in the logic control description of the clock circuit in table 1):

in the clock signal reception direction:

when the receiving enable control terminal is at a low level, the input clock signal VID = a first electrical signal VA input from the second input terminal a-a second electrical signal VB input from the fourth input terminal B is at a low level, and the single-ended clock receiving terminal R outputs a low level; when the receiving enabling control end is at a low level, the input clock signal VID is at a high level, and the single-ended clock receiving end R outputs a high level; when the receiving enable control end is in a high level, the sending state of the clock circuit is closed, the input clock signal VID is not processed no matter the input clock signal VID inputs the high level or the low level, and the single-ended clock receiving end R is always in a high-impedance state.

In the clock signal transmission direction:

when the transmission enable control end DE is at a high level, the single-ended clock transmission end D inputs a low level, the first output end Y outputs a low level, and the third output end Z outputs a high level; when the transmission enable control end DE is at a high level, the single-ended clock transmission end D inputs the high level, the first output end Y outputs the high level, and the third output end Z outputs the low level; when the transmission enable control terminal DE is at a low level, the receiving state of the clock circuit is turned off, the single-ended clock transmission terminal D does not process whether a high level or a low level is input, and the first output terminal Y and the third output terminal Z are always at a high impedance state.

Table 1: logic control description of the clock circuit.

Wherein, X represents that the input signal is not processed, when the input signal is at a high level and DE is at a low level, the single-ended clock receiving end R, the first output end Y and the third output end Z are in a high impedance state, the first clock circuit and the second clock circuit are in an off state, and the vectored VDS L2 service is not turned on.

In the invention, the core chip of the clock circuit adopts an SN65M L VD205ADR clock chip, and the chip can realize the isolation and the disconnection of clock signals, control the change of the sending direction of the clock signals and realize the conversion of a single-ended clock and a differential clock.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A method for implementing vectored VDS L2 services in a VDS L2 system, comprising the steps of:

the DSP module set as a vectored processor sends a synchronous clock signal to the DSP module on the same VD32 service machine disk, and sends a synchronous clock signal to the DSP modules on other VD32 service machine disks in the system through a clock circuit of the service machine disk, and the DSP modules on the other VD32 service machine disks receive the synchronous clock signal through a clock circuit on the VD32 service machine disk, so that the clock synchronization of all the DSP modules in the system is realized;

under the condition that the vectored VDS L2 service is not started, no clock transmission is needed among VD32 service disks;

under the condition that the vectored VDS L2 service is enabled, clock synchronization of all DSP modules in the system specifically includes the following steps:

when the first DSP block is selected to be the vectored processor,

when the second VD32 service disk is the previous service disk, the first DSP module of the second VD32 service disk is selected as the vectoring processor, and the processing mode is the same as the principle;

the logic control of the clock circuit specifically comprises:

in the clock signal reception direction:

when the receiving enabling control end is at a low level, the input clock signal is at the low level, and the single-ended clock receiving end outputs the low level; when the receiving enabling control end is at a low level, the input clock signal is at a high level, and the single-ended clock receiving end outputs the high level; when the receiving enabling control end is at a high level, the clock circuit is in a sending state, and the single-ended clock receiving end is always in a high-resistance state; the input clock signal is obtained by subtracting the second electric signal input by the fourth input end from the first electric signal input by the second input end;

in the clock signal transmission direction:

2. The method of claim 1, wherein the logic control circuit of the clock circuit is comprised of a first logic gate and a second logic gate;

3. The method of claim 1, wherein a core chip of the clock circuit employs an SN65M L VD205ADR clock chip.

4. The method of claim 1, wherein the number of the VD32 service disks in the VDS L2 system is two, namely a first VD32 service disk and a second VD32 service disk, wherein the first VD32 service disk comprises a first DSP module, a third DSP module, a first clock circuit and a first clock control circuit;

5. The method of claim 4, wherein in the case that vectored VDS L2 traffic is not enabled, the first and second clock control circuits default to turning off the first and second clock circuits, setting receive enable high, setting transmit enable low, and the clock signal output and input terminals are in a high impedance state.