CN107707246A - The subthreshold value CMOS level shifting circuits and implementation method of internet of things oriented - Google Patents
The subthreshold value CMOS level shifting circuits and implementation method of internet of things oriented Download PDFInfo
- Publication number
- CN107707246A CN107707246A CN201710731861.0A CN201710731861A CN107707246A CN 107707246 A CN107707246 A CN 107707246A CN 201710731861 A CN201710731861 A CN 201710731861A CN 107707246 A CN107707246 A CN 107707246A
- Authority
- CN
- China
- Prior art keywords
- threshold voltage
- pmos
- nmos
- voltage pmos
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
The invention discloses the subthreshold value CMOS level shifting circuits and implementation method of internet of things oriented, sub-threshold level converter in the present invention, by using prime current mirror (including two regular threshold voltage PMOS, one high threshold voltage PMOS and two low threshold voltage NMOS) threshold mos device optimization and balance the pull-up of overall transformation device and the driving force of pulldown network (cross-coupled circuit pull-up pulldown network be made up of respectively two high threshold PMOS and two Low threshold NMOS), realize low delay, low-power consumption, small area and the design object of ultralow subthreshold voltage input.
Description
Technical field
The present invention relates to the subthreshold value CMOS electricity of multi-power source voltage IC design field, more particularly to internet of things oriented
Flat change-over circuit and implementation method, subthreshold value CMOS level shifting circuits have high speed, energy efficient, wide input range dash forward
Go out characteristic.
Background technology
Multi-power source voltage technology has been widely used in (Y.Kim, I.Hong, and in modern low power consumption integrated circuit design
H.-J.Yoo,“A 0.5v 54w ultra-low-power recognition processor with
93.5compression,”in IEEE Int.Solid-State Circuits Conf.(ISSCC)
Dig.Tech.Papers,San Francisco,CA,Feb 2015,pp.330-331).Circuit is divided into different by the technology
Module, modules are operated in each different power supplys：Non-key piece of module using provide near/low threshold voltage (VDDL) with
Optimize power consumption, and higher voltage (VDDH) is supplied to key modules to realize that speed maximizes.Therefore, level shifter turns into not
With the indispensable circuit unit to be communicated between voltage domain.Simultaneously as the data bandwidth increase of modern integrated circuits design,
The significant increase of quantity of level translator.In order to optimize the performance entirely designed, level translator must realize low-power, facet
The technical goal of product and low propagation delay.
Current CMOS level translation devices are all based on two kinds of traditional level translators：One kind is that Cross coupled level turns
Parallel operation；Another kind is the level translator based on current mirror.Fig. 1 (a)-Fig. 1 (b), it is the principle of two conventional level shifters
Figure.Wherein, the PMOS that Fig. 1 (a) Cross coupled level shift unit is coupled using a pair of cross is to positive and negative in (MP1 and MP2)
Feedback produces full swing voltage output.But when input voltage is less than NMOS threshold voltage, the NMOS of drop-down to (MN1 and
MN2 driving intensity) is weak much by the driving intensity than PMOS pairs of pull-up.Therefore, exporting logic possibly can not switch.This
Problem can be by increasing several orders of magnitude to solve by NMOS size, while needs bigger power consumption and silicon area.Fig. 1
(b) another traditional level shifter in realizes the conversion of level using current mirror.But the shortcomings that converter is when defeated
Enter for high level when, flow through MP1 electric current can caused by larger static power.
In addition, generally all there is bigger Power leakage, incoming level narrow range and from low in current level translator
The problem of time delay that level is changed to high level is longer.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of low delay of internet of things oriented, energy efficient, ultra low voltage
The sub-threshold level converter of input.
Solve above-mentioned technical problem, the invention provides sub-threshold level converter, that includes：With backfeed loop
Current mirror and cross-coupled circuit, and by prime current mirror and multi-threshold mos device come balance the pull-up of overall transformation device and
The driving force of pulldown network, realize the optimization of the converter power consumption, speed and area.
Specifically, a kind of subthreshold value CMOS level shifting circuits are provided in the present invention, including：It is input buffer, anti-
The current mirror, cross-coupled circuit and output buffer on road are fed back to, the input buffer is as the anti-phase of low threshold voltage
Device, the output of the cross-coupled circuit export through output buffer,
The current mirror of the backfeed loop is located at prime, is connected with the cross-coupled circuit positioned at rear class,
Input voltage is promoted in the cross-coupled circuit on NMOS threshold value by the current mirror of the backfeed loop.
Further, the current mirror of the backfeed loop includes：First regular threshold voltage PMOS, the second normality threshold electricity
PMOS, the first high threshold voltage PMOS are pressed,
The first regular threshold voltage PMOS and the second regular threshold voltage PMOS source electrode connect high supply voltage respectively,
The drain electrode of the first regular threshold voltage PMOS connects the source electrode of the first high threshold voltage PMOS,
Also include：First low threshold voltage NMOS, the second low threshold voltage NMOS,
The source ground of the first low threshold voltage NMOS, the drain electrode of the second regular threshold voltage PMOS connect described
Second low threshold voltage NMOS drain electrode, the source ground of the second low threshold voltage NMOS,
The first regular threshold voltage PMOS and the second regular threshold voltage PMOS grid are connecing described first just
Normal threshold voltage PMOS drain electrode, the grid of the first high threshold voltage PMOS connect the second regular threshold voltage PMOS's
Drain electrode；
Meanwhile the grid of the first low threshold voltage NMOS is connect into input as the first input end of the current mirror and delayed
One end of device is rushed,
The second input termination input buffer using the grid of the second low threshold voltage NMOS as the current mirror
The other end；
The first output end using the drain electrode of the first regular threshold voltage PMOS as the current mirror, by described second
Second output end of the regular threshold voltage PMOS drain electrode as the current mirror.
Further, the cross-coupled circuit includes：3rd low threshold voltage NMOS, the 4th low threshold voltage NMOS,
4th high threshold voltage PMOS and the 5th high threshold voltage PMOS,
The 4th high threshold voltage PMOS and the 5th high threshold voltage PMOS source electrode connects high supply voltage, described
4th high threshold voltage PMOS grid meets the drain electrode of the 5th high threshold voltage PMOS, the 5th high threshold voltage PMOS
Grid connect the 4th high threshold voltage PMOS drain electrode；The drain electrode of the 3rd low threshold voltage NMOS connects the 4th high threshold
Voltage PMOS drain electrode, the drain electrode of the 4th low threshold voltage NMOS connect the 5th high threshold voltage PMOS drain electrode, and described
Three low threshold voltage NMOS source electrode and the 4th low threshold voltage NMOS source ground；
The grid of the 3rd low threshold voltage NMOS is connect to the second output end of the current mirror of the backfeed loop,
The grid of the 4th low threshold voltage NMOS is connect to the second output end of the current mirror of the backfeed loop；
Output end using the drain electrode of the 5th high threshold voltage PMOS as the subthreshold value CMOS level shifting circuits.
Beneficial effects of the present invention：
Sub-threshold level converter in the present invention, by using prime current mirror and multi-threshold mos device optimization and
Balance overall transformation device pull-up and pulldown network (cross-coupled circuit pull-up pulldown network have two high threshold PMOS respectively
Formed with two Low threshold NMOS) driving force, it is defeated to realize low delay, low-power consumption, small area and ultralow subthreshold voltage
The design object entered.
Brief description of the drawings
Fig. 1 (a), (b) are level translator structural representations of the prior art；
Fig. 2 is the structural representation of the sub-threshold level converter in one embodiment of the invention；
Fig. 3 is the Transient waveform diagram that operation principle coordinates its each node；
Fig. 4 is the total power consumption and VDDL relation schematic diagrams of level translator；
Fig. 5 is leakage current and input VDDL relation schematic diagrams；
Fig. 6 is VDDL and the corresponding relation schematic diagram of propagation delay；
Fig. 7 is the working frequency and total power consumption, the relation schematic diagram of total power consumption when 0.2V is converted to 1.2V；
Fig. 8 is the implementation method schematic flow sheet of the present invention.
Embodiment
The principle of the disclosure is described referring now to some example embodiments.It is appreciated that these embodiments are merely for saying
It is bright and help it will be understood by those skilled in the art that with the purpose of the embodiment disclosure and describe, rather than suggest the model to the disclosure
Any restrictions enclosed.Content of this disclosure described here can in a manner of described below outside various modes implement.
As described herein, term " comprising " and its various variants are construed as open-ended term, it means that " bag
Include but be not limited to ".Term "based" is construed as " being based at least partially on ".Term " one embodiment " it is understood that
For " at least one embodiment ".Term " another embodiment " is construed as " at least one other embodiment ".
It refer to the structural representation that Fig. 2 is the sub-threshold level converter in one embodiment of the invention, a kind of subthreshold value
CMOS level shifting circuits, including：Input buffer, the current mirror of backfeed loop, cross-coupled circuit and output buffer,
Phase inverter of the input buffer as low threshold voltage, the output of the cross-coupled circuit export through output buffer,
The current mirror of the backfeed loop is located at prime, is connected with the cross-coupled circuit positioned at rear class, the electric current of the backfeed loop
Input voltage is promoted in the cross-coupled circuit on NMOS threshold value by mirror.Electricity will be inputted by using prime current mirror
Pressure lifting the balance optimizing driving force for pulldown network of coming up, realizes work(into cross-coupled circuit on NMOS threshold value
Consumption, the optimization of delay, the wide scope of input voltage.
As preferred in the present embodiment, the current mirror of the backfeed loop includes：First regular threshold voltage PMOS1,
Second regular threshold voltage PMOS2, the first high threshold voltage PMOS3, the first regular threshold voltage PMOS1 and second are normal
Threshold voltage PMOS2 source electrode connects high supply voltage respectively, and the drain electrode of the first regular threshold voltage PMOS1 connects described first
High threshold voltage PMOS3 source electrode, in addition to：First low threshold voltage NMOS3, the second low threshold voltage NMOS4, described first
Low threshold voltage NMOS3 source ground, the drain electrode of the second regular threshold voltage PMOS2 connect second low threshold voltage
NMOS4 drain electrode, the source ground of the second low threshold voltage NMOS4, the first regular threshold voltage PMOS1 and described
Second regular threshold voltage PMOS2 grid connects the drain electrode of the first regular threshold voltage PMOS1, the first high threshold electricity
Pressure PMOS3 grid connects the drain electrode of the second regular threshold voltage PMOS2；Meanwhile by the first low threshold voltage NMOS3
Grid one end of input buffer is connect as the first input end of the current mirror, by the second low threshold voltage NMOS4
Grid as the current mirror second input termination input buffer the other end；By first regular threshold voltage
First output end of the PMOS1 drain electrode as the current mirror, using the drain electrode of the second regular threshold voltage PMOS2 as institute
State the second output end of current mirror.The CMOS level shifting circuits of the level translator proposed in the present embodiment are realized such as Fig. 2 institutes
Show, can preferably simultaneously use multi thresholds device (MTCMOS) technical optimization propagation delay and reduce energy expenditure, using more
Threshold device is used cooperatively the design for further optimizing CMOS level shifting circuits.Wherein, IN complementary signal IN_ is inputted
NOT is generated by the input buffer of Low threshold, and the purpose for using Low threshold device is to reduce the delay of input.Immediately
, input voltage is increased to the voltage for being close to or higher than NMOS threshold values by prime current mirror, to balance cross-couplings electricity below
Come on road and pull down driving force.High threshold PMOS (MP3) accesses the backfeed loop of current mirror, for eliminating in the current mirror of front end
Quiescent current.
The use of the reason for high threshold PMOS is that can further reduce its leakage current.Pulldown network (MN1, MN2, MN3 and
MN4) realized with Low threshold NMOS, and upper pull-up network is made up of the PMOS (MP4 and MP5) of high threshold, the work of limiting circuit
Make electric current.
As preferred in the present embodiment, the cross-coupled circuit includes：It is 3rd low threshold voltage NMOS7, the 4th low
Threshold voltage NMOS8, the 4th high threshold voltage PMOS5 and the 5th high threshold voltage PMOS6, the 4th high threshold voltage
PMOS and the 5th high threshold voltage PMOS source electrode connect high supply voltage, and the grid of the 4th high threshold voltage PMOS connects
The drain electrode of the 5th high threshold voltage PMOS, the grid of the 5th high threshold voltage PMOS meet the 4th high threshold voltage PMOS
Drain electrode；The drain electrode of the 3rd low threshold voltage NMOS connects the drain electrode of the 4th high threshold voltage PMOS, and the described 4th is low
Threshold voltage NMOS drain electrode connects the 5th high threshold voltage PMOS drain electrode, the source electrode of the 3rd low threshold voltage NMOS and
Four low threshold voltage NMOS source ground；Further, the grid of the 3rd low threshold voltage NMOS is connect into described feed back to
Second output end of the current mirror on road, further, the grid of the 4th low threshold voltage NMOS is connect into the backfeed loop
Second output end of current mirror；Further, using the drain electrode of the 5th high threshold voltage PMOS as subthreshold value CMOS electricity
The output end of flat change-over circuit.
In certain embodiments, incoming level is connect in the first input end of the current mirror of the backfeed loop.
In certain embodiments, incoming level is terminated and by described in the second input of the current mirror of the backfeed loop
Input buffer exports.
In certain embodiments, low suppling voltage is terminated in the power input of the input buffer.
In certain embodiments, the output buffer is connected on the output end of sub-threshold level converter.
In certain embodiments, the power input of the output buffer terminates high supply voltage.
In certain embodiments, CMOS level shifting circuits also include：Multi thresholds device MTCMOS, prolongs to reduce input
Late.
Refer to Fig. 3 is the Transient waveform diagram that operation principle coordinates its each node, specifically in the present embodiment
In the operation principle of sub-threshold level converter to coordinate the Transient waveform of its each node to be described as follows：Here low electricity
Voltage VDDL and high power supply voltage VDDH are respectively 0.2V and 1.2V in source.Differential Input IN and IN_NOT frequency are 1MHz.It is first
First, in the logic high to Low transition period, i.e. IN is height, and IN_NOT is low, and MN1 is conducting state.Electric current I1Flow through MP1, MP3 and
MN1.Then this current mirror is to MP2.When MN2 is closed, node A will be electrically charged, until MP3 is closed.Due to using the anti-of MP3
Feedback, quiescent current reduce.MP3 is realized using the PMOS of high threshold voltage, further reduces quiescent current.On the other hand, patrolling
Collect the low to high transition period, i.e. IN is low, and IN_NOT is height, and MN1 is closed, and MN2 is turned on.Node A will discharge into ground, and node B
It would rise to voltage VDDH-Vth：MP1-Vth：MP3.Vth：MP1 and Vth：MP3 is MP1 and MP3 threshold voltage respectively.Most
Afterwards, cross coupling structure further brings up to high level voltage 1.2V VDDH.Exceed or approach because node A and B have
The high level voltage of NMOS threshold values, so A and B can easily exceed corresponding PMOS transistor MP4 and MP5 driving intensity
Successfully to overturn.It is worth noting that, node A and B high level voltage should be adjusted suitably：If too high, whole level
The power consumption of converter will be very big；If too low, very large-sized MP4 and MP5 is needed to change success.Pulldown network and
Upper pull-up network respectively with low the present embodiment level translator via 65nm MTCMOS techniques realize.Its specific test knot
Fruit is as follows：
For testing power consumption, VDDL is changed to 1V from for 0.1V, and is fed with 1MHz frequency.Fig. 4 shows this implementation
The total power consumption of the level translator proposed in example is with VDDL relations.It can be seen that VDDL is the optimization area of power consumption from 0.2V to 0.7V
Between.When VDDL is less than 0.2V, the reason for power consumption is big is that drivings of the NMOS to (MN1 and MN2) in prime current mirror is strong
Degree is limited by small VDDL.Therefore, the input node A or B for cross coupling structure can not be completely discharged to ground.Saving
The larger voltage of logical zero is by the MN5 or MN6 that cause low threshold voltage higher power consumption at point A or B.On the other hand, due to low
Threshold voltage input buffer (MP11 and MN11), when VDDL is higher than 0.7V, general power increase.
Leakage current and input VDDL relations in the present embodiment is as shown in Figure 5.In power optimization region, (i.e. VDDL is 0.2V
To 0.7V), leakage-power is about 2.1nW.When VDDL is more than 0.7V, total significant increase of leakage current, this is primarily due to input
The leakage current increase of the input buffer of low threshold voltage.
Fig. 6 is for VDDL and the corresponding relation of propagation delay.It can be seen that propagation delay and VDDL are inversely, this shows
Level shifter in the present embodiment can be operated in upper frequency with larger VDDL.Typical propagation delay is 0.2V's
It is 20.38ns during VDDL.Fig. 7 is the working frequency and total power consumption, the relation of total power consumption when 0.2V is converted to 1.2V.Its
In, power consumption is directly proportional to incoming frequency.The maximum operation frequency that VDDL is 0.2V is 16MHz.When conversion 0.2V to 1.2V, clock
When frequency is 10MHz, the minimal energy consumption each changed is 26.61fJ.
The performance of this level translator and the performance comparison of existing level translator are as shown in table 1.Itd is proposed in the present embodiment
Level translator design there is minimum convertible VDDL (0.09V) and lowest latency (20.38ns) in the design of implementation,
Consume the significant advantage of minimum often conversion energy (26.61fJ).
Table 1 is the performance comparison figure that level translator is realized with other level translators in the present embodiment
It refer to implementation method schematic flow sheet the present embodiment that Fig. 8 is the present invention and additionally provide a kind of subthreshold value CMOS electricity
The implementation method of flat change-over circuit, comprises the following steps：
Step S1 configurations input buffer, the current mirror of backfeed loop, cross-coupled circuit and output buffer,
Phase inverters of the step S2 using the input buffer as low threshold voltage, the output warp of the cross-coupled circuit
Output buffer exports,
The current mirror of the backfeed loop is placed in prime by step S3, is connected with the cross-coupled circuit positioned at rear class,
Input voltage is promoted to NMOS in the cross-coupled circuit by step S4 by the current mirror of the backfeed loop
Threshold value on.
As preferred in the present embodiment, in step s3, the current mirror of the backfeed loop includes：First normality threshold
Voltage PMOS, the second regular threshold voltage PMOS, the first high threshold voltage PMOS,
The first regular threshold voltage PMOS and the second regular threshold voltage PMOS source electrode connect high supply voltage respectively,
The drain electrode of the first regular threshold voltage PMOS connects the source electrode of the first high threshold voltage PMOS,
Also include：First low threshold voltage NMOS, the second low threshold voltage NMOS,
The source ground of the first low threshold voltage NMOS, the drain electrode of the second regular threshold voltage PMOS connect described
Second low threshold voltage NMOS drain electrode, the source ground of the second low threshold voltage NMOS,
The first regular threshold voltage PMOS and the second regular threshold voltage PMOS grid are connecing described first just
Normal threshold voltage PMOS drain electrode, the grid of the first high threshold voltage PMOS connect the second regular threshold voltage PMOS's
Drain electrode；
Meanwhile the grid of the first low threshold voltage NMOS is connect into input as the first input end of the current mirror and delayed
One end of device is rushed,
The second input termination input buffer using the grid of the second low threshold voltage NMOS as the current mirror
The other end；
The first output end using the drain electrode of the first regular threshold voltage PMOS as the current mirror, by described second
Second output end of the regular threshold voltage PMOS drain electrode as the current mirror.
As preferred in the present embodiment, in step s3, the cross-coupled circuit includes：3rd low threshold voltage
NMOS, the 4th low threshold voltage NMOS, the 4th high threshold voltage PMOS and the 5th high threshold voltage PMOS,
The 4th high threshold voltage PMOS and the 5th high threshold voltage PMOS source electrode connects high supply voltage, described
4th high threshold voltage PMOS grid meets the drain electrode of the 5th high threshold voltage PMOS, the 5th high threshold voltage PMOS
Grid connect the 4th high threshold voltage PMOS drain electrode；The drain electrode of the 3rd low threshold voltage NMOS connects the 4th high threshold
Voltage PMOS drain electrode, the drain electrode of the 4th low threshold voltage NMOS connect the 5th high threshold voltage PMOS drain electrode, and described
Three low threshold voltage NMOS source electrode and the 4th low threshold voltage NMOS source ground；
The grid of the 3rd low threshold voltage NMOS is connect to the second output end of the current mirror of the backfeed loop,
The grid of the 4th low threshold voltage NMOS is connect to the second output end of the current mirror of the backfeed loop；
Output end using the drain electrode of the 5th high threshold voltage PMOS as the subthreshold value CMOS level shifting circuits.
It should be appreciated that each several part of the present invention can be realized with hardware, software, firmware or combinations thereof.Above-mentioned
In embodiment, software that multiple steps or method can be performed in memory and by suitable instruction execution system with storage
Or firmware is realized.If, and in another embodiment, can be with well known in the art for example, realized with hardware
Any one of row technology or their combination are realized：With the logic gates for realizing logic function to data-signal
Discrete logic, have suitable combinational logic gate circuit application specific integrated circuit, programmable gate array (PGA), scene
Programmable gate array (FPGA) etc..
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description
Point is contained at least one embodiment or example of the present invention.In this manual, to the schematic representation of above-mentioned term not
Necessarily refer to identical embodiment or example.Moreover, specific features, structure, material or the feature of description can be any
One or more embodiments or example in combine in an appropriate manner.
In general, the various embodiments of the disclosure can be with hardware or special circuit, software, logic or its any combination
Implement.Some aspects can be implemented with hardware, and some other aspect can be with firmware or software implementation, and the firmware or software can
With by controller, microprocessor or other computing devices.Although the various aspects of the disclosure be shown and described as block diagram,
Flow chart is represented using some other drawing, but it is understood that frame described herein, equipment, system, techniques or methods can
With in a non limiting manner with hardware, software, firmware, special circuit or logic, common hardware or controller or other calculating
Equipment or some combinations are implemented.
Although in addition, operation is described with particular order, this is understood not to require this generic operation with shown suitable
Sequence is performed or performed with generic sequence, or requires that all shown operations are performed to realize expected result.In some feelings
Under shape, multitask or parallel processing can be favourable.Similarly, begged for although the details of some specific implementations is superincumbent
By comprising but these are not necessarily to be construed as any restrictions to the scope of the present disclosure, but the description of feature is only pin in
To specific embodiment.Some features described in some embodiments of separation can also be held in combination in single embodiment
OK.Mutually oppose, the various features described in single embodiment can also in various embodiments be implemented separately or to appoint
The mode of what suitable sub-portfolio is implemented.
Claims (10)
- A kind of 1. subthreshold value CMOS level shifting circuits, it is characterised in that including：Input buffer, backfeed loop current mirror, Cross-coupled circuit and output buffer, phase inverter of the input buffer as low threshold voltage, the cross-couplings The output of circuit exports through output buffer,The current mirror of the backfeed loop is located at prime, is connected with the cross-coupled circuit positioned at rear class,Input voltage is promoted in the cross-coupled circuit on NMOS threshold value by the current mirror of the backfeed loop.
- 2. subthreshold value CMOS level shifting circuits according to claim 1, it is characterised in that the electric current of the backfeed loop Mirror includes：First regular threshold voltage PMOS, the second regular threshold voltage PMOS, the first high threshold voltage PMOS,The first regular threshold voltage PMOS and the second regular threshold voltage PMOS source electrode connect high supply voltage respectively,The drain electrode of the first regular threshold voltage PMOS connects the source electrode of the first high threshold voltage PMOS,Also include：First low threshold voltage NMOS, the second low threshold voltage NMOS,The source ground of the first low threshold voltage NMOS, the drain electrode of the second regular threshold voltage PMOS connect described second Low threshold voltage NMOS drain electrode, the source ground of the second low threshold voltage NMOS,The first regular threshold voltage PMOS and the second regular threshold voltage PMOS grid connect the described first normal threshold Threshold voltage PMOS drain electrode, the grid of the first high threshold voltage PMOS connect the leakage of the second regular threshold voltage PMOS Pole；Meanwhile the grid of the first low threshold voltage NMOS is connect into input buffer as the first input end of the current mirror One end,Using the grid of the second low threshold voltage NMOS as the another of the second input termination input buffer of the current mirror One end；The first output end using the drain electrode of the first regular threshold voltage PMOS as the current mirror is normal by described second Second output end of the threshold voltage PMOS drain electrode as the current mirror.
- 3. subthreshold value CMOS level shifting circuits according to claim 1, it is characterised in that the cross-coupled circuit bag Include：3rd low threshold voltage NMOS, the 4th low threshold voltage NMOS, the 4th high threshold voltage PMOS and the 5th high threshold voltage PMOS,The 4th high threshold voltage PMOS and the 5th high threshold voltage PMOS source electrode connects high supply voltage, and the described 4th High threshold voltage PMOS grid connects the drain electrode of the 5th high threshold voltage PMOS, the grid of the 5th high threshold voltage PMOS Pole connects the 4th high threshold voltage PMOS drain electrode；The drain electrode of the 3rd low threshold voltage NMOS connects the 4th high threshold voltage PMOS drain electrode, the drain electrode of the 4th low threshold voltage NMOS connect the 5th high threshold voltage PMOS drain electrode, and the described 3rd is low The source ground of threshold voltage NMOS source electrode and the 4th low threshold voltage NMOS；The grid of the 3rd low threshold voltage NMOS is connect to the second output end of the current mirror of the backfeed loop,The grid of the 4th low threshold voltage NMOS is connect to the second output end of the current mirror of the backfeed loop；Output end using the drain electrode of the 5th high threshold voltage PMOS as the subthreshold value CMOS level shifting circuits.
- 4. subthreshold value CMOS level shifting circuits according to claim 1, it is characterised in that in the electricity of the backfeed loop The first input end of stream mirror connects incoming level.
- 5. subthreshold value CMOS level shifting circuits according to claim 1, it is characterised in that in the electricity of the backfeed loop Second input termination incoming level of stream mirror is simultaneously exported by the input buffer.
- 6. subthreshold value CMOS level shifting circuits according to claim 1, it is characterised in that in the input buffer Power input terminates low suppling voltage.
- 7. subthreshold value CMOS level shifting circuits according to claim 1, it is characterised in that the output buffer is connected on The output end of sub-threshold level converter.
- 8. subthreshold value CMOS level shifting circuits according to claim 1, it is characterised in that the electricity of the output buffer Source input terminates high supply voltage.
- 9. subthreshold value CMOS level shifting circuits according to claim 1, it is characterised in that also include：Multi thresholds device MTCMOS, to reduce input delay.
- 10. a kind of implementation method of subthreshold value CMOS level shifting circuits, it is characterised in that comprise the following steps：Input buffer, the current mirror of backfeed loop, cross-coupled circuit and output buffer are configured,Phase inverter using the input buffer as low threshold voltage, the output of the cross-coupled circuit is through output buffer Output,The current mirror of the backfeed loop is placed in prime, is connected with the cross-coupled circuit positioned at rear class,Input voltage is promoted in the cross-coupled circuit on NMOS threshold value by the current mirror of the backfeed loop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710731861.0A CN107707246A (en) | 2017-08-23 | 2017-08-23 | The subthreshold value CMOS level shifting circuits and implementation method of internet of things oriented |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710731861.0A CN107707246A (en) | 2017-08-23 | 2017-08-23 | The subthreshold value CMOS level shifting circuits and implementation method of internet of things oriented |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107707246A true CN107707246A (en) | 2018-02-16 |
Family
ID=61169744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710731861.0A Pending CN107707246A (en) | 2017-08-23 | 2017-08-23 | The subthreshold value CMOS level shifting circuits and implementation method of internet of things oriented |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107707246A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110442884A (en) * | 2018-05-02 | 2019-11-12 | 中国科学院微电子研究所 | A kind of optimization method and device of subthreshold value digital timing circuit |
| CN111966158A (en) * | 2020-08-24 | 2020-11-20 | 中国电子科技集团公司第二十四研究所 | Complementary low-drift constant current source and control method thereof |
| US11409314B2 (en) | 2018-09-20 | 2022-08-09 | Canaan Creative Co., Ltd. | Full swing voltage conversion circuit and operation unit, chip, hash board, and computing device using same |
| CN115051701A (en) * | 2022-06-24 | 2022-09-13 | 深圳数马电子技术有限公司 | Level auxiliary conversion control circuit and level conversion circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1630193A (en) * | 2003-12-17 | 2005-06-22 | 三星电子株式会社 | Level shifter utilizing input controlled zero threshold blocking transistors |
| US7605609B1 (en) * | 2007-12-17 | 2009-10-20 | Lattice Semiconductor Corporation | Programmable level shifter |
| CN105958994A (en) * | 2016-04-25 | 2016-09-21 | 深圳大学 | Subthreshold level shifter having wide input voltage range |
-
2017
- 2017-08-23 CN CN201710731861.0A patent/CN107707246A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1630193A (en) * | 2003-12-17 | 2005-06-22 | 三星电子株式会社 | Level shifter utilizing input controlled zero threshold blocking transistors |
| US7605609B1 (en) * | 2007-12-17 | 2009-10-20 | Lattice Semiconductor Corporation | Programmable level shifter |
| CN105958994A (en) * | 2016-04-25 | 2016-09-21 | 深圳大学 | Subthreshold level shifter having wide input voltage range |
Non-Patent Citations (1)
| Title |
|---|
| YUAN CAO等: ""An Energy-Efficient Subthreshold Level Shifter with A Wide Input Voltage Range"", 《2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110442884A (en) * | 2018-05-02 | 2019-11-12 | 中国科学院微电子研究所 | A kind of optimization method and device of subthreshold value digital timing circuit |
| CN110442884B (en) * | 2018-05-02 | 2023-04-07 | 中国科学院微电子研究所 | Optimization method and device of sub-threshold digital sequential circuit |
| US11409314B2 (en) | 2018-09-20 | 2022-08-09 | Canaan Creative Co., Ltd. | Full swing voltage conversion circuit and operation unit, chip, hash board, and computing device using same |
| CN111966158A (en) * | 2020-08-24 | 2020-11-20 | 中国电子科技集团公司第二十四研究所 | Complementary low-drift constant current source and control method thereof |
| CN115051701A (en) * | 2022-06-24 | 2022-09-13 | 深圳数马电子技术有限公司 | Level auxiliary conversion control circuit and level conversion circuit |
| CN115051701B (en) * | 2022-06-24 | 2024-12-06 | 深圳数马电子技术有限公司 | Level auxiliary conversion control circuit and level conversion circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107707246A (en) | The subthreshold value CMOS level shifting circuits and implementation method of internet of things oriented | |
| US8207758B2 (en) | Ultra-low power multi-threshold asynchronous circuit design | |
| US10924118B1 (en) | Positive feedback XOR/XNOR gate and low-delay hybrid logic adder | |
| CN104124954A (en) | Level conversion circuit and operation method thereof | |
| KR19980069727A (en) | Storage Devices Using Charge Recycling Differential Logic (CRDL) Circuits | |
| US20230112781A1 (en) | Circuits and Methods to use energy harvested from transient on-chip data | |
| CN208985029U (en) | Voltage conversion circuit, data operation unit, chip, force calculation board and calculation equipment | |
| Kai et al. | Variable Body Biasing (VBB) based VLSI Design Approach to Reduce Static Power. | |
| Mahendran | CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications | |
| CN104836570A (en) | AND/XOR gate circuit based on transistor level | |
| CN102386908B (en) | Heat insulation domino circuit and heat insulation domino ternary AND gate circuit | |
| Sivakumar et al. | Recent trends in low power VLSI design | |
| Sandiri et al. | Design of noise immune subthreshold circuits using dynamic threshold Schmitt trigger logic | |
| Ho et al. | Energy-effective sub-threshold interconnect design using high-boosting predrivers | |
| CN106505995B (en) | A Single-Rail Current-Mode One-Bit Full Adder Based on FinFET Devices | |
| CN210120546U (en) | CMOS (complementary Metal oxide semiconductor) combinational logic circuit | |
| Bhaskar et al. | An Efficient PFSCL based D-Latch Design Using Dynamic-Threshold Voltage MOSFET | |
| Varma et al. | Sub Threshold Level Shifters and Level Shifter with LEC for LSI’s | |
| CN102427340B (en) | A Limiting Transformation Circuit Suitable for Subthreshold Region | |
| Kumar et al. | Design of High-speed Power efficient full adder with Body-biasing | |
| Rao et al. | DESIGN OF LOW VOLTAGE MODIFIED WILSON CURRENT MIRROR CIRCUITS BASED ENERGY EFFICIENT LEVEL SHIFTERS | |
| CN202435379U (en) | SET/MOS Hybrid Structure Multiplier Unit Based on Threshold Logic | |
| Dhanumjaya et al. | Low Power Standard Logic Gate Cells Design and its Power & Delay Analysis | |
| Rajeev et al. | VLSI Implementation of Level Shifter: A Review Paper | |
| JP3560849B2 (en) | Low power consumption type neuron MOS circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180216 |
|
| RJ01 | Rejection of invention patent application after publication |