CN107706196B - Array substrate and preparation method thereof, and display device - Google Patents
Array substrate and preparation method thereof, and display device Download PDFInfo
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- CN107706196B CN107706196B CN201710897693.2A CN201710897693A CN107706196B CN 107706196 B CN107706196 B CN 107706196B CN 201710897693 A CN201710897693 A CN 201710897693A CN 107706196 B CN107706196 B CN 107706196B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Abstract
本发明提供一种阵列基板及其制备方法、显示装置，涉及显示技术领域，可改善因信号线被腐蚀而导致的显示不良的问题。所述阵列基板包括衬底，还包括依次设置在所述衬底上的信号线、导电保护图案、至少一层绝缘层和透明导电图案，所述导电保护图案设置在所述信号线的表面，所述至少一层绝缘层上设置有过孔，所述透明导电图案通过所述过孔与所述信号线接触；所述过孔在所述衬底上的正投影落入所述导电保护图案在所述衬底上的正投影内，所述导电保护图案在所述衬底上的正投影落入所述信号线在所述衬底上的正投影内。
The invention provides an array substrate, a preparation method thereof, and a display device, which relate to the field of display technology and can improve the problem of poor display caused by corrosion of signal lines. The array substrate includes a substrate, and further includes a signal line, a conductive protection pattern, at least one insulating layer and a transparent conductive pattern sequentially arranged on the substrate, and the conductive protection pattern is arranged on the surface of the signal line, A via hole is provided on the at least one insulating layer, and the transparent conductive pattern is in contact with the signal line through the via hole; the orthographic projection of the via hole on the substrate falls into the conductive protection pattern In the orthographic projection on the substrate, the orthographic projection of the conductive protection pattern on the substrate falls within the orthographic projection of the signal line on the substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display device.
Background
A conventional display device includes an array substrate including signal lines disposed on a substrate, and an Integrated Circuit (IC) connected to the signal lines at a bonding region and outputting corresponding signals to the signal lines. Because the signal line and the IC are in different layers, when the signal line is connected with the IC, different transparent conductive patterns are usually connected with the signal line through the via holes to complete the switching of the signal line.
As shown in fig. 1(a), the signal line 20 is usually formed by sequentially forming an Nd (neodymium) alloy film layer and an Mo (molybdenum) film layer on the substrate 10, and when a via hole is formed by a dry etching process, a process gas is ionized, and a generated plasma has a strong bombardment effect on a metal material, so that a metal lattice state of metal Mo is damaged, and a hole is formed on the Mo metal layer 21. Since the transparent conductive pattern 30 is thin and has a non-dense structure, and the Nd alloy layer 22 is corroded at a very high speed, moisture in the environment easily passes through the holes in the Mo metal layer 21, and a large area of the Nd alloy layer 22 is corroded. As shown in fig. 1(b), after the Nd alloy layer 22 is extensively etched, the Mo metal layer 21 may be depressed downward at the etched portion of the Nd alloy layer 22, which may easily cause the Mo metal layer 21 to break; on the other hand, the Nd alloy layer 22 affects the Mo metal layer 21 during the etching process, and the Mo metal layer 21 is also etched to some extent, and finally the signal line 20 is broken, thereby causing display failure.
Disclosure of Invention
Embodiments of the present invention provide an array substrate, a method for manufacturing the same, and a display device, which can solve the problem of poor display caused by corrosion of signal lines.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, an array substrate is provided, which includes a substrate, and further includes a signal line, a conductive protection pattern, at least one insulating layer, and a transparent conductive pattern, which are sequentially disposed on the substrate, wherein the conductive protection pattern is disposed on a surface of the signal line, a via hole is disposed on the at least one insulating layer, and the transparent conductive pattern is in contact with the signal line through the via hole; the orthographic projection of the via hole on the substrate falls into the orthographic projection of the conductive protection pattern on the substrate, and the orthographic projection of the conductive protection pattern on the substrate falls into the orthographic projection of the signal line on the substrate.
Preferably, the signal line includes a gate line and a common electrode line; the conductive protection pattern comprises a first conductive protection pattern arranged on the surface of the grid line and a second conductive protection pattern arranged on the surface of the common electrode line.
Preferably, an orthographic projection of a channel region in a thin film transistor included in the array substrate on the substrate does not overlap with an orthographic projection of the conductive protection pattern on the substrate.
Preferably, the conductive protection pattern has a thickness of
Preferably, the conductive protection pattern is made of the same material as the transparent conductive pattern.
Preferably, the signal line includes an Nb alloy layer and an Mo metal layer sequentially disposed on the substrate.
In a second aspect, a method for manufacturing an array substrate is provided, including: forming a signal line and a conductive protection pattern on a substrate, wherein the orthographic projection of the conductive protection pattern on the substrate falls into the orthographic projection of the signal line on the substrate; forming at least one insulating layer on the substrate on which the conductive protection pattern is formed; a through hole is formed on the at least one insulating layer, and the orthographic projection of the through hole on the substrate falls into the orthographic projection of the conductive protection pattern on the substrate; and forming a transparent conductive pattern on the substrate on which the at least one insulating layer is formed, wherein the transparent conductive pattern is in contact with the signal line through the via hole.
Preferably, the method further comprises: forming a semiconductor layer on a substrate, the semiconductor layer including a channel region; an orthographic projection of the channel region on the substrate does not overlap with an orthographic projection of the conductive protection pattern on the substrate.
Optionally, the step of forming the signal line and the conductive protection pattern includes: sequentially forming a metal film and a conductive film on a substrate, and forming a photoresist covering the conductive film; exposing and developing the photoresist by adopting a semi-permeable mask plate to form a photoresist complete retaining area, a photoresist semi-retaining area and a photoresist complete removing area; etching the conductive film and the metal film corresponding to the photoresist complete removal area to form the signal line; ashing the photoresist in the photoresist semi-reserved area; etching the conductive film corresponding to the photoresist semi-reserved area to form the conductive protection pattern; stripping the photoresist corresponding to the photoresist complete reserve area;
optionally, the step of forming the signal line and the conductive protection pattern includes: forming a metal film on the substrate, and patterning to form the signal line; and forming a conductive thin film on the substrate on which the signal line is formed, and patterning to form the conductive protection pattern.
In a third aspect, a display device is provided, which includes the array substrate of the first aspect.
The embodiment of the invention provides an array substrate, a preparation method thereof and a display device, wherein a layer of conductive protection pattern is formed on the surface of a signal line, so that when a via hole for enabling a transparent conductive pattern to be in contact with the signal line is formed on an insulating layer in an etching mode, the conductive protection pattern can play a role in protecting the signal line, and etching process gas cannot influence the signal line below the via hole. The metal lattice state of the signal wire can not be damaged, so that water vapor can be prevented from entering the signal wire, the corrosion resistance of the signal wire can be improved, and poor display can be avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1(a) is a schematic structural diagram of an array substrate according to the prior art;
fig. 1(b) is a schematic structural diagram of an array substrate according to the prior art;
fig. 2 is a first schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a second schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 6 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 7(a) -fig. 7(f) are schematic views illustrating a manufacturing process of an array substrate according to an embodiment of the invention;
fig. 8 is a fifth schematic structural view of an array substrate according to an embodiment of the present invention.
Reference numerals
10-a substrate; 20-signal lines; a 21-Mo metal layer; a 22-Nd alloy layer; 23-a gate line; 24-a data line; 30-a transparent conductive pattern; 31-a first transparent conductive pattern; 32-a second transparent conductive pattern; 40-a conductive protection pattern; 41-a first conductive protection pattern; 42-a second conductive protection pattern; 51-a first insulating layer; 52-second insulating layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides an array substrate, as shown in fig. 2, including a substrate 10, a signal line 20, a conductive protection pattern 40, at least one insulating layer (illustrated by including a first insulating layer 51 in fig. 2, and illustrated by including a first insulating layer 51 and a second insulating layer 52 in fig. 3) and a transparent conductive pattern 30, which are sequentially disposed on the substrate 10, wherein the conductive protection pattern 40 is disposed on a surface of the signal line 20, at least one insulating layer is disposed with a via hole, and the transparent conductive pattern 30 is in contact with the signal line 20 through the via hole; the orthographic projection of the via hole on the substrate 10 falls within the orthographic projection of the conductive protection pattern 40 on the substrate 10, and the orthographic projection of the conductive protection pattern 40 on the substrate 10 falls within the orthographic projection of the signal line 20 on the substrate 10.
First, the signal line 20 is not limited, and may be any one of a gate line, a data line, and a common electrode line, for example.
Second, the conductive protection pattern 40 is used to prevent the signal line 20 from being damaged by the process gas during etching when the insulating layer is etched, and therefore, it is understood by those skilled in the art that the conductive protection pattern 40 preferably does not react with the process gas during etching, or reacts with the process gas during etching at a slow rate, or the conductive protection pattern 40 is thick enough.
The material of the conductive protection pattern 40 may be the same as or different from the material of the signal line 20.
Third, the orthographic projection of the conductive protection pattern 40 on the substrate 10 falls within the orthographic projection of the signal line 20 on the substrate 10, and thus, as for the shape of the conductive protection pattern 40, it may coincide with the pattern of the signal line 20 as shown in fig. 3; or may fall within the pattern of signal lines 20 as shown in figure 2.
Fourthly, the transparent conductive pattern 30 may be used to connect the signal line 20 with the IC, or when the signal line 20 overlaps with other wires and requires a jumper, the transparent conductive pattern 30 may be used to complete signal connection at the break of the signal line 20.
Fifth, as shown in fig. 2, when only the first insulating layer 51 is provided, the first insulating layer 51 is provided with a via hole so that the transparent conductive pattern 30 contacts the signal line 20; as shown in fig. 3, when there are multiple insulating layers, the via holes provided on each insulating layer correspond to each other to form a large via hole for allowing the transparent conductive pattern 30 to contact the signal line 20.
The orthographic projection of the via hole on the substrate 10 falls within the orthographic projection of the conductive protection pattern 40 on the substrate 10, and thus, as to the shape of the conductive protection pattern 40, it can coincide with the pattern of the via hole on the insulating layer for contacting the transparent conductive pattern 30 with the signal line 20; or a pattern of via holes on the insulating layer for contacting the transparent conductive pattern 30 with the signal line 20 falls within the pattern of the conductive protection pattern 40.
In the array substrate provided by the embodiment of the invention, a layer of conductive protection pattern 40 is formed on the surface of the signal line 20, so that when a via hole for contacting the transparent conductive pattern 30 with the signal line 20 is formed on the insulating layer by etching, the conductive protection pattern 40 can protect the signal line 20, and etching process gas cannot influence the signal line 20 below the via hole. The metal lattice state of the signal line 20 is not damaged, so that the entry of moisture into the signal line 20 can be prevented, and thus the corrosion resistance of the signal line 20 can be improved, and poor display can be prevented.
Preferably, the signal line 20 includes a gate line and a common electrode line; the conductive protection pattern 40 includes a first conductive protection pattern disposed on a surface of the gate line and a second conductive protection pattern disposed on a surface of the common electrode line.
Of course, the transparent conductive pattern 30 includes a first transparent conductive pattern in contact with the gate line and a second transparent conductive pattern in contact with the common electrode line.
Further preferably, the gate line and the common electrode line are disposed in the same layer, and the first conductive protection pattern and the second conductive protection pattern are disposed in the same layer.
Alternatively, as shown in fig. 4, the signal line 20 includes a gate line 23 and a data line 24, and an interlayer insulating layer is further disposed between the gate line 23 and the data line 24; the conductive protection pattern includes a first conductive protection pattern 41 disposed on a surface of the gate line 23 and a second conductive protection pattern 42 disposed on a surface of the data line 24; the transparent conductive pattern 30 includes a first transparent conductive pattern 31 contacting the gate line 23 and a second transparent conductive pattern 32 contacting the data line 24.
In order to avoid the influence of the conductive protection pattern 40 on the electron mobility of the channel region of the thin film transistor, and thus the performance of the thin film transistor, as shown in fig. 5, it is preferable that the orthographic projection of the channel region of the thin film transistor included in the array substrate on the substrate 10 does not overlap with the orthographic projection of the conductive protection pattern 40 on the substrate 10.
That is, the conductive protection pattern 40 does not overlap with the channel region of the thin film transistor on the premise that the above conditions are satisfied. That is, there is no conductive protection pattern 40 at the channel region position.
The channel region in the thin film transistor is the channel region in the semiconductor layer of the thin film transistor, and the channel region forms a channel after the thin film transistor is conducted.
In order to reduce the thickness of the array substrate as much as possible under the protection, it is preferable that the conductive protection pattern 40 has a thickness of
For example, the conductive protection pattern 40 may have a thickness of
Preferably, the material of the conductive protection pattern 40 is the same as that of the transparent conductive pattern 30.
For example, the material of the conductive protection pattern 40 and the transparent conductive pattern 30 may be ITO (Indium tin oxide).
The embodiment of the present invention provides that the material of the conductive protection pattern 40 is the same as the material of the transparent conductive pattern 30, so that the contact interface of the via hole is not increased, the transfer resistance of the via hole is not increased, and the signal Loading (Loading) is not affected.
In order to reduce the resistance of the signal line 20, it is preferable that the signal line 20 includes an Nb alloy layer and an Mo metal layer sequentially disposed on the substrate 10 according to an embodiment of the present invention.
The Nb alloy layer may be an AlNb (aluminum neodymium) alloy, for example.
An embodiment of the present invention further provides a method for manufacturing an array substrate, as shown in fig. 6, the method includes:
s10, forming the signal line 20 and the conductive protection pattern 40 on the substrate 10, wherein the orthographic projection of the conductive protection pattern 40 on the substrate 10 falls within the orthographic projection of the signal line 20 on the substrate 10.
S20, forming at least one insulating layer on the substrate on which the conductive protection pattern 40 is formed; at least one of the insulating layers has a via formed thereon, and an orthographic projection of the via on the substrate 10 falls within an orthographic projection of the conductive protection pattern 40 on the substrate 10.
S30, forming the transparent conductive pattern 30 on the substrate formed with the at least one insulating layer, the transparent conductive pattern 30 contacting the signal line 20 through the via hole.
In the array substrate provided by the embodiment of the invention, a layer of conductive protection pattern 40 is formed on the surface of the signal line 20, so that when a via hole for contacting the transparent conductive pattern 30 with the signal line 20 is formed on the insulating layer by etching, the conductive protection pattern 40 can protect the signal line 20, and etching process gas cannot influence the signal line 20 below the via hole. The metal lattice state of the signal line 20 is not damaged, so that the entry of moisture into the signal line 20 can be prevented, and thus the corrosion resistance of the signal line 20 can be improved, and poor display can be prevented.
Further preferably, the method further comprises forming a semiconductor layer on the substrate, the semiconductor layer comprising a channel region; an orthogonal projection of the channel region on the substrate 10 does not overlap an orthogonal projection of the conductive protection pattern 40 on the substrate 10.
By not overlapping the conductive protection pattern 40 with the channel region, it is possible to prevent the conductive protection pattern 40 from affecting electron mobility of the channel region of the thin film transistor, thereby affecting performance of the thin film transistor.
Optionally, step S10 specifically includes:
s11, as shown in fig. 7(a), a metal thin film and a conductive thin film are sequentially formed on the substrate 10, and a photoresist covering the conductive thin film is formed.
When the signal line 20 includes a plurality of metal layers, the metal thin film layers should be a plurality of layers.
S12, as shown in fig. 7(b), exposing and developing the photoresist by using the semi-transparent mask plate to form a photoresist complete-remaining region, a photoresist semi-remaining region, and a photoresist complete-removing region.
S13, as shown in fig. 7(c), the conductive film and the metal film corresponding to the completely removed photoresist region are etched to form the signal line 20.
S14, as shown in fig. 7(d), the photoresist in the photoresist half-retaining region is ashed.
S15, as shown in fig. 7(e), the conductive film corresponding to the photoresist half-reserved region is etched to form the conductive protection pattern 40.
S16, as shown in fig. 7(f), the photoresist corresponding to the photoresist complete remaining region is stripped.
That is, the signal line 20 and the conductive protection pattern 40 are formed through the same patterning process.
Optionally, step S10 specifically includes:
a metal thin film is formed on the substrate 10 and patterned to form the signal line 20.
A conductive thin film is formed on the substrate on which the signal line 20 is formed, and a conductive protection pattern 40 is patterned.
That is, the signal line 20 is formed through a single patterning process, and then the conductive protection pattern 40 is formed through a single patterning process.
As shown in fig. 8, the method further includes forming at least one insulating layer and a transparent conductive layer 30 and other film layers on the substrate on which the conductive protection pattern 40 is formed.
The embodiment of the invention also provides a display device which comprises the array substrate.
The display device may be a display panel or a display device including a display panel.
The display device can be any product or component with a display function, such as a liquid crystal display, an organic light-emitting diode display, a liquid crystal television, a digital photo frame, a mobile phone or a tablet computer and the like.
The display device provided by the embodiment of the invention has the same beneficial effects as the array substrate, and the description is omitted here.
When the Display device is a Liquid Crystal Display (LCD), it includes an array substrate, a pair of cell substrates, and a Liquid Crystal layer disposed therebetween. The array substrate comprises a thin film transistor and a pixel electrode electrically connected with a first drain electrode of the thin film transistor; further, a common electrode may be included. The opposite-box substrate can comprise a black matrix and a color film. Here, the color film may be disposed on the box alignment substrate or on the array substrate; the common electrode may be disposed on the array substrate or the pair of cell substrates.
When the display device is an Organic Light Emitting Diode (OLED) display, the display device includes an array substrate and a package substrate. The array substrate comprises a thin film transistor, an anode electrically connected with a first drain electrode of the thin film transistor, a cathode and an organic material functional layer positioned between the anode and the cathode.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (8)
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| CN110928085B (en) * | 2019-11-26 | 2021-01-15 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN113096849B (en) * | 2021-06-10 | 2021-09-24 | 苏州华星光电技术有限公司 | Conductive silver paste composite material, display device and preparation method thereof |
| CN114677949A (en) * | 2022-03-29 | 2022-06-28 | 京东方科技集团股份有限公司 | Display module, display device and working method thereof |
| CN118315394B (en) * | 2024-05-06 | 2024-08-16 | 惠科股份有限公司 | Array substrate and preparation method thereof, and display panel |
| CN118136636B (en) * | 2024-05-06 | 2024-08-02 | 惠科股份有限公司 | Array substrate and preparation method thereof, and display panel |
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| CN106910750A (en) * | 2017-04-24 | 2017-06-30 | 京东方科技集团股份有限公司 | A kind of preparation method of array base palte, display panel and array base palte |
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