CN107689219A - Gate driving circuit and its display device - Google Patents
Gate driving circuit and its display device Download PDFInfo
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- CN107689219A CN107689219A CN201710818797.XA CN201710818797A CN107689219A CN 107689219 A CN107689219 A CN 107689219A CN 201710818797 A CN201710818797 A CN 201710818797A CN 107689219 A CN107689219 A CN 107689219A
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- 230000005540 biological transmission Effects 0.000 description 3
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- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
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- 235000008434 ginseng Nutrition 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
This application discloses gate driving circuit and its display device.The gate driving circuit includes being respectively used to the multistage drive element of the grid for driving a corresponding gate line on display panel, there is compole at the both ends of every grade of drive element of the grid, drive element of the grid includes, pre-charge module, according to the first pulse signal, first clock signal provides the voltage of first node, the first transistor, first gate driving signal is produced according to the voltage of second clock signal and first node, pull down module, according to the second pulse signal, 3rd clock signal and the 4th clock signal produce pulldown signal, pulldown signal pulls down first gate driving signal the gate drive signal to form this grade of drive element of the grid output, stable module, the gate drive signal of first node and this grade of drive element of the grid output is maintained into low level.The present invention provides a kind of lossless input system, ensure that the transitivity of signal, saves the design that domain space ensures narrow frame.
Description
Technical field
The present invention relates to display technology field, more particularly, to gate driving circuit and its display device.
Background technology
Display device generally comprises display panel, gate driving circuit and source electrode drive circuit.Wherein, liquid crystal display panel
Basic functional principle with drive circuit is：Gate driving circuit with what gate line was electrically connected with by pulling up transistor to grid
Line sends out gate drive signal, sequentially opens the TFT of every a line, then by source electrode drive circuit simultaneously by the pixel of a full line
Unit is charged to each required voltage, to show different GTGs.It is passed through by the gate driving circuit of the first row first
Pull up transistor the volume thin film switch pipe opening of the first row, then the pixel cell of the first row is carried out by source electrode drive circuit
Charging.When the pixel cell of the first row is charged, gate driving circuit closes the row thin film transistor (TFT), then the grid of the second row
Pole drive circuit is pulled up transistor by it and opens the thin film transistor (TFT) of the second row, then by source electrode drive circuit to the second row
Pixel cell carries out discharge and recharge.So sequentially go down, when the pixel cell of last column of substituting the bad for the good, just again since the first row
Charging.
Existing gate driving circuit, the grid of input transistors typically can be by gate output signal or clock signal control
System, its current potential only up to reach VGH, it is impossible to the current potential for transmitting signal is charged into ideal height, opened by VGH control gates brilliant
Body pipe, which carries out signal input, signal is lost, and be unfavorable for signal stable delivery.
Fig. 1 shows the electrical block diagram of n-th grade of drive element of the grid in the gate driving circuit of prior art.Grid
Driver element includes pre-charge circuit 101, bootstrapping pull-up circuit 102, pull-down circuit 103 and low level holding circuit 104.Enter
One step, pre-charge circuit 101 includes first switch pipe T1；Pull-up circuit 102 of booting includes second switch pipe T2, the first electric capacity
C1；Pull-down circuit 103 includes the 3rd switch transistor T 3, the 6th switch transistor T 6 and the 7th switch transistor T 7；Low level holding circuit includes
Second electric capacity C2, the 4th switch transistor T 4 and the 5th switch transistor T 5.When drive element of the grid receives the first clock signal clk 1, second
Clock signal CLK2, upwards difference one-level gate drive signal Gn-1, downwards difference one-level gate drive signal Gn+1 and
Low suppling voltage VGL, produce this grade of gate drive signal Gn.When the Gn-1 output high level of difference one-level upwards, T1 conductings,
First node Q1 is filled with high level.When first node Q1 voltage be more than T2 threshold voltage when T2 open, pull-up the stage by
In the first electric capacity C1 boot strap so that second switch pipe T2 is opened, and reaches the high level needed for grid output line.When downward
When differing the Gn+1 output high level of one-level, pull-down circuit drags down the point position of output point.The low level maintenance stage is when first
When clock signal CLK1 is by low uprise, the noise current potential of section point Q2 points is set to be higher than Q points under the second electric capacity C2 coupling,
Because the effect of checking and balance of the 4th switch transistor T 4 and the 5th switch transistor T 5 makes the current potential of Q points stable in VGL.
Therefore, it is necessary to improved technical scheme is provided to overcome above technical problem present in prior art.
The content of the invention
The main technical problem to be solved in the present invention is to provide a kind of signal lossless input system, and loss can be controlled to ensure
The transitivity of signal, the design that domain space ensures narrow frame can be saved again.
According to an aspect of the present invention, there is provided a kind of gate driving circuit, including be respectively used to drive on display panel
A corresponding gate line multistage drive element of the grid, there are compole, the grid in the both ends of every grade of drive element of the grid
Driver element includes：Input module, for providing the electricity of the first node according to the first pulse signal, the first clock signal
Pressure.Output module, for producing first gate driving signal according to the voltage of the second clock signal and the first node.
Module is pulled down, is believed for producing the first drop-down according to second pulse signal, the 3rd clock signal and the 4th clock signal
Number and the second pulldown signal, first pulldown signal and second pulldown signal first gate driving signal is pulled down
Form the gate drive signal of this grade of drive element of the grid output.Stable module, for by the first node and described level
The gate drive signal of drive element of the grid output maintains low level.
Preferably, the head and end of every grade of drive element of the grid has two-stage compole, and the compole is first
Buffering signals and the second buffering signals provide high voltage, and the output signal of the compole is not exported to display panel.
Preferably, the input module includes first switch pipe, described in the first control terminal of the first switch pipe receives
First buffering signals, the first path terminal receive first clock signal.
Preferably, the output module includes second switch pipe and the first electric capacity, and the second control terminal of second switch pipe connects
The alternate path end of first switch pipe is connect, the third path end of second switch pipe receives second clock signal, second switch pipe
Fourth passage exports the gate drive signal of described level drive element of the grid, the first electric capacity C1 first ends connection second switch pipe
The second control terminal, first electric capacity for the second switch pipe fourth passage end and the second control terminal between parasitism electricity
Hold.
Preferably, the drop-down module includes the 3rd switching tube, the 4th switching tube and the 6th switching tube, the 3rd switching tube
3rd control terminal receives the second buffering signals, and the fifth passage end of the 3rd switching tube connects the alternate path end of first switch pipe,
6th path terminal of the 3rd switching tube receives the 3rd clock signal, and the 4th control terminal of the 4th switching tube receives the 4th clock letter
Number, the fourth passage end of the 7th path terminal connection second switch pipe of the 4th switching tube, the 8th path termination of the 4th switching tube
Receive low voltage signal, the 6th control terminal of the 6th switching tube connects the 9th path terminal of the 5th switching tube, and the of the 6th switching tube
12 path terminals connect the 14th path terminal of the 7th switching tube.
Preferably, the stable module includes the 5th switching tube, the 7th switching tube, the 8th switching tube and the 9th switch
Pipe, the alternate path end of the 9th path terminal connection first switch pipe of the 5th switching tube, the tenth path terminal of the 5th switching tube connect
The 12nd path terminal of the 6th switching tube is connect, the 7th control terminal of the 7th switching tube connects the 5th control terminal of the 5th switching tube,
Tenth threeway terminal of the 7th switching tube connects the second end of the first electric capacity, the 14th path terminal connection the 4th of the 7th switching tube
8th path terminal of switching tube, the 8th control terminal reception second clock signal of the 8th switching tube, the 15th of the 8th switching tube the
Path terminal connects the 8th control terminal of the 8th switching tube, and the 9th control terminal of the 9th switching tube connects the 16th of the 8th switching tube the
Path terminal, the 15th path terminal of the 17th path terminal the 8th switching tube of connection of the 9th switching tube, the tenth of the 9th switching tube the
Eight path terminals connect the 11st path terminal of the 6th switching tube.
The first node is the alternate path end of first switch pipe, the second control terminal of second switch pipe, the 3rd switch
The fifth passage end of pipe and the common port of the 9th path terminal of the 5th switching tube.
Preferably, first clock signal, the second clock signal, the 3rd clock signal and the described 4th
The cycle of clock signal is equal, and first clock signal, the second clock signal, the 3rd clock signal and
The dutycycle of 4th clock signal is 50%.
Preferably, first clock signal, the second clock signal, the 3rd clock signal and the described 4th
Clock signal becomes from low level successively turns to high level, and first clock signal, the second clock signal, the described 3rd
Clock signal and the 4th clock signal become the interval time for turning to high level as a quarter cycle by low level.
According to another aspect of the present invention ,-kind of display device is also provided, it includes any raster data model as described above
Circuit, the gate driving circuit are used to export the pixel cell on gate drive signal driving display panel.
Compared to prior art, control signal high voltage as caused by compole of input of the present invention provides, in realization
Between repeat unit lossless input.And the output signal of compole is not exported to display panel, such lossless input electricity
Road greatly reduces the chip area of input switch pipe, and its input signal obtained can reach with reference to high voltage, than traditional
The minimum high threshold voltage of input signal, and the rise time of input signal is reduced, ensure to transmit the integrality of signal.
Brief description of the drawings
By the description to the embodiment of the present invention referring to the drawings, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 shows the electrical block diagram of n-th grade of drive element of the grid in the gate driving circuit of prior art.
Fig. 2 shows the electrical block diagram of the gate driving circuit of the embodiment of the present invention.
Fig. 3 shows the time diagram during gate driving circuit work of the embodiment of the present invention.
Fig. 4 shows the structural representation frame of n-th grade of drive element of the grid in the full level gate driving circuit of the embodiment of the present invention
Figure.
Fig. 5 shows the simulation result comparison of wave shape figure of the gate driving circuit of the embodiment of the present invention and prior art.
Fig. 6 show in the case of 27 DEG C the gate driving circuit of the present invention and prior art in precharge input phase and
The T-V curves in pull-up stage.
Fig. 7 shows that the gate driving circuit of the present invention and prior art is bent in the T-V in drop-down stage in the case of 27 DEG C
Line.
Embodiment
The present invention is more fully described hereinafter with reference to accompanying drawing.In various figures, identical element is using similar attached
Icon is remembered to represent.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.Furthermore, it is possible to it is not shown some
Known part.
It describe hereinafter many specific details of the present invention, such as the structure of device, material, size, processing work
Skill and technology, to be more clearly understood that the present invention.But just as the skilled person will understand, it can not press
The present invention is realized according to these specific details.
The present invention can be presented in a variety of manners, some of embodiments explained below.
Fig. 2 shows the electrical block diagram of the gate driving circuit of the embodiment of the present invention.Gate driving circuit includes the
One to the 9th switching tube.First switch pipe Tl includes the first path terminal, alternate path end and the first control terminal, second switch pipe T2
Including third path end, fourth passage end and the second control terminal, the 3rd switch transistor T 3 include fifth passage end, the 6th path terminal and
3rd control terminal, the 4th switch transistor T 4 include the 7th path terminal, the 8th path terminal and the 4th control terminal, and the 5th switch transistor T 5 includes
9th path terminal, the tenth path terminal and the 5th control terminal, the 6th switch transistor T 6 include the 11st path terminal, the 12nd path terminal and
6th control terminal, the 7th switch transistor T 7 include the tenth threeway terminal, the 14th path terminal and the 7th control terminal, the 8th switch transistor T 8
Including the 15th path terminal, the 16th path terminal and the 8th control terminal, the 9th switch transistor T 9 includes the 17th path terminal, the 18th
Path terminal and the 9th control terminal.
Gate driving circuit includes input module 201, output module 202, drop-down module 203, stable module 204.Wherein,
Input module 201 includes first switch pipe T1, and first switch pipe T1 the first control terminal receives the compole of difference level Four upwards
Caused high voltage Q (n-4), the first path terminal receive the first clock signal clk 1.Output module 202 includes second switch pipe
T2, the first electric capacity C1, second switch pipe T2 the second control terminal via node Q connection first switch pipes T1 alternate path end,
Third path end receives second clock signal CLK2, and fourth passage end exports the gate drive signal of n-th grade of drive element of the grid
Gn, the first electric capacity C1 first ends connect the second control terminal.Pull down module 203 and include the 3rd switch transistor T 3, the 4th switch transistor T 4, the
Six switch transistor Ts 6, the 3rd control terminal of the 3rd switch transistor T 3 receive high voltage Q (n+ caused by the compole of difference level Four downwards
4), the alternate path end of fifth passage end connection first switch pipe, the 6th path terminal receive the 3rd clock signal clk 3, and the 4th opens
The 4th control terminal for closing pipe T4 receives the 4th clock signal clk 4, and the 7th path terminal connects the fourth passage end of second switch pipe,
8th path terminal receives low reference voltage VGL, and the 6th control terminal of the 6th switch transistor T 6 is via node Q connection first switch pipes
Alternate path end, the 12nd path terminal receive low reference voltage VGL.Stable module 204 switchs comprising the 5th switch transistor T the 5, the 7th
Pipe T7, the 8th switch transistor T 8, the 9th switch transistor T 9, wherein, the 9th switch transistor T 9 and the 8th switch transistor T 8 form the first stable list
Member, the 5th switch transistor T 5 and the 7th switch transistor T 7 form the second stable unit.The 9th path terminal connection the of 5th switch transistor T 5
The alternate path end of one switching tube, the tenth path terminal receive low reference voltage VGL, the 7th control terminal connection of the 7th switch transistor T 7
5th control terminal of the 5th switching tube, the tenth threeway terminal connect the first electric capacity C1 the second end, and the 14th path terminal receives ginseng
Low-voltage VGL is examined, the 8th control terminal of the 8th switch transistor T 8 receives second clock signal CLK2, the 15th path terminal connection the 8th
Control terminal, the 9th control terminal of the 9th switch transistor T 9 connect the 16th path terminal of the 8th switching tube, the connection of the 17th path terminal
15th path terminal of the 8th switching tube, the 18th path terminal via the switching tube of node QB connections the 6th the 11st path terminal.
Wherein, first switch pipe Tl alternate path end, second switch pipe T2 the second control terminal, the of the 3rd switching tube
Five path terminals, the common port of the 9th path terminal of the 5th switch transistor T 5 are designated as node Q, the 5th control terminal of the 5th switch transistor T 5,
The 11st path terminal, the 7th control terminal of the 7th switch transistor T 7 and the 18th path of the 9th switch transistor T 9 of 6th switch transistor T 6
The common port at end is designated as node QB.
Wherein, the first electric capacity Cl is the parasitic capacitance between second switch pipe T2 fourth passage end and the second control terminal.
Certainly it will be appreciated by those skilled in the art that, can second switch pipe T2 the second control terminal and fourth passage end it
Between storage capacitance is set, now, the first electric capacity C1 be second switch pipe T2 fourth passage end and the second control terminal between posting
Raw electric capacity and separate storage electric capacity sum.
In the present embodiment, first to the 9th switch transistor T l~T9 is N-type transistor.First control terminal to the 9th control terminal
For the grid of transistor.The odd channel end of first to the 9th switching tube is the drain of transistor, the first to the 9th switching tube
Even channel end be transistor source class.Certainly, it will be appreciated by persons skilled in the art that the first to the 9th switching tube
Tl~T9 can also use other switch elements to realize, such as P-type transistor, and the odd channel end of each transistor and
Even channel end can exchange (i.e. drain and source electrode can exchange).The using first to the 9th switching tube is as N-type transistor below
Example come specifically introduce the present invention embodiment and its operation principle.But the present invention be practiced without limitation to this.
Fig. 3 is the time diagram of gate driving circuit as shown in Figure 2, with reference to Fig. 2, Fig. 3, in the present invention, first
It is AC signal to the 4th clock signal, wherein the first clock signal clk 1 and second clock signal CLK2, the 3rd clock are believed
The cycle of number CLK3 and the 4th clock signal clk 4 is equal, and first clock signal clk 1 and second clock signal
CLK2, the 3rd clock signal clk 3 and the 4th clock signal clk 4 dutycycle are 50%.In n-th grade of drive element of the grid
In GIA [n] course of work, first clock signal clk 1 and second clock signal CLK2, the 3rd clock signal clk 3 and the
Four clock signal clks 4 become from low level successively turns to high level, and first clock signal clk 1 and second clock signal
CLK2, the 3rd clock signal clk 3 and the 4th clock signal clk 4 become from low level turn to the time interval of high level into four/
A cycle.Certainly, it will be appreciated by those skilled in the art that, the present invention is not limited thereto.
The course of work in gate driving circuit per one-level drive element of the grid be divided into pre-charging stage, the pull-up stage, under
4 stages of drawing stage and stabilization sub stage.
In pre-charging stage P1, first switch pipe Tl the first control terminal is received caused by the compole of difference level Four upwards
High voltage Q (n-4), first switch pipe Tl are turned on, and the first clock signal clk 1 is low level, and the voltage at node Q passes through conducting
First switch pipe Tl be pulled low, now the electric charge at node Q is cleared, when second clock signal CLK2 is changed into high from low level
During level, the 8th switch transistor T 8 and the 9th switch transistor T 9 are both turned on, and node QB is driven high by the 9th switch transistor T 9 of conducting, the
Seven switch transistor Ts 7 are turned on, and this grade of gate drive signal Gn is pulled low by the 7th switch transistor T 7 of conducting；When the first clock signal
When CLK1 is changed into high level from low level, the voltage at node Q is by the first switch pipe T1 of conducting by the first clock signal
CLK1 is pre-charged, second switch pipe T2 conductings；Because the voltage at node Q is precharged, the 6th switch transistor T 6 turns on, node QB
The voltage at place is pulled low to low reference voltage VGL by the 6th switch transistor T 6 of conducting, so that the 5th switch transistor T 5 is closed,
To stop the drop-down to node Q.
Pull-up stage P2, when second clock signal CLK2 level is by low uprise, due in pre-charging stage node Q
Through being precharged, therefore, second switch pipe T2 conductings, due to second switch pipe T2 conducting, and the first electric capacity C1 bootstrapping is made
With the voltage at node Q is further pulled up, and voltage is further pulled up at node Q so that second switch pipe T2 is fully led
It is logical, further such that this grade of gate drive signal Gn of the output end output of this grade of drive element of the grid opens by the second of conducting
Pipe T2 is closed to be drawn high by second clock signal CLK2.
Low level is changed into from high level in drop-down stage P3, second clock signal CLK2, the voltage at pull-up stage node Q
Be further pulled up, second switch pipe T2 conductings, this grade of gate drive signal Gn drawn by the second switch pipe T2 of conducting
It is low, meanwhile, the 4th clock signal clk 4 is changed into high level from low level, and the 4th switch transistor T 4 is both turned on, this grade of raster data model letter
Number Gn is pulled to low reference voltage VGL, the quilt of the 6th switch transistor T 6 that node QB passes through conducting by the 4th switch transistor T 4 of conducting
Drag down.Further, since the compole of difference level Four is changed into high level in the voltage Q (n+4) of Q points from low level downwards, the 3rd opens
Close pipe T3 to turn on, therefore when the 3rd clock signal clk 3 is changed into low level from high level, node Q passes through the 3rd switch of conducting
Pipe T3 is pulled low, and second Katyuan part M2 is closed.
In stabilization sub stage P4, because the voltage at the drop-down stage, node Q is pulled low, therefore, second switch pipe T2 is closed
Close, avoid influences of the second clock signal CLK2 to this grade of gate drive signal Gn, while the 6th switch transistor T 6 is closed, and is stopped
Drop-down to node QB.Because second clock signal CLK2 is clock signal, within the follow-up time (i.e. the stabilization sub stage it
Pulse can be also ceaselessly produced afterwards), it will this grade of gate drive signal Gn of this grade of drive element of the grid output is had an impact,
In order to eliminate these influences, the embodiment of the present invention utilizes the 9th switch transistor T 9, the 8th switch transistor T 8, the 5th switch transistor T 5 and the 7th
Switch transistor T 7 is improved.
It can be seen that, input loss 301 and drop-down loss 302 are all 0 in Fig. 3.In pre-charging stage, the Q of n-4 levels is utilized
Point high voltage control input switch transistor T 1, coordinates n-2 levels signal to complete the transmission of input signal.In the drop-down stage, drop-down
Switch transistor T 3 coordinates the Q point high voltages of n+4 levels and n+2 level grids low level signal to complete drive element of the grid and transmit under signal
Draw.It can be seen that the switch tube grid in input and drop-down stage is all operated under Q point high potentials, the lossless defeated of signal is completed
Enter, lossless drop-down.
Fig. 4 shows the structural representation frame of n-th grade of drive element of the grid of the full level gate driving circuit of the embodiment of the present invention
Figure.The full level gate driving circuit of the present invention includes multistage drive element of the grid as shown in Figure 4, the drive element of the grid
The first and last end of gate driving circuit 401 respectively have a two-stage compole, the compole includes the first compole 502, the second compole
503rd, the 3rd compole 504 and the 4th compole 505.The gate output signal of first to fourth compole do not export to
Display panel, and control signal of the Q point high voltages as drive element of the grid input in gate driving circuit is merely creating, from
And realize the lossless input of middle drive element of the grid.N-th grade of drive element of the grid is used to export gate drive signal Gn, with area
Corresponding gate line that Qu Dong be on display panel.Based on the design that gate driving circuit head and end is full symmetric, match somebody with somebody
The change of clock is closed, this circuit can realize positive and negative sweep.
Further, because the gate driving circuit of first order drive element of the grid is without the auxiliary for differing level Four upwards
Level, the gate driving circuit of level drive element of the grid last is without the compole for differing level Four downwards.So first order grid
The first pulse signal that pole driver element receives by the first order drive element of the grid the first compole and the second compole
There is provided, the second pulse signal that level drive element of the grid last receives is by the of the level drive element of the grid last
Three compoles and the 4th compole provide.In addition, the first pulse signal of drive element of the grid is difference level Four upwards
The high voltage Q (n-4) of compole output, the high voltage Q (n+ that the second pulse signal exports for the compole of difference level Four downwards
4)。
Fig. 5 shows the simulation result comparison of wave shape figure of the gate driving circuit of the embodiment of the present invention and prior art.In figure
Waveform describes the potential change for transmitting signal Q points, and solid line represents that the present embodiment transmits the change waveform of signal Q point current potentials, empty
Line represents the potential change waveform of the transmission signal Q points of the gate driving circuit of prior art.The raster data model electricity of the present embodiment
The input thin film transistor (TFT) breadth length ratio of road and prior art circuits is respectively 100um/4um, 500um/4um, electric in the prior art
The chip area on road is 4 times or so of new-type circuit.As can be seen that in input phase, the gate driving circuit of the present embodiment
Transmit signal and Vgh=15V is increased to by Vgl=-11V quickly, and traditional circuit then needs longer time to be increased to Vgh-Vth
=11V or so.And it can be improved to 36V via capacitance coupling effect in bootstrapping output stage, the Q point current potentials of the present embodiment circuit
More than, and the circuit of prior art can only achieve 33V, it is more abundant that higher Q point current potentials can open output transistor T2,
Output signal Gn rise time and fall time is shortened, makes circuit that there is advantage in terms of high-resolution high capacity is tackled.
Fig. 6 show in the case of 27 DEG C the gate driving circuit of the present invention and prior art in precharge input phase and
The T-V curves in pull-up stage.Fig. 7 shows that the gate driving circuit of the present invention and prior art is in drop-down rank in the case of 27 DEG C
The T-V curves of section.601 are being pre-charged for clock signal, input signal and Q point voltages in the gate driving circuit of prior art
Input phase and pull-up the stage T-V curves, 602 for the present embodiment gate driving circuit in clock signal, input signal with
And Q point voltages are when precharge input phase and the T-V curves in pull-up stage, 701 are in the gate driving circuit of prior art
Clock signal, input signal and Q point voltages drop-down the stage T-V curves, 702 for the present embodiment gate driving circuit in when
The T-V curves of clock signal, input signal and Q point voltages in the drop-down stage.As can be seen that the present invention is implemented from Fig. 6, Fig. 7
The input signal of example gate driving circuit is lossless in precharge input phase, pull-up stage and the transmission of drop-down stage, and existing
The input signal of technology gate driving circuit about reaches Q in precharge input phase, pull-up stage and drop-down stage slippages
The half of point ceiling voltage.Using the gate driving circuit of the present invention, visual resolution is different from panel size, and input is with
Saving for the domain space of drag switch pipe can be that 40~100um border width is saved in the design of narrow frame gate driving circuit
Take.And lossless signal transmission can ensure output transistor T2 fan-out capability with higher Q point current potentials, ensure output energy
T2 chip area is reduced on the premise of power, certain frame can also be equally saved and take.
The embodiment of the present invention also provides-kind of display device, including above-mentioned gate driving circuit, the gate driving circuit
For exporting the pixel cell on gate drive signal driving display panel.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation make a distinction with another entity or operation, and not necessarily require or imply and deposited between these entities or operation
In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Nonexcludability includes, so that process, method, article or equipment including a series of elements not only will including those
Element, but also the other element including being not expressly set out, or it is this process, method, article or equipment also to include
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Other identical element also be present in process, method, article or equipment including the key element.
According to embodiments of the invention as described above, these embodiments do not have all details of detailed descriptionthe, not yet
It is only described specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
Book is chosen and specifically describes these embodiments, is in order to preferably explain the principle and practical application of the present invention, so that affiliated
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its four corner and equivalent.
Claims (10)
1. a kind of gate driving circuit, it is characterised in that including being respectively used to drive a corresponding grid on display panel
There is compole at the multistage drive element of the grid of line, the both ends of every grade of drive element of the grid, and the drive element of the grid includes：
Pre-charge module, for providing the voltage of the first node according to the first pulse signal, the first clock signal；And
The first transistor, for producing first grid driving letter according to the voltage of the second clock signal and the first node
Number；And
Module is pulled down, is believed for producing the first drop-down according to the second pulse signal, the 3rd clock signal and the 4th clock signal
Number and the second pulldown signal, first pulldown signal and second pulldown signal first gate driving signal is pulled down
Form the gate drive signal of this grade of drive element of the grid output；And
Stable module, for the gate drive signal of the first node and described level drive element of the grid output to be maintained
Low level.
2. gate driving circuit according to claim 1, it is characterised in that the first and last two of every grade of drive element of the grid
Respectively there is two-stage compole at end, and the compole provides high voltage, the compole for the first buffering signals and the second buffering signals
Output signal do not export to display panel.
3. gate driving circuit according to claim 2, it is characterised in that the input module includes first switch pipe,
First control terminal of the first switch pipe receives first buffering signals, and the first path terminal receives the first clock letter
Number.
4. gate driving circuit according to claim 1 or 2, it is characterised in that the output module includes second switch
Pipe and the first electric capacity, the alternate path end of the second control terminal connection first switch pipe of second switch pipe, the of second switch pipe
Three-way end receives second clock signal, and the fourth passage of second switch pipe exports the grid drive of described level drive element of the grid
Dynamic signal, the second control terminal of the first end connection second switch pipe of the first electric capacity, first electric capacity is the second switch
Parasitic capacitance between the fourth passage end of pipe and the second control terminal.
5. gate driving circuit according to claim 1 or 2, it is characterised in that the drop-down module includes the 3rd switch
Pipe, the 4th switching tube and the 6th switching tube, the 3rd control terminal of the 3rd switching tube receive the second buffering signals, the 3rd switching tube
Fifth passage end connects the alternate path end of first switch pipe, and the 6th path terminal of the 3rd switching tube receives the 3rd clock signal,
4th control terminal of the 4th switching tube receives the 4th clock signal, the 7th path terminal connection second switch pipe of the 4th switching tube
Fourth passage end, the 8th path terminal of the 4th switching tube receive low voltage signal, the 6th control terminal connection of the 6th switching tube the
The alternate path end of one switching tube, the 12nd path terminal of the 6th switching tube receive low voltage signal.
6. gate driving circuit according to claim 1 or 2, it is characterised in that the stable module includes the 5th switch
Pipe, the 7th switching tube, the 8th switching tube and the 9th switching tube, the 9th path terminal connection first switch pipe of the 5th switching tube
Alternate path end, the tenth path terminal of the 5th switching tube receive low voltage signal, the 7th control terminal connection of the 7th switching tube the
5th control terminal of five switching tubes, the tenth threeway terminal of the 7th switching tube connect the second end of the first electric capacity, the 7th switching tube
The 14th path terminal receive low voltage signal, the 8th control terminal of the 8th switching tube receives second clock signal, the 8th switch
15th path terminal of pipe connects the 8th control terminal of the 8th switching tube, the switch of the 9th control terminal connection the 8th of the 9th switching tube
16th path terminal of pipe, the 17th path terminal of the 9th switching tube connect the 15th path terminal of the 8th switching tube, and the 9th opens
The 18th path terminal for closing pipe connects the 11st path terminal of the 6th switching tube.
7. gate driving circuit according to claim 1, it is characterised in that the first node is the of first switch pipe
Two path terminals, the second control terminal of second switch pipe, the fifth passage end of the 3rd switching tube and the 9th path of the 5th switching tube
The common port at end.
8. gate driving circuit according to claim 1, it is characterised in that first clock signal, it is described second when
The cycle of clock signal, the 3rd clock signal and the 4th clock signal is equal, and first clock signal, institute
The dutycycle for stating second clock signal, the 3rd clock signal and the 4th clock signal is 50%.
9. gate driving circuit according to claim 8, it is characterised in that first clock signal, it is described second when
Clock signal, the 3rd clock signal and the 4th clock signal become from low level successively turns to high level, and described the
One clock signal, the second clock signal, the 3rd clock signal and the 4th clock signal are changed by low level
Interval time for high level is a quarter cycle.
10. a kind of display device, it is characterised in that it includes any gate driving circuit as described in claim 1 to 9.
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|---|---|---|---|
| CN201710818797.XA CN107689219A (en) | 2017-09-12 | 2017-09-12 | Gate driving circuit and its display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710818797.XA CN107689219A (en) | 2017-09-12 | 2017-09-12 | Gate driving circuit and its display device |
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| CN201710818797.XA Pending CN107689219A (en) | 2017-09-12 | 2017-09-12 | Gate driving circuit and its display device |
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| CN110503927A (en) * | 2018-05-16 | 2019-11-26 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN113314067A (en) * | 2021-06-08 | 2021-08-27 | 武汉华星光电技术有限公司 | Grid driving circuit and display panel |
| CN113741726A (en) * | 2021-07-30 | 2021-12-03 | 惠科股份有限公司 | Drive circuit, four-stage drive circuit and display panel |
| CN113781950A (en) * | 2021-10-09 | 2021-12-10 | 福建华佳彩有限公司 | Novel grid driving circuit and driving method |
| CN114999384A (en) * | 2018-07-31 | 2022-09-02 | 乐金显示有限公司 | Gate driver and electroluminescent display device using gate driver |
| CN115691393A (en) * | 2022-11-14 | 2023-02-03 | 惠科股份有限公司 | Gate drive circuit and display device |
| CN115862541A (en) * | 2022-12-19 | 2023-03-28 | 义乌清越光电技术研究院有限公司 | Shift register, grid drive circuit and passive matrix organic light-emitting display panel |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant after: InfoVision Optoelectronics(Kunshan)Co.,Ltd. Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Applicant before: INFOVISION OPTOELECTRONICS (KUNSHAN) Co.,Ltd. |
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Application publication date: 20180213 |