CN107682126A - A kind of ethernet network transmission performance test device - Google Patents
A kind of ethernet network transmission performance test device Download PDFInfo
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Abstract
本发明公开了一种以太网网络传输性能测试装置，属于网络通信测试领域，包括发送与接收两部分；发送部分主要由测试帧数据存贮电路、帧间隔控制电路、突发控制电路、时间控制电路、发送状态机、时标序号插入电路、校验插入电路与输出电路组成；接收部分主要由输入电路、测试帧识别电路、错误检验电路、发送时标提取电路、接收时标锁存电路、序号提取电路、测试帧统计电路、伪随机序列提取电路、复位时间测试电路、时延测试电路、恢复时间测试电路、丢包率测试电路、吞吐量测试电路、误码测试电路与测试结果存储器组成。本发明可一次完成全部性能参数的测试，提高测试效率，缩短测试时间。
The invention discloses an Ethernet network transmission performance testing device, which belongs to the field of network communication testing and includes two parts: sending and receiving; the sending part is mainly composed of a test frame data storage circuit, a frame interval control circuit, a burst control circuit, and a time control circuit. circuit, sending state machine, time stamp serial number insertion circuit, check insertion circuit and output circuit; the receiving part is mainly composed of input circuit, test frame recognition circuit, error checking circuit, sending time stamp extraction circuit, receiving time stamp latch circuit, Serial number extraction circuit, test frame statistics circuit, pseudo-random sequence extraction circuit, reset time test circuit, delay test circuit, recovery time test circuit, packet loss rate test circuit, throughput test circuit, bit error test circuit and test result memory . The invention can complete the test of all performance parameters at one time, improves the test efficiency and shortens the test time.
Description
技术领域technical field
本发明属于网络通信测试领域，具体涉及一种以太网网络传输性能测试装置。The invention belongs to the field of network communication testing, in particular to an Ethernet network transmission performance testing device.
背景技术Background technique
网络技术得到广泛应用，速率越来越高传输速率。对网络通信设备测试需求很高。如何模拟实际网络的数据发生是网络传输测试的关键技术之一。现在一般的以太网测试中都是分别编辑一种静态数据帧，进行单一参数测试，并且各厂家的测试帧不兼容，不能相互进行测试。Network technology is widely used, and the transmission rate is getting higher and higher. There is a high demand for network communication equipment testing. How to simulate the data generation of the actual network is one of the key technologies of network transmission testing. In the general Ethernet test now, one kind of static data frame is edited separately, and a single parameter test is performed, and the test frames of various manufacturers are not compatible, so they cannot be tested with each other.
发明内容Contents of the invention
针对现有技术中存在的上述技术问题，本发明提出了一种以太网网络传输性能测试装置，编辑一种测试帧，可一次完成所有网络传输性能参数的测试。设计合理，克服了现有技术的不足，提高了测试效率，具有良好的应用效果。Aiming at the above-mentioned technical problems existing in the prior art, the present invention proposes an Ethernet network transmission performance test device, which can complete the test of all network transmission performance parameters at one time by editing a test frame. The design is reasonable, the deficiency of the prior art is overcome, the test efficiency is improved, and the application effect is good.
为了实现上述目的，本发明采用如下技术方案：In order to achieve the above object, the present invention adopts the following technical solutions:
一种以太网网络传输性能测试装置，首先定义以太网测试帧的格式：A kind of Ethernet network transmission performance testing device, at first defines the format of Ethernet test frame:
编辑一个或多个测试帧，每个测试帧包括源MAC地址、目的MAC地址、源IP地址、目的IP地址、测试帧标志、测试数据与时间标记；其中，测试帧中源MAC地址、目的MAC地址、源IP地址、目的IP地址根据测试场景确定；测试帧中的测试帧长度值根据用户设定的帧长而定，测试帧长度值＝帧长-46字节；测试帧中的测试数据由用户设定，测试数据长度＝测试帧长度值-12字节；测试帧中的伪随机序列是连续的；测试帧中的时间标记通过FPGA电路自动生成并在发送时合成到测试帧中去；Edit one or more test frames, each test frame includes source MAC address, destination MAC address, source IP address, destination IP address, test frame flag, test data and time stamp; among them, the source MAC address, destination MAC The address, source IP address, and destination IP address are determined according to the test scene; the test frame length value in the test frame is determined according to the frame length set by the user, and the test frame length value = frame length - 46 bytes; the test data in the test frame Set by the user, test data length = test frame length value - 12 bytes; the pseudo-random sequence in the test frame is continuous; the time stamp in the test frame is automatically generated by the FPGA circuit and synthesized into the test frame when sending ;
以太网网络传输性能测试装置，具体包括发送部分与接收部分；An Ethernet network transmission performance testing device, specifically including a sending part and a receiving part;
发送部分，被配置为用于完成构造测试帧并将测试帧发送出去；主要由测试帧数据存贮电路、帧间隔控制电路、突发控制电路、时间控制电路、地址控制电路、发送状态机电路、时标序号插入电路、发送序号与时标发生电路、发送时标锁存电路、校验插入电路与输出电路组成；The sending part is configured to complete the construction of the test frame and send the test frame; it mainly consists of a test frame data storage circuit, a frame interval control circuit, a burst control circuit, a time control circuit, an address control circuit, and a sending state machine circuit , Time stamp sequence number insertion circuit, transmission sequence number and time stamp generation circuit, transmission time stamp latch circuit, check insertion circuit and output circuit;
测试帧数据存贮电路，被配置为用于存贮测试帧定义的帧数据；A test frame data storage circuit configured to store frame data defined by the test frame;
帧间隔控制电路，被配置为用于控制每帧之间的间隔时间长短；A frame interval control circuit configured to control the interval time between each frame;
突发控制电路，被配置为用于控制连续发送帧的数量；a burst control circuit configured to control the number of consecutively transmitted frames;
时间控制电路，被配置为用于控制测试帧的发送持续时间；a time control circuit configured to control the transmission duration of the test frame;
地址控制电路，被配置为用于进行多端口的RFC2544测试，自动将测试帧需要到达端口的MAC目的地址、IP目的地址以及通道识别号插入到测试帧中；The address control circuit is configured to be used for multi-port RFC2544 test, and automatically inserts the MAC destination address, IP destination address and channel identification number of the port that the test frame needs to reach into the test frame;
发送状态机电路，被配置为用于生成测试帧；sending state machine circuitry configured to generate test frames;
时标序号插入电路，被配置为用于将当前发送帧的序号和时标插入到当前发送的帧中；A time stamp sequence number insertion circuit configured to insert the sequence number and time stamp of the currently transmitted frame into the currently transmitted frame;
发送序号与时标发生电路，用于产生发送序号与时间标记，利用时标序号插入电路插入到发送帧中；The transmission sequence number and time stamp generation circuit is used to generate the transmission sequence number and time stamp, and insert the time stamp sequence number into the transmission frame by using the time stamp sequence number insertion circuit;
发送时标锁存电路，被配置为用于测试系统恢复时间，当按过载速率发送完测试周期时锁存最后一个时标，然后按正常速率重新发送测试帧，并持续一个测试周期时间与门限时间之和；Transmit time stamp latch circuit, configured to test system recovery time, latches the last time stamp when the test cycle is sent at the overload rate, and then resends the test frame at the normal rate for a test cycle time and threshold the sum of time;
校验插入电路，被配置为用于将计算得出的CRC32校验值插入帧的最后四个字节位置；A check insertion circuit configured to insert the calculated CRC32 check value into the last four byte positions of the frame;
输出电路被配置为用于将整个测试帧发送出去；the output circuit is configured to send out the entire test frame;
接收部分，被配置为用于完成测试帧的接收、识别以及各参数的测量；主要由输入电路、测试帧识别电路、测试帧错误检测电路、发送时标提取电路、接收时标锁存电路、序号提取电路、测试帧统计电路、伪随机序列提取电路、复位时间测试电路、时延测试电路、恢复时间测试电路、丢包率测试电路、吞吐量测试电路、误码测试电路与测试结果存储器组成；The receiving part is configured to complete the receiving and identification of test frames and the measurement of various parameters; it mainly consists of an input circuit, a test frame identification circuit, a test frame error detection circuit, a transmission time stamp extraction circuit, a reception time stamp latch circuit, Serial number extraction circuit, test frame statistics circuit, pseudo-random sequence extraction circuit, reset time test circuit, delay test circuit, recovery time test circuit, packet loss rate test circuit, throughput test circuit, bit error test circuit and test result memory ;
输入电路，被配置为用于接收处理到达本端口的以太网帧，包括测试帧和非测试帧；The input circuit is configured to receive and process Ethernet frames arriving at the port, including test frames and non-test frames;
测试帧识别电路，被配置为用于持续检测测试帧标记，并将其后长度字节锁存到一个RAM中，并在帧结束时判断实际检测的测试帧长度是否与锁存的长度一致；The test frame identification circuit is configured to continuously detect the test frame mark, and latch the length byte thereafter into a RAM, and judge whether the actual detected test frame length is consistent with the latched length at the end of the frame;
测试帧错误检测电路，被配置为用于对识别出的测试帧进行错误检测，主要检测测试帧校验是否正确，若不正确，直接舍弃，不再进行下面的操作；The test frame error detection circuit is configured to perform error detection on the identified test frame, mainly to detect whether the test frame check is correct, if not, discard it directly, and do not perform the following operations;
发送时标提取电路，被配置为用于提取有效时标测试帧中的发送时标；A transmission time stamp extraction circuit configured to extract the transmission time stamp in the valid time stamp test frame;
接收时标锁存电路，被配置为用于锁存所有测试帧的到达时刻；A receiving time stamp latch circuit configured to latch the arrival moments of all test frames;
序号提取电路，被配置为用于将测试帧中的发送序号提取出来；A sequence number extraction circuit configured to extract the transmission sequence number in the test frame;
测试帧统计电路，被配置为用于统计所有有效的时标测试帧的个数，用于计算平均间隔时间(间隔时间＝本帧到达时间-上帧到达时间)，即抖动值；The test frame statistics circuit is configured to count the number of all effective time scale test frames, and is used to calculate the average interval time (interval time=the arrival time of this frame-the arrival time of the last frame), that is, the jitter value;
伪随机序列提取电路，被配置为用于被配置为用于从接收到的测试帧中剥离出伪随机序列数据，送到误码测试电路进行误码测试；The pseudo-random sequence extraction circuit is configured to be configured to strip the pseudo-random sequence data from the received test frame, and send it to the error testing circuit for bit error testing;
复位时间测试电路，被配置为用于连续锁存两个相邻的丢失帧到达时刻，其差值即为系统恢复时间；The reset time test circuit is configured to continuously latch the arrival time of two adjacent lost frames, and the difference thereof is the system recovery time;
时延测试电路，被配置为用于连续不断的统计所有时延测试帧的延迟时间，并锁存最大延迟时间和最小延迟时间；The delay test circuit is configured to continuously count the delay times of all delay test frames, and latch the maximum delay time and the minimum delay time;
恢复时间测试电路，被配置为用于锁存帧丢失后超过时间门限时到达的时延测试帧的时刻，将该时刻与发送方锁存的发送时标相减，即可得到系统恢复时间；The recovery time test circuit is configured to latch the moment of the delay test frame arriving when the time threshold is exceeded after the frame is lost, and subtract this moment from the transmission time stamp latched by the sender to obtain the system recovery time;
丢包率测试电路，被配置为用于统计测试开始后接收到的测试帧数量，并与发送的帧数据进行比较，计算出丢包率；The packet loss rate test circuit is configured to count the number of test frames received after the test starts, and compare it with the sent frame data to calculate the packet loss rate;
吞吐量测试电路，被配置为用于统计测试开始后，单位时间内接收到的最大测试帧数量，并与发送的帧数据进行比较，计算出吞吐量；The throughput test circuit is configured to count the maximum number of test frames received per unit time after the start of the test, and compare it with the sent frame data to calculate the throughput;
误码测试电路，被配置为用于将从测试帧中分享出的伪随机序列与接收端产生的伪随机序列进行比特同步，检测出错误，计算出误码率；The bit error testing circuit is configured to perform bit synchronization between the pseudo-random sequence shared from the test frame and the pseudo-random sequence generated by the receiving end, detect errors, and calculate the bit error rate;
测试结果存储器，被配置为用于存储全部测试结果。The test result memory is configured to store all test results.
本发明所带来的有益技术效果：Beneficial technical effects brought by the present invention:
(1)定义适用于全部参数测试的测试帧格式，减少测试帧的种类，有利用编程使用，减小编程工作量，提高效率。(1) Define the test frame format applicable to all parameter tests, reduce the types of test frames, use programming, reduce programming workload, and improve efficiency.
(2)可一次性完成网络传输性能的全部参数测试，缩短测试时间；(2) All parameter tests of network transmission performance can be completed at one time, shortening the test time;
(3)适用于10Gbps速率以下的以太网传输性能测试；(3) Suitable for Ethernet transmission performance test below 10Gbps rate;
附图说明Description of drawings
图1为测试帧定义格式示意图。Fig. 1 is a schematic diagram of a test frame definition format.
图2为本发明发送部分的原理框图。Fig. 2 is a functional block diagram of the sending part of the present invention.
图3为本发明接收部分的原理框图。Fig. 3 is a functional block diagram of the receiving part of the present invention.
具体实施方式detailed description
下面结合附图以及具体实施方式对本发明作进一步详细说明：Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:
本发明提出了一种以太网网络传输性能测试装置，编辑一种测试帧，可一次完成所有网络传输性能参数的测试。The invention provides an Ethernet network transmission performance test device, which can complete the test of all network transmission performance parameters at one time by editing a test frame.
如图1所示，本发明定义了一种以太网测试帧。测试包括了源MAC地址(6字节)、目的MAC地址(6字节)、类型(2字节)、IP头部(20字节)、UDP头部(8字节)、测试数据部分(N字节)与CRC检验(4字节)。其中的源MAC地址、目的MAC地址、源IP地址、目的IP地址均可预置一个固定值，若测试需要，可由图2所示的硬件电路自动生成动态地址。CRC检验由图2所示的硬件电路自动生成。As shown in Fig. 1, the present invention defines an Ethernet test frame. The test includes source MAC address (6 bytes), destination MAC address (6 bytes), type (2 bytes), IP header (20 bytes), UDP header (8 bytes), test data part ( N bytes) and CRC check (4 bytes). The source MAC address, destination MAC address, source IP address, and destination IP address can be preset with a fixed value. If the test requires, a dynamic address can be automatically generated by the hardware circuit shown in Figure 2. CRC check is automatically generated by the hardware circuit shown in Figure 2.
测试数据部分由测试帧ID(4字节)、测试帧长度(2字节)、测试数据(N-12字节)与时间标记(6字节)组成。测试帧ID是固定为一字符，测试帧长度值依据测试数据部分长度决定。时间标记由图2所示的硬件电路自动生成。测试数据部分由图2所示的硬件电路自动生成，为设定的某一种伪随机序列(如2n-1序列,n＝11,13,15,17,20,23,31)中的一部分。每一帧中的这一数据连接起来就是一个完整的伪随机序列。The test data part is composed of test frame ID (4 bytes), test frame length (2 bytes), test data (N-12 bytes) and time stamp (6 bytes). The test frame ID is fixed as one character, and the test frame length value is determined according to the length of the test data part. The time stamp is automatically generated by the hardware circuit shown in Figure 2. The test data part is automatically generated by the hardware circuit shown in Figure 2, which is a set of a pseudo-random sequence (such as 2 n -1 sequence, n = 11, 13, 15, 17, 20, 23, 31) part. This data in each frame is concatenated to form a complete pseudo-random sequence.
使用图1所示测试帧格式为每个发送端口设置一个或多个测试帧。每个测试帧数据写入发送电路的帧数据存贮器。每一帧最大长度为16384字节。Set up one or more test frames for each transmit port using the test frame format shown in Figure 1. Each test frame data is written into the frame data memory of the sending circuit. The maximum length of each frame is 16384 bytes.
如图2所示，发送部分主要由测试帧数据存贮电路、帧间隔控制电路、突发控制电路、时间控制电路、地址控制电路、发送状态机电路、时标序号插入电路、发送时标锁存电路、校验插入电路与输出电路组成。As shown in Figure 2, the sending part is mainly composed of a test frame data storage circuit, a frame interval control circuit, a burst control circuit, a time control circuit, an address control circuit, a sending state machine circuit, a time stamp serial number insertion circuit, and a sending time stamp lock It is composed of a storage circuit, a check insertion circuit and an output circuit.
测试帧定义的帧数据写入测试帧数据存储器；按照帧间隔控制电路和突发控制电路产生的定时生成测试帧；测试帧的发送持续时间由时间控制电路实现；地址控制电路用于多端口的RFC2544测试，它自动将测试帧需要到达端口的MAC目的地址、IP目的地址以及通道识别号插入到测试帧中；发送状态机电路根据这些信息生成测试帧；时标与序号插入电路将当前发送帧的序号和时标插入到当前发送的帧中；标记控制电路用于测试时延，当测试帧发送一半时，需要插入一个时延测试标记，用于接收部分识别提取发送时标；发送时标锁存电路用于测试系统恢复时间，当按过载速率发送完测试周期时锁存最后一个时标，然后按正常速率重新发送测试帧，并持续一个测试周期时间与门限时间之和；最后校验插入电路将计算得出的CRC32校验值插入帧的最后四个字节位置，输出电路将整个测试帧发送出去。The frame data defined by the test frame is written into the test frame data memory; the test frame is generated according to the timing generated by the frame interval control circuit and the burst control circuit; the transmission duration of the test frame is realized by the time control circuit; the address control circuit is used for multi-port RFC2544 test, it automatically inserts the MAC destination address, IP destination address and channel identification number of the test frame that needs to reach the port into the test frame; the sending state machine circuit generates the test frame according to these information; the time stamp and sequence number insertion circuit inserts the current sending frame The serial number and time stamp of the frame are inserted into the currently sent frame; the mark control circuit is used to test the delay. When the test frame is halfway sent, a delay test mark needs to be inserted for the receiving part to identify and extract the send time mark; the send time mark The latch circuit is used to test the recovery time of the system. When the test cycle is sent at the overload rate, the last time mark is latched, and then the test frame is resent at the normal rate, and lasts for a sum of the test cycle time and the threshold time; the final check The insertion circuit inserts the calculated CRC32 check value into the last four byte positions of the frame, and the output circuit sends out the entire test frame.
如图3所示，接收部分，被配置为用于完成测试帧的接收、识别以及各参数的测量；主要由输入电路、测试帧识别电路、测试帧错误检测电路、发送时标提取电路、接收时标锁存电路、序号提取电路、测试帧统计电路、伪随机序列提取电路、复位时间测试电路、时延测试电路、恢复时间测试电路、丢包率测试电路、吞吐量测试电路、误码测试电路与测试结果存储器组成。As shown in Figure 3, the receiving part is configured to complete the receiving and identification of test frames and the measurement of various parameters; it mainly consists of an input circuit, a test frame identification circuit, a test frame error detection circuit, a transmission time stamp extraction circuit, a receiving Time scale latch circuit, serial number extraction circuit, test frame statistics circuit, pseudo-random sequence extraction circuit, reset time test circuit, delay test circuit, recovery time test circuit, packet loss rate test circuit, throughput test circuit, bit error test It is composed of circuit and test result memory.
接收端的输入电路接收处理到达本端口的以太网帧，包括测试帧和非测试帧。测试帧识别电路，持续检测测试帧标记，并将其后长度字节锁存到一个RAM中，并在帧结束时判断实际检测的测试帧长度是否与锁存的长度一致。本设计支持测试帧的嵌套，并总是启用最后一个有效的测试帧。测试帧错误检测电路对识别出的测试帧进行错误检测，主要检测测试帧校验是否正确，若不正确，直接舍弃，不再进行下面的操作。The input circuit of the receiving end receives and processes the Ethernet frames arriving at the port, including test frames and non-test frames. The test frame identification circuit continuously detects the test frame mark, and latches the subsequent length byte into a RAM, and judges whether the actually detected test frame length is consistent with the latched length at the end of the frame. This design supports nesting of test frames and always enables the last valid test frame. The test frame error detection circuit performs error detection on the identified test frame, mainly to detect whether the test frame check is correct, if not, discard it directly, and do not perform the following operations.
输入电路，被配置为用于接收处理到达本端口的以太网帧，包括测试帧和非测试帧；The input circuit is configured to receive and process Ethernet frames arriving at the port, including test frames and non-test frames;
测试帧识别电路，被配置为用于持续检测测试帧标记，并将其后长度字节锁存到一个RAM中，并在帧结束时判断实际检测的测试帧长度是否与锁存的长度一致；The test frame identification circuit is configured to continuously detect the test frame mark, and latch the length byte thereafter into a RAM, and judge whether the actual detected test frame length is consistent with the latched length at the end of the frame;
测试帧错误检测电路，被配置为用于对识别出的测试帧进行错误检测，主要检测测试帧校验是否正确，若不正确，直接舍弃，不再进行下面的操作；The test frame error detection circuit is configured to perform error detection on the identified test frame, mainly to detect whether the test frame check is correct, if not, discard it directly, and do not perform the following operations;
发送时标提取电路，被配置为用于提取有效时标测试帧中的发送时标；A transmission time stamp extraction circuit configured to extract the transmission time stamp in the valid time stamp test frame;
接收时标锁存电路，被配置为用于锁存所有测试帧的到达时刻；A receiving time stamp latch circuit configured to latch the arrival moments of all test frames;
序号提取电路，被配置为用于将测试帧中的发送序号提取出来；A sequence number extraction circuit configured to extract the transmission sequence number in the test frame;
测试帧统计电路，被配置为用于统计所有有效的时标测试帧的个数，用于计算平均间隔时间(间隔时间＝本帧到达时间-上帧到达时间)，即抖动值；The test frame statistics circuit is configured to count the number of all effective time scale test frames, and is used to calculate the average interval time (interval time=the arrival time of this frame-the arrival time of the last frame), that is, the jitter value;
伪随机序列提取电路，被配置为用于被配置为用于从接收到的测试帧中剥离出伪随机序列数据，送到误码测试电路进行误码测试；The pseudo-random sequence extraction circuit is configured to be configured to strip the pseudo-random sequence data from the received test frame, and send it to the error testing circuit for bit error testing;
复位时间测试电路，被配置为用于连续锁存两个相邻的丢失帧到达时刻，其差值即为系统恢复时间；The reset time test circuit is configured to continuously latch the arrival time of two adjacent lost frames, and the difference thereof is the system recovery time;
时延测试电路，被配置为用于连续不断的统计所有时延测试帧的延迟时间，并锁存最大延迟时间和最小延迟时间；The delay test circuit is configured to continuously count the delay times of all delay test frames, and latch the maximum delay time and the minimum delay time;
恢复时间测试电路，被配置为用于锁存帧丢失后超过时间门限时到达的时延测试帧的时刻，将该时刻与发送方锁存的发送时标相减，即可得到系统恢复时间；The recovery time test circuit is configured to latch the moment of the delay test frame arriving when the time threshold is exceeded after the frame is lost, and subtract this moment from the transmission time stamp latched by the sender to obtain the system recovery time;
丢包率测试电路，被配置为用于统计测试开始后接收到的测试帧数量，并与发送的帧数据进行比较，计算出丢包率；The packet loss rate test circuit is configured to count the number of test frames received after the test starts, and compare it with the sent frame data to calculate the packet loss rate;
吞吐量测试电路，被配置为用于统计测试开始后，单位时间内接收到的最大测试帧数量，并与发送的帧数据进行比较，计算出吞吐量；The throughput test circuit is configured to count the maximum number of test frames received per unit time after the start of the test, and compare it with the sent frame data to calculate the throughput;
误码测试电路，被配置为用于将从测试帧中分享出的伪随机序列与接收端产生的伪随机序列进行比特同步，检测出错误，计算出误码率；The bit error testing circuit is configured to perform bit synchronization between the pseudo-random sequence shared from the test frame and the pseudo-random sequence generated by the receiving end, detect errors, and calculate the bit error rate;
测试结果存储器，被配置为用于存储全部测试结果，并定时通过数据总线送往主机，形成测试报告或测试曲线图。The test result memory is configured to store all the test results and send them to the host through the data bus at regular intervals to form a test report or a test curve.
当然，上述说明并非是对本发明的限制，本发明也并不仅限于上述举例，本技术领域的技术人员在本发明的实质范围内所做出的变化、改型、添加或替换，也应属于本发明的保护范围。Of course, the above descriptions are not intended to limit the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or replacements made by those skilled in the art within the scope of the present invention shall also belong to the present invention. protection scope of the invention.
Claims (1)
- A kind of 1. ethernet network transmission performance test device, it is characterised in that：The form of ethernet test frame is defined first：One or more test frames are edited, each test frame includes source MAC, target MAC (Media Access Control) address, source IP address, purpose IP Address, test flag of frame, test data and time mark；Wherein, source MAC, target MAC (Media Access Control) address, source IP in test frame Location, purpose IP address determine according to test scene；Depending on the frame length that test frame length value in test frame is set according to user, survey Try frame length angle value=byte of frame length -46；Test data in test frame is set by the user, test data length=test frame length It is worth -12 bytes；Pseudo-random sequence in test frame is continuous；Time mark in test frame is automatically generated by FPGA circuitry And it is synthesized to when sending in test frame；Ethernet network transmission performance test device, specifically includes transmitting portion and receiving portion；Transmitting portion, it is configurable for completing construction test frame and sends test frame；Mainly deposited by test frame data Store circuit, frame period control circuit, burst control circuitry, time control circuit, address control circuit, send state machine circuit, Markers sequence number insertion circuit, sending sequence number occurs circuit with markers, sends markers latch cicuit, verification insertion circuit and output electricity Road forms；Test frame data-storing circuit, it is configurable for the frame data of storage test frame definition；Frame period control circuit, it is configurable for controlling the interval time length between every frame；Burst control circuitry, it is configurable for the quantity that control continuously transmits frame；Time control circuit, it is configurable for controlling the sending duration of test frame；Address control circuit, is configurable for carrying out the RFC2544 tests of multiport, automatically needs test frame to reach port MAC destination addresses, IP destination addresses and channel recognition number be inserted into test frame；State machine circuit is sent, is configurable for generating test frame；Markers sequence number inserts circuit, is configurable for for the sequence number of currently transmitted frame and markers being inserted into currently transmitted frame In；Send sequence number and circuit occurs with markers, marked for producing to send sequence number with the time, inserted using markers sequence number insertion circuit Enter into transmission frame；Send markers latch cicuit, be configurable for test system recovery time, when by overload speed sent test period Last markers of Shi Suocun, then resends test frame by normal speed, and continues time test period and thresholding Time sum；Verification insertion circuit, it is configurable for last four byte locations of CRC32 check values insertion frame that will be calculated；Output circuit is configurable for sending whole test frame；Receiving portion, it is configurable for completing reception, identification and the measurement of each parameter of test frame；Mainly by input electricity Road, test frame identification circuit, test Framing Error Detection circuit, transmission markers extraction circuit, reception markers latch cicuit, sequence number carry When sense circuit, test frame statistical circuit, pseudo-random sequence extraction circuit, resetting time test circuit, delay testing circuit, recovery Between test circuit, packet loss test circuit, testing throughput circuit, error code testing circuit and test result memory form；Input circuit, it is configurable for the ethernet frame that reception processing reaches the port, including test frame and non-test frame；Test frame identification circuit, it is configurable for continuing detection test frame flag, and one will be latched into by length byte thereafter In RAM, and judge whether actually detected test frame length is consistent with the length of latch in frame end；Framing Error Detection circuit is tested, is configurable for carrying out error detection to the test frame identified, predominantly detects test Whether frame check is correct, if incorrect, directly gives up, and no longer carries out following operation；Markers extraction circuit is sent, is configurable for extracting the transmission markers in effective markers test frame；Markers latch cicuit is received, is configurable for latching the due in of all test frames；Sequence number extracts circuit, is configurable for extracting sending sequence number in test frame；Test frame statistical circuit, it is configurable for counting the number of all effective markers test frames, between calculating averagely Every time, i.e. jitter value；Pseudo-random sequence extracts circuit, is configurable for separating pseudorandom from the test frame received Sequence data, it is sent to error code testing circuit and carries out error code testing；Resetting time test circuit, it is configurable for continuously latching two adjacent lost frames due ins, its difference is System recovery time；Delay testing circuit, it is configurable for continuously counting the time delay of all delay testing frames, and latches most Big time delay and minimum delay time；Recovery time test circuit, it is configurable for latching the delay testing frame that is reached after LOF when exceeding time threshold At the moment, the transmission markers that the moment latches with sender is subtracted each other, you can obtain system recovery time；Packet loss test circuit, is configurable for the test number of frames received after statistical test starts, and with the frame of transmission Data are compared, and calculate packet loss；Testing throughput circuit, it is configurable for after statistical test starts, the full test frame number received in the unit interval Amount, and compared with the frame data of transmission, calculate handling capacity；Error code testing circuit, be configurable for from test frame sharing puppet caused by the pseudo-random sequence and receiving terminal with Machine sequence carries out bit synchronous, and detection makes mistake, and calculates the bit error rate；Test result memory, it is configurable for storing whole test results.
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