CN107665924A - A kind of mesolow groove type MOS device and preparation method thereof - Google Patents

Abstract

The present invention relates to the field of semiconductor manufacturing technology, in particular to a medium and low voltage trench type MOS device and its preparation method. By using the trench structure as the terminal junction of the device, the working area and protective ring mask in the traditional process are omitted. These two photolithographic mask plates; and the contact hole mask plate is used to form the source area of the device, so the source area mask plate in the traditional process is saved, so only the trench mask plate and the contact hole mask plate are needed Medium and low voltage trench MOS devices can be prepared by using three photolithographic masks and a metal mask. Due to the reduction in the number of photolithographic plates, the process steps for device production are reduced, thereby greatly reducing the cost of medium and low voltage trench MOS devices. The production cost of the device, thereby enhancing the competitiveness of the product.

Description

A medium and low voltage trench MOS device and its preparation method

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a medium and low voltage trench MOSFET device and a preparation method thereof.

Background technique

Medium and low voltage trench MOS (MOSFET) devices (Trench MOS) have important applications in network communication, computer and consumer fields and industrial control fields due to their high reliability, low on-resistance and high power and high current processing capabilities; For example, it is widely used in the fields of lithium battery protection modules, LED displays, LCD monitors, notebook power supplies and mobile phone power management, so the current research on this device has been very in-depth, and the design and manufacturing process of this device has been very mature. .

At present, in the traditional manufacturing process of low-voltage trench field effect transistors, a 6-layer mask is generally used to realize the manufacture of the device, which are the working area, the guard ring, the trench, the source area, the contact hole and the metal mask. board, which requires a higher cost. With the increasing integration of semiconductor devices, it is very necessary to reduce the manufacturing cost of a single chip.

Chinese patent (publication number: CN101866923A) discloses a three-layer photomask trench N-type MOS device and its manufacturing method. With different opening sizes, by depositing a dielectric layer with good step coverage ability, the gate trench notch and the gate contact trench notch have different shapes, and then undergo a dry etching process, and then assist a photolithography process, It can be achieved to retain the dielectric layer in the required area. The remaining dielectric layer can replace the photoresist mask and be used as a mask for N+ source ion implantation and a mask for P-type well ion implantation. It can also be used from aligned source contact holes and self-aligned gate contact hole. Therefore, trench MOSFET devices can be fabricated with only three layers of photomasks. Therefore, while the manufacturing process is simple and the cost is low, a higher unit cell density, that is, better performance can be achieved.

Although the above-mentioned method of using a three-layer photomask (ie, a photolithography mask) to realize a trench type MOS device is provided, this manufacturing method is aimed at a device whose gate trench width is smaller than the gate contact trench width. , is not universal.

Therefore, how to find a general method of using as few photolithography masks as possible to prepare medium and low voltage trench MOS devices has become a research direction for those skilled in the art.

Contents of the invention

In view of the above problems, the present invention discloses a medium and low voltage trench MOS device, including:

A heavily doped substrate of the first conductivity type, where the heavily doped substrate of the first conductivity type is divided into a cell region and a terminal region;

a lightly doped epitaxial layer of the first conductivity type, disposed on the heavily doped substrate of the first conductivity type;

a second conductivity type body region doped layer disposed on the first conductivity type lightly doped epitaxial layer;

A groove structure, including a cell region groove structure disposed in the cell region and a terminal region groove structure disposed in the terminal region, the cell region groove structure and the terminal region groove The structures are all disposed in the lightly doped epitaxial layer of the first conductivity type through the body doped layer of the second conductivity type;

a dielectric layer disposed on the doped layer of the body region of the second conductivity type and the trench structure;

a second conductivity type body region contact region, disposed in the second conductivity type body region doped layer;

a source region of the first conductivity type, disposed in the doped layer of the body region of the second conductivity type, and located on the contact region of the body region of the second conductivity type;

A contact hole includes a cell region contact hole and a terminal region contact hole, the cell region contact hole is disposed in the second conductivity type body region contact region through the dielectric layer, and the terminal region contact hole includes a terminal region contact hole that penetrates through the dielectric layer The dielectric layer is disposed in the first contact hole in the trench structure of the termination region and the dielectric layer passing through the termination region is disposed in the second contact hole in the contact region of the second conductivity type body region;

An electrode is arranged in the contact hole and covers part of the upper surface of the dielectric layer.

The above medium and low voltage trench MOS device, wherein, the first conductivity type is N-type, the second conductivity type is P-type or the first conductivity type is P-type, and the second conductivity type is N-type type.

In the above medium and low voltage trench MOS device, wherein the trench structure includes:

a trench, disposed in the lightly doped epitaxial layer of the first conductivity type through the body doped layer of the second conductivity type;

a gate oxide layer disposed on the bottom of the trench and its sidewall surfaces;

The conductive layer is arranged in the groove.

In the above medium and low voltage trench MOS device, the width of the trench is 0.2-1um.

In the above medium and low voltage trench MOS device, the gate oxide layer has a thickness of 200-600 angstroms.

In the above medium and low voltage trench MOS device, the thickness of the doped layer in the body region of the second conductivity type is 0.5-1um.

In the above medium and low voltage trench MOS device, the thickness of the dielectric layer is 0.2-1um.

The invention discloses a method for preparing a medium-low voltage trench type MOS device, which comprises the following steps:

Step S1, providing a first photolithography mask, a second photolithography mask, a third photolithography mask and a semiconductor structure having a cell region and a terminal region, the semiconductor structure includes a first conductivity type heavy a doped substrate and a lightly doped epitaxial layer of the first conductivity type located on the heavily doped substrate of the first conductivity type;

Step S2, forming a doped body layer of a second conductivity type on the lightly doped epitaxial layer of the first conductivity type;

Step S3, using the first photolithography mask to perform a trench etching process to form a trench in the cell region in the cell region and a trench in the termination region in the termination region, and the Both the trenches in the cell region and the trenches in the terminal region are disposed in the lightly doped epitaxial layer of the first conductivity type through the doped layer of the body region of the second conductivity type;

Step S4, forming a conductive layer in both the trenches of the cell region and the trenches of the terminal region;

Step S5, forming a dielectric layer on the conductive layer and the second conductive type body region doped layer;

Step S6, using the second photolithography mask to etch the dielectric layer to form a contact hole, and performing an ion implantation process on the doped layer of the second conductivity type body region at the bottom of the contact hole to form a first conductivity type source region;

Step S7, and after etching part of the source region of the first conductivity type, implanting ions into the doped layer of the body region of the second conductivity type at the bottom of the contact hole and the conductive layer to form a second conductivity type Body area contact area;

Step S8 , after forming conductive materials on both the front and back surfaces of the semiconductor structure, performing an etching process on the conductive materials by using the third mask to form electrodes of the MOS device.

The above method for manufacturing a low-voltage trench MOS device, wherein the first conductivity type is N-type, the second conductivity type is P-type or the first conductivity type is P-type, and the second conductivity type is P-type. The type is N type.

The above-mentioned method for manufacturing a low-voltage trench MOS device, wherein the step S2 includes:

Step S21, growing a first oxide layer on the lightly doped epitaxial layer of the first conductivity type;

Step S22 , performing ion implantation and annealing processes on the first oxide layer to form the doped body layer of the second conductivity type.

The above-mentioned method for manufacturing a low-voltage trench MOS device, wherein the step S3 includes:

Step S31, forming a second oxide layer on the doped layer of the body region of the second conductivity type;

Step S32, using the first photolithography mask to perform a trench etching process to form a lightly doped epitaxial layer disposed on the first conductivity type through the second oxide layer and the doped layer of the P-type body region in sequence. The cell region trenches and the terminal region trenches of the layer.

The above-mentioned method for manufacturing a low-voltage trench MOS device, wherein the step S4 includes:

Step S41, forming a sacrificial oxide layer on the bottom and sidewalls of the trenches in the cell region and the trenches in the terminal region;

Step S42, removing the sacrificial oxide layer and the second oxide layer;

Step S43, forming a gate oxide layer to cover the bottoms and sidewall surfaces of the trenches in the cell region and the trenches in the terminal region, and exposing the upper doped layer of the body region of the second conductivity type the surface is covered;

Step S44 , filling the trench with a conductive material to form the conductive layer.

The above-mentioned method for manufacturing a low-voltage trench MOS device, wherein the step S7 includes:

Step S71, etching the source region of the first conductivity type at the bottom of the contact hole in the cell region to form a cell region contact hole, and etching the conductive source region at the bottom of the contact hole in the terminal region. layer to form a contact hole in the first termination region, and simultaneously etch the source region of the first conductivity type at the bottom of the contact hole in the termination region to form a contact hole in the second termination region.

Step S72, performing a hole implantation process on the doped region of the body region of the second conductivity type through the contact hole in the cell region, and performing a hole implantation process on the conductive layer and the body region of the second conductivity type through the contact hole in the termination region A hole implantation process is performed on the doped layer to form a second conductivity type body region contact region around bottoms of the cell region contact hole and the terminal region contact hole.

In the manufacturing method of the above medium and low voltage trench MOS device, the thickness of the gate oxide layer is 200-600 angstroms.

In the manufacturing method of the above medium and low voltage trench MOS device, the width of the trench in the cell region and the trench in the terminal region is 0.2-1um.

In the manufacturing method of the above medium and low voltage trench MOS device, the thickness of the doped layer of the body region of the second conductivity type is 0.5-1um.

In the above-mentioned manufacturing method of a medium-low voltage trench MOS device, the thickness of the dielectric layer is 0.2-1um.

The above invention has the following advantages or beneficial effects:

The invention discloses a medium and low voltage trench type MOS device and a preparation method thereof. By using the trench structure as the terminal junction of the device, two photolithography masks, the working area and the protective ring mask plate, are omitted in the traditional process. and use a contact hole mask (i.e. the second photolithography mask) to form the source region of the device, so the source region mask in the traditional process is saved, so only the trench mask (i.e. The first photolithography mask), the contact hole mask (ie the second photolithography mask) and the metal mask (ie the third photolithography mask) three photolithography masks can be prepared For low-voltage trench MOS devices, due to the reduction in the number of layers of the photolithography plate, the process steps for device production are reduced, thereby greatly reducing the production cost of medium and low-voltage trench MOS devices, and thus improving the competitiveness of products.

Description of drawings

The invention and its characteristics, configurations and advantages will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. Like numbers designate like parts throughout the drawings. The drawings may not be drawn to scale, emphasis instead being placed upon illustrating the gist of the invention.

FIG. 1 is a schematic structural view of a medium-low voltage trench MOS device in an embodiment of the present invention;

Fig. 2 is the flow chart of the method for preparing medium and low voltage trench type MOS devices in the embodiment of the present invention;

3 to 16 are schematic diagrams of the process flow structure of the method for preparing a medium-low voltage trench MOS device in the embodiment of the present invention.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Embodiment one

As shown in Figure 1, this embodiment relates to a medium-low voltage trench MOS device. Specifically, the medium-low voltage trench MOS device includes a heavily doped liner of the first conductivity type that is divided into a cell region and a terminal region. The bottom 100, the first conductivity type lightly doped epitaxial layer 101 disposed on the first conductivity type heavily doped substrate 100, the second conductivity type body region disposed on the first conductivity type lightly doped epitaxial layer 101 The doped layer 102, the trench structure including the trench structure in the cell region and the trench structure in the termination region, and the trench structure in the cell region and the trench structure in the termination region are both disposed through the doped layer 102 in the body region of the second conductivity type In the lightly doped epitaxial layer 101 of the first conductivity type, the dielectric layer 105 arranged on the body doped layer 102 of the second conductivity type and the trench structure, and the second doped layer of the body region of the second conductivity type 102 The second conductivity type body region contact region 106, the first conductivity type source region 107 disposed in the second conductivity type body region doped layer 102 and located on the second conductivity type body region contact region 106, including a cell region contact The hole 1081 and the contact hole of the terminal area contact hole, and the cell area contact hole 1081 penetrates the dielectric layer 105 and is disposed in the second conductivity type body region contact area 106, and the terminal area contact hole includes a trench that penetrates the dielectric layer 105 and is disposed in the terminal area The first contact hole 10821 in the structure and the dielectric layer 105 penetrating through the terminal region are arranged in the second contact hole 10822 in the contact region 106 of the body region of the second conductivity type, and the second contact hole 10822 is arranged in the contact hole and covers part of the upper surface of the dielectric layer 105 Electrodes 109 (gate and source).

In a preferred embodiment of the present invention, the first conductivity type is N type and the second conductivity type is P type or the first conductivity type is P type and the second conductivity type is N type.

In a preferred embodiment of the present invention, the above-mentioned trench structure including the trench structure in the cell region and the trench structure in the termination region includes lightly doped layers of the first conductivity type disposed through the doped layer 102 of the body region of the second conductivity type. The trench in the epitaxial layer 101, the gate oxide layer 103 disposed on the bottom of the trench and its sidewall surface, and the conductive layer 104 disposed in the trench, in an embodiment of the present invention, the conductive layer 104 is polysilicon , the conductive layer 104 can also be other conductive materials, not limited to polysilicon.

On this basis, further, the width of the above-mentioned trenches is 0.2-1um (such as 0.2um, 0.5um, 0.6um or 1um, etc.), generally speaking, the depth of the trenches located in the terminal area is greater than that located in the cell area the depth of the groove.

On this basis, further, the gate oxide layer 103 has a thickness of 200-600 angstroms (for example, 200 angstroms, 300 angstroms, 400 angstroms or 600 angstroms, etc.).

In a preferred embodiment of the present invention, the thickness of the doped layer 102 in the body region of the second conductivity type is -0.5-1 um (0.5 um, 0.7 um, 0.8 um, 1 um, etc.).

In a preferred embodiment of the present invention, the thickness of the dielectric layer 105 is 0.2-1um (for example, 0.2um, 0.6um, 0.8um and 1um, etc.).

In a preferred embodiment of the present invention, the electrode 109 includes a gate and a source, and the maximum thickness of the electrode 109 is preferably 0.8-2um (for example, 0.8um, 1um, 1.4um or 2um, etc.).

Embodiment two

As shown in Figure 2, the present embodiment relates to a method for preparing a medium-low voltage trench type MOS device. The method of the present invention will be specifically described below by taking the preparation method of a medium-low voltage N-type trench type MOS device as an example; , the method includes

Step S1, providing a first photolithography mask (ie trench mask), a second photolithography mask (ie contact hole mask), a third photolithography mask (ie metal mask) And a semiconductor structure 200 having a cell region and a terminal region, the semiconductor structure 200 includes an N-type heavily doped substrate 2001 (N+) and an N-type lightly doped substrate 2001 located on the first conductivity type heavily doped substrate The epitaxial layer 2002 (N-) has a structure as shown in FIG. 3 .

Step S2 , forming a P-type body doped layer 201 on the N-type lightly doped epitaxial layer 2002 , as shown in FIG. 4 .

In a preferred embodiment of the present invention, the above step S2 specifically includes:

Step S21 , growing a first oxide layer on the N-type lightly doped epitaxial layer 2002 , the thickness of the first oxide layer is about 200 angstroms (180˜220 angstroms).

Step S22 , performing ion implantation and appropriate high-temperature annealing process on the first oxide layer to form a P-type body doped layer 201 , as shown in FIG. 4 .

In a preferred embodiment of the present invention, the thickness of the P-type body region doped layer 201 is -0.5-1um (0.5um, 0.7um, 0.8um, 1um, etc.).

Step S3, using the first photolithography mask to perform a trench etching process to form a cell region trench 2031 located in the cell region and a terminal region trench 2032 located in the terminal region, and the cell region trench 2031 The groove 2032 in the terminal region and the terminal region are both disposed in the N-type lightly doped epitaxial layer 2002 through the P-type body region doped layer 201 , as shown in FIGS. 5-6 .

In a preferred embodiment of the present invention, the above step S3 includes:

Step S31, forming a second oxide layer 202 with a thickness of about 200-10000 angstroms (such as 2000 angstroms, 6000 angstroms, 8000 angstroms or 10000 angstroms) on the doped layer 201 in the p-type body region by chemical vapor deposition, such as The structure shown in Figure 5.

Step S32, using the first photolithography mask to perform a trench etching process to form a cell region that is disposed in the N-type lightly doped epitaxial layer 2002 through the second oxide layer 202 and the P-type body region doped layer 201 in sequence The groove 2031 and the terminal area groove 2032; that is, the first photolithography mask is used to define the groove, and the width of the groove is about 0.2-1um, and then the cell area groove 2031 of the device is formed by dry etching and terminal region groove 2032, preferably, the width of the above-mentioned cell region groove 2031 and terminal region groove 2032 is 0.2-1um (such as 0.2um, 0.5um, 0.6um or 1um, etc.), and the terminal region groove 2032 The depth is greater than the depth of the trench 2031 in the cell area; the structure shown in FIG. 6 .

In step S4 , a conductive layer 206 is formed in both the cell region trench 2031 and the terminal region trench 2032 , as shown in FIGS. 7-10 .

In a preferred embodiment of the present invention, the above step S4 includes:

Step S41, forming a sacrificial oxide layer 204 on the bottom and sidewalls of the cell region trench 2031 and the termination region trench 2032, and the thickness of the sacrificial oxide layer 204 is 500˜1250 angstroms (for example, 500 angstroms, 600 angstroms, 900 angstroms) Angstroms or 1250 Angstroms, etc.), the structure shown in Figure 7.

In step S42, wet etching is used to remove the sacrificial oxide layer 204 and the second oxide layer 202, as shown in FIG. 8 .

In step S43, the gate oxide layer 205 is grown by high temperature oxidation to cover the bottoms and sidewall surfaces of the trenches 2031 in the cell region and the trenches 2032 in the terminal region, and expose the doped layer 201 in the P-type body region. The upper surface is covered, as shown in FIG. 9 .

In a preferred embodiment of the present invention, the gate oxide layer 205 has a thickness of 200-600 angstroms (for example, 200 angstroms, 300 angstroms, 400 angstroms or 600 angstroms, etc.).

Step S44, depositing a conductive material on the upper surface of the semiconductor structure formed in the above step S43 by means of chemical vapor deposition, the thickness of the conductive material is 0.5-2 μm (such as 0.5 μm, 0.6 μm, 0.8 μm or 2 μm, etc.), generally Polysilicon is selected as the conductive material; then dry etching is used to remove excess conductive material, and the dry etching stops on the upper surface of the gate oxide layer 205 to form a conductive layer 206 filled in the trench, as shown in FIG. 10 Structure.

Step S5 , forming a dielectric layer 207 on the conductive layer 206 and the P-type body doped layer 201 by chemical vapor deposition, as shown in FIG. 11 .

In a preferred embodiment of the present invention, the dielectric layer 207 has a thickness of 0.2-1um (for example, 0.2um, 0.6um, 0.8um and 1um, etc.).

Step S6, using a second photolithographic mask to etch the dielectric layer 207 to form a contact hole 208, and performing an ion implantation process on the P-type body region doped layer 201 at the bottom of the contact hole 208 to form an N-type source region 209, The structure shown in Figure 12-13.

In a preferred embodiment of the present invention, the above step S6 specifically includes:

First, use the second photolithography mask to define the contact hole of the device, then etch away the dielectric layer 207 by dry etching to form a contact hole 208, the structure shown in Figure 12, and then the P-type body at the bottom of the contact hole The region doping layer 201 is subjected to an ion implantation process to form an N-type source region 209, as shown in FIG. 13 .

Step S7, and after etching part of the N-type source region 209, implant ions into the P-type body region doped layer 201 and the conductive layer 206 at the bottom of the contact hole to form a P-type body region contact region; as shown in Figure 14- 15 shows the structure.

In a preferred embodiment of the present invention, the above step S7 specifically includes:

Step S71, etching the N-type source region 209 at the bottom of the contact hole in the cell region to form a cell region contact hole 2101, and etching the conductive layer 206 at the bottom of the contact hole in the terminal region to form a first terminal region contact hole 21021, while etching the N-type source region 209 at the bottom of the contact hole in the terminal region to form the second terminal region contact hole 21022. Preferably, the above etching adopts a dry etching process, as shown in FIG. 14 .

Step S72, perform a hole implantation process (hole ion implantation process) on the doped region of the P-type body region through the contact hole 2101 in the cell region, and contact holes 21022) to the conductive layer 206 and the p-type body doped layer 201 hole implantation process (hole ion implantation process), in order to contact holes 2101 in the cell area and terminal area contact holes (including the first terminal area contact hole 21021 and A P-type body region contact region 211 (that is, an ohmic contact of the body region) is formed around the bottom of the second termination region contact hole 21022), as shown in FIG. 15 .

Step S8, after forming metal materials (or other conductive materials, not limited to metal materials) on both the front and back surfaces of the semiconductor structure by physical vapor deposition, use the third mask to etch the metal materials to The electrodes 212 (gate and source) of the MOS device are formed, as shown in FIG. 16 .

It is not difficult to find that this embodiment is a method embodiment corresponding to the embodiment of the above medium and low voltage trench type MOS device, and this embodiment can be implemented in cooperation with the above embodiment of the above medium and low voltage trench type MOS device. The relevant technical details mentioned in the above embodiment of the medium and low voltage trench MOS device are still valid in this embodiment, and will not be repeated here in order to reduce repetition. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments of the medium and low voltage trench MOS devices.

Those skilled in the art should understand that those skilled in the art can implement variations by combining the existing technology and the foregoing embodiments, and details are not described here. Such variations do not affect the essence of the present invention, and will not be repeated here.

The preferred embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and the devices and structures that are not described in detail should be understood to be implemented in a common manner in the art; Within the scope of the technical solutions of the invention, the methods and technical contents disclosed above can be used.

Claims (17)

1. A medium and low voltage trench MOS device, characterized in that it comprises: A heavily doped substrate of the first conductivity type, where the heavily doped substrate of the first conductivity type is divided into a cell region and a terminal region; a lightly doped epitaxial layer of the first conductivity type, disposed on the heavily doped substrate of the first conductivity type; a second conductivity type body region doped layer disposed on the first conductivity type lightly doped epitaxial layer; A groove structure, including a cell region groove structure disposed in the cell region and a terminal region groove structure disposed in the terminal region, the cell region groove structure and the terminal region groove The structures are all disposed in the lightly doped epitaxial layer of the first conductivity type through the body doped layer of the second conductivity type; a dielectric layer disposed on the doped layer of the body region of the second conductivity type and the trench structure; a second conductivity type body region contact region, disposed in the second conductivity type body region doped layer; a source region of the first conductivity type, disposed in the doped layer of the body region of the second conductivity type, and located on the contact region of the body region of the second conductivity type; A contact hole includes a cell region contact hole and a terminal region contact hole, the cell region contact hole is disposed in the second conductivity type body region contact region through the dielectric layer, and the terminal region contact hole includes a terminal region contact hole that penetrates through the dielectric layer The dielectric layer is disposed in the first contact hole in the trench structure of the termination region and the dielectric layer passing through the termination region is disposed in the second contact hole in the contact region of the second conductivity type body region; An electrode is arranged in the contact hole and covers part of the upper surface of the dielectric layer. 2. The medium and low voltage trench MOS device according to claim 1, wherein the first conductivity type is N-type, the second conductivity type is P-type or the first conductivity type is P-type , the second conductivity type is N type. 3. The medium and low voltage trench MOS device according to claim 1, wherein the trench structure comprises: a trench, disposed in the lightly doped epitaxial layer of the first conductivity type through the body doped layer of the second conductivity type; a gate oxide layer disposed on the bottom of the trench and its sidewall surfaces; The conductive layer is arranged in the groove. 4. The medium and low voltage trench MOS device according to claim 3, characterized in that the width of the trench is 0.2-1um. 5. The medium and low voltage trench MOS device according to claim 3, wherein the gate oxide layer has a thickness of 200-600 angstroms. 6 . The medium and low voltage trench MOS device according to claim 1 , wherein the thickness of the doped layer in the body region of the second conductivity type is 0.5-1 μm. 7. The medium and low voltage trench MOS device according to claim 1, characterized in that the thickness of the dielectric layer is 0.2-1um. 8. A method for preparing a medium and low voltage trench type MOS device, characterized in that it comprises the steps of: Step S1, providing a first photolithography mask, a second photolithography mask, a third photolithography mask and a semiconductor structure having a cell region and a terminal region, the semiconductor structure includes a first conductivity type heavy a doped substrate and a lightly doped epitaxial layer of the first conductivity type located on the heavily doped substrate of the first conductivity type; Step S2, forming a doped body layer of a second conductivity type on the lightly doped epitaxial layer of the first conductivity type; Step S3, using the first photolithography mask to perform a trench etching process to form a trench in the cell region in the cell region and a trench in the termination region in the termination region, and the Both the trenches in the cell region and the trenches in the terminal region are disposed in the lightly doped epitaxial layer of the first conductivity type through the doped layer of the body region of the second conductivity type; Step S4, forming a conductive layer in both the trenches of the cell region and the trenches of the terminal region; Step S5, forming a dielectric layer on the conductive layer and the second conductive type body region doped layer; Step S6, using the second photolithography mask to etch the dielectric layer to form a contact hole, and performing an ion implantation process on the doped layer of the second conductivity type body region at the bottom of the contact hole to form a first conductivity type source region; Step S7, and after etching part of the source region of the first conductivity type, implanting ions into the doped layer of the body region of the second conductivity type at the bottom of the contact hole and the conductive layer to form a second conductivity type Body area contact area; Step S8 , after forming conductive materials on both the front and back surfaces of the semiconductor structure, performing an etching process on the conductive materials by using the third photolithography mask to form electrodes of the MOS device. 9. The manufacturing method of medium and low voltage trench MOS devices according to claim 8, wherein the first conductivity type is N-type, and the second conductivity type is P-type or the first conductivity type is P-type, and the second conductivity type is N-type. 10. The preparation method of medium and low voltage trench MOS devices as claimed in claim 8, characterized in that, said step S2 comprises: Step S21, growing a first oxide layer on the lightly doped epitaxial layer of the first conductivity type; Step S22 , performing ion implantation and annealing processes on the first oxide layer to form the doped body layer of the second conductivity type. 11. The manufacturing method of medium and low voltage trench MOS devices as claimed in claim 8, characterized in that said step S3 comprises: Step S31, forming a second oxide layer on the doped layer of the body region of the second conductivity type; Step S32, using the first photolithography mask to perform a trench etching process to form a lightly doped epitaxial layer disposed on the first conductivity type through the second oxide layer and the doped layer of the P-type body region in sequence. The cell region trenches and the terminal region trenches of the layer. 12. The preparation method of medium and low voltage trench MOS devices as claimed in claim 11, characterized in that said step S4 comprises: Step S41, forming a sacrificial oxide layer on the bottom and sidewalls of the trenches in the cell region and the trenches in the terminal region; Step S42, removing the sacrificial oxide layer and the second oxide layer; Step S43, forming a gate oxide layer to cover the bottoms and sidewall surfaces of the trenches in the cell region and the trenches in the terminal region, and exposing the upper doped layer of the body region of the second conductivity type the surface is covered; Step S44 , filling the trench with a conductive material to form the conductive layer. 13. The manufacturing method of medium and low voltage trench MOS devices as claimed in claim 12, characterized in that, the step S7 comprises: Step S71, etching the source region of the first conductivity type at the bottom of the contact hole in the cell region to form a cell region contact hole, and etching the conductive source region at the bottom of the contact hole in the terminal region. layer to form a contact hole in the first termination region, and simultaneously etch the source region of the first conductivity type at the bottom of the contact hole in the termination region to form a contact hole in the second termination region. Step S72, performing a hole implantation process on the doped region of the body region of the second conductivity type through the contact hole in the cell region, and performing a hole implantation process on the conductive layer and the body region of the second conductivity type through the contact hole in the termination region A hole implantation process is performed on the doped layer to form a second conductivity type body region contact region around bottoms of the cell region contact hole and the terminal region contact hole. 14. The method for manufacturing a medium-low voltage trench MOS device according to claim 12, wherein the gate oxide layer has a thickness of 200-600 angstroms. 15. The manufacturing method of a medium-low voltage trench MOS device according to claim 8, wherein the width of the trench in the cell region and the trench in the terminal region is 0.2-1 um. 16 . The method for manufacturing a medium-low voltage trench MOS device according to claim 8 , wherein the thickness of the doped layer in the body region of the second conductivity type is 0.5-1 μm. 17. The method for manufacturing a medium-low voltage trench MOS device according to claim 8, wherein the dielectric layer has a thickness of 0.2-1um.