CN107659800A - A kind of DMD high frame frequency and high resolutions synchronous dynamic display system - Google Patents

Abstract

The present invention relates to a DMD high frame rate and high resolution synchronous dynamic display system, comprising: a host computer, an interface module, a control module, and a digital micromirror device; image data; the interface module is connected to the control module for receiving the image data of the specific frame rate and decoding the image data; the control module is connected to the digital micromirror device for decoding Gray scale modulation and format conversion processing are carried out on the image data after, so as to satisfy the display frame rate and the display format of the digital micromirror device, and the image data after processing are loaded into the digital micromirror device; the digital micromirror device A device is used to display the processed image data. The invention can realize high frame rate, real-time transmission, and high-resolution display, and makes up for the lack of real-time display of high frame rate and high gray-level images by using DMD in the field of semi-physical simulation in China.

Description

A DMD High Frame Rate and High Resolution Synchronous Dynamic Display System

technical field

The invention belongs to the technical field of image processing, in particular to a DMD high frame rate and high resolution synchronous dynamic display system.

Background technique

The digital micromirror projection system is a reflective optical spatial modulator based on a micro-electromechanical structure, and its core device is a DMD (Digital Micromirror Device) produced by TI. DMD is a micromirror array composed of micromirrors, each micromirror represents a pixel, and the external radiation of the light source is switched on and off by controlling the flipping of the micromirrors. This device is currently widely used in projectors using DLP technology, and is developing rapidly in visible light projection. By replacing the transmission window of the DMD micromirror, it can also be used in the field of infrared projection. No matter which optical radiation band it is applied to, the control principle of the DMD micromirror is the same, and there are not many restrictions on the purchase of DMD in China, which gives Its application in the military field began to provide great convenience. Compared with other infrared scene generation systems, DMD has the advantages of high image resolution, good uniformity, small geometric deformation, high frame rate, and energy concentration.

Shanghai Institute of Technical Physics, Harbin Institute of Technology, Weapon 211 and other research institutes have all developed corresponding infrared image projection systems on the basis of changing the window of DMD. Among them, the DMD infrared dynamic scene simulator developed by Kang Weimin and others of Harbin Institute of Technology in 2008 has a resolution of 800×600, a gray scale of 8 bits, a frame frequency of 60Hz, a temperature resolution of 0.1°C, and no flicker in the image (see "Kang Weimin, Li Yanbin , Gao Weizhi. Development of digital micromirror array infrared dynamic scene simulator[J]. Infrared and Laser Engineering, 2008, (05): 753-756”); Ren Guotao of Harbin Institute of Technology developed a DMD-based visible light imaging guidance simulation system, The frame frequency can reach 60Hz (see "Ren Guotao. Design of Visible Light Imaging Guidance Simulation System Based on DMD [D]. Harbin Institute of Technology, 2016."). The DMD-based infrared dynamic target simulator developed by Zhang Kai and Ma Jun of Northwestern Polytechnical University in 2011 has a resolution of 1024×768, the image is also grayscale 8bit, and the frame frequency is continuously adjustable from 10 to 100 (see " Zhang Kai, Ma Jun, Sun Siliang. Design of Infrared Dynamic Target Simulator Drive and Control System[J]. Laser and Infrared, 2011, (01):58-62.", "Liang Yong, Zhao Xiaobei, Ma Jun, Li Shaoyi, Sun Li. Hardware system design of infrared scene simulator based on DMD [J]. Infrared Technology, 2011, (12): 683-686."). The infrared projection system developed by Weapon 211 has a resolution of 1024×768 and a frame rate of 100Hz. The frame rate of the DMD-based infrared scene simulator developed by Zhang Erlei and Qi Ming of China Air-to-Air Missile Research Institute is also 100Hz, and the energy contrast ratio reaches 91:1 (see "Zhang Erlei, Qi Ming. DMD-Based Dynamic Infrared Scene Generation System [ J]. Electronic Science and Technology, 2011, (07): 140-143.").

Yet, there is following shortcoming in the scheme of prior art: 1, the frame rate that existing DMD carries out the high-grayscale image display is not high. A simple switching operation of the DMD micromirror can only express a binary image. If a single DMD can display a grayscale image, it is necessary to perform grayscale modulation on the DMD. The traditional grayscale modulation algorithm, in the display process of high grayscale images such as 8bit, is difficult to increase the frame rate by more than 150Hz, which cannot meet the requirements of high frame rate. 2. The image display of DMD lacks real-time performance. At present, in the development of DMD-based scene simulators in China, in the process of projecting and displaying high frame rate and high grayscale images with a frame rate exceeding 200Hz, the image data is mostly converted and cached in advance, not from the host computer. Synchronously transmitted, the infrared scene projected by the DMD is not a real-time display of the scene simulated by the host computer.

Contents of the invention

In order to solve the above-mentioned problems existing in the prior art, the present invention provides a kind of DMD high frame rate high resolution synchronous dynamic display system capable of realizing high frame rate and real-time transmission display.

In order to realize the above-mentioned purpose of the invention, the technical scheme that the present invention adopts is:

A DMD high frame rate and high resolution synchronous dynamic display system, comprising: upper computer, interface module, control module, digital micromirror device;

The host computer is connected to the interface module for sending image data with a specific frame rate;

The interface module is connected to the control module, and is used to receive the image data of the specific frame rate and decode the image data;

The control module is connected to the digital micromirror device, and is used to perform grayscale modulation and format conversion processing on the decoded image data, so as to meet the display frame rate and display format of the digital micromirror device, and convert the processed image data loaded into said digital micromirror device;

The digital micromirror device is used to display the processed image data.

Further, the control module includes a control processor, a DMD drive unit, and a storage unit;

The control processor is used to perform grayscale modulation on the decoded image data, and convert the modulated grayscale value image into a bit plane image;

The DMD drive unit is connected to the control processor for loading the bit plane image to the digital micromirror device;

The storage unit is connected to the control processor and used for storing at least one of the decoded image data, the multi-gray value image data, and the bit plane image data.

Further, the gray scale modulation algorithm is a PWM algorithm.

Further, the storage unit includes at least two subspaces, each of which includes a plurality of bit plane spaces, wherein the number of bit plane spaces is determined according to the bit width of the pixel data.

Further, a display is also included, and the display is connected to the interface module;

The control module is also used to perform frame down processing on the decoded image data, and send the frame down processed image data to the display through the interface module;

The display is used for displaying the image data of the down-frame processing.

Further, the control processor is FPGA.

Further, the storage unit is DDR2 SDRAM high-speed memory.

Further, the interface module includes a DVI interface and an HDMI interface.

The embodiment of the present invention makes up for the lack of real-time display of high frame rate and high grayscale images by using DMD in the field of hardware-in-the-loop simulation in China. Firstly, the traditional PWM algorithm is optimized, so that the DMD can display 8bit grayscale images with a frame rate of over 200Hz. Then a data cache method based on DDR2 SDRAM block storage is proposed, which solves the data cache problem of DMD in the process of image format conversion and grayscale modulation of high frame rate dynamic images. Finally, the design goal of DMD real-time display of XGA resolution, 8bit grayscale images and frame frequency up to 200Hz was realized.

Description of drawings

Fig. 1 is a module block diagram of the DMD high frame rate and high resolution synchronous dynamic display system of the present invention.

Fig. 2 is a block diagram of the control module of the present invention.

Fig. 3 is a hardware structural diagram of the DMD high frame rate high resolution synchronous dynamic display system in a specific embodiment of the present invention.

Fig. 4 is a time relation diagram during the continuous loading process of the DMD in the embodiment of the present invention.

FIG. 5 is a time sequence diagram of a traditional PWM algorithm in an embodiment of the present invention.

FIG. 6 is an operation flowchart of the clearing and resetting method in the embodiment of the present invention.

FIG. 7 is a time sequence diagram of the clearing and resetting method in the embodiment of the present invention.

FIG. 8 is a schematic diagram of format conversion from a "pixel packet" format to a "bit plane" format.

FIG. 9 is a schematic diagram of the storage space division of the block-stored DDR2 SDRAM of the present invention.

FIG. 10 is a schematic diagram of the data flow of the block cache according to the present invention.

FIG. 11 is a schematic diagram of the parallel-to-serial conversion of the present invention.

Detailed ways

The present invention will be further described in detail below in combination with specific embodiments. But this should not be interpreted as that the scope of the above-mentioned theme of the present invention is limited to the following embodiments, and all technologies realized based on the content of the present invention all belong to the scope of the present invention.

Embodiment one

In this embodiment, the image gray level is 8 bits, and the display frame frequency is 200 Hz as an example for illustration.

Fig. 1 is a DMD high frame frequency high resolution synchronous dynamic display system module block diagram of the present invention, comprising: host computer 1, interface module 2, control module 3, digital micromirror device 4;

The host computer 1 is connected to the interface module 2 for sending image data at a specific frame rate;

The interface module 2 is connected to the control module 3, for receiving the image data of the specific frame rate, and decoding the image data;

The control module 3 is connected to the digital micromirror device 4, and is used to perform grayscale modulation and format conversion processing on the decoded image data, so as to meet the display frame rate and display format of the digital micromirror device 4, and The processed image data is loaded into the digital micromirror device 4;

The digital micromirror device 4 is used to display the processed image data.

Referring to Fig. 2, described control module 3 comprises control processor 31, DMD driving unit 32, storage unit 33;

The control processor 31 is used to perform grayscale modulation on the decoded image data, and convert the modulated grayscale value image into a bit plane image;

Described DMD driving unit 32 is connected described control processor 31, is used for loading described bit plane image to described digital micromirror device 4;

The storage unit 33 is connected to the control processor 31, and is used for storing at least one of the decoded image data, the multi-grayscale image data, and the bit-plane image data.

The storage unit includes at least two subspaces, each of which includes a plurality of bit plane spaces, wherein the number of bit plane spaces is determined according to the bit width of the pixel data. Among them, the pixel data is the bit width of the gray value of the image to be stored. In this embodiment, an image gray level of 8 bits is taken as an example, so the number of bit plane spaces is 8.

First introduce the hardware composition of the present invention. The hardware part of the present invention can be divided into two modules according to functions, data transmission and system control. The content of data transmission mainly includes the image signal and its synchronous control signal. The data channel exists between the host computer, DMD, display and control core FPGA. The system control part is mainly responsible for realizing the DMD gray-scale modulation algorithm and controlling the DMD for accurate display. In this embodiment, the block diagram of the hardware system of the present invention is shown in FIG. 3 .

The core control processor of the control module is FPGA (Field-Programmable Gate Array Field Programmable Gate Array); the interface module has HDMI (High Definition Multimedia Interface) and DVI (Digital Visual Interface) dual link Various data transmission interfaces are used to meet different data transmission requirements.

Specifically, the interface module is mainly responsible for receiving high-frequency real-time images from the host computer, and outputting a low-frequency image that has undergone frame reduction to the display. The real-time image frame frequency transmitted by the host computer of the present invention is as high as 200Hz, and the VESA (Video Electronics Standards Association Video Electronics Standards Association) timing output by the upper computer NVIDIA graphics card is calculated, and the pixel clock is 250MHz, even if the pixel clock is reduced by manually customizing the timing Clock, considering the stability of timing alone, the pixel clock will not be lower than 200MHz. Therefore the interface must support the transmission of images with a pixel clock exceeding 200MHz. Among the video output interfaces of computers at present, the most common ones are DVI and HDMI, both of which are high-bandwidth pure digital interfaces, and each has its own characteristics. In order to meet different application requirements, the present invention designs two interfaces, DVI and HDMI, at the video input end of the interface module for receiving images from the upper computer. In order to facilitate debugging and monitor the working conditions of the system, the present invention also designs one HDMI output interface, which is connected to the display.

The DMD high frame rate and high resolution synchronous dynamic display system of the present invention has designed a high-speed video transmission interface module meeting the real-time transmission requirements of high-bandwidth images at the input end of the data. Among them, the DVI dual-link interface and HDMI interface can transmit RGB 8bit images with a pixel clock of up to 300MHz, and support the transmission of XGA resolution images with a frame frequency of up to 200Hz. In order to facilitate debugging and monitor the working status of the system, the interface board also adds an HDMI output interface, which is connected to the monitor.

According to the above design scheme, two HDMI interfaces are designed on the interface module, one as input and the other as output. Among them, the input chip of HDMI is ADV7619 of ADI Company, which supports HDMI1.4 version, and the image color depth can reach up to 36bit. In terms of physical structure, ADV7619 supports two interface inputs at the same time. When the output image color depth is 24bit, the pixel clock can reach up to 300MHz. For data transmission between ADV7619 and FPGA, if you want to make the pixel clock reach 300MHz, the data transmission timing is similar to that of DVI dual link, and the odd and even pixels are also transmitted separately. Although this method will increase the bit width of the data bus and occupy more chip IO (Input/Output input/output) pins, the data transmission rate will be reduced, which helps to improve the stability of data transmission.

For the selection of HDMI output chip, the present invention has adopted SiI9136-3 of Silicon Image company, and this chip supports HDMI1.4 version, and image color depth supports 48bit at the highest, and pixel clock supports 300MHz at the highest equally. In the case of RGB format and 24bit color depth, the data formats of these two chips are R[23:16], G[15:8], B[7:0]. Assign the RGB channels to the same value, and a grayscale image will appear on the monitor. Taking the 8bit grayscale image as an example, any 8bit of the 24bit channel can be selected as the effective data input bit when the image is input, and the 8bit data can be assigned to the three channels of RGB and output to the display when monitoring the output.

In the process of debugging and working, it is necessary to monitor the output results of the algorithm with a monitor. Since the highest frame rate of images displayed by monitors currently on the market is mostly lower than 100Hz, while the image frame rate of this system is 200Hz, it is necessary to downframe the image when monitoring image output. In order to simplify the logic, the present invention down-frames the image by an integer multiple, reducing the frame frequency of the image to 50 Hz.

The frame-down image is still output according to the VESA timing standard, and is output from the FPGA to the HDMI sending chip SiI9136-3. Inside the SiI9136-3, the data sent by the FPGA is encoded into a TMDS (Transition-minimized differential) suitable for high-speed transmission of the interface. signaling minimized transmission differential signal) format, sent to the display. Before ADV7619 and SiI9136-3 work, the FPGA also needs to configure the chip through the I2C (Inter-Integrated Circuit) bus (composed of clock SCL and data bus SDA) to make it in the current required working mode.

Specifically, the control module is the control core of the whole system, mainly responsible for the realization of the DMD grayscale modulation algorithm and the video image frame reduction algorithm, as well as the display driver of the DMD. The core control processor of the control module is a Virtex-5LX series (XC5VLX50) FPGA of Xilinx Company, and a DDR2 SDRAM (KTL-TP667/2G) high-speed memory of Kingston Company is plugged in. The control module is connected with the interface module through the board-to-board high-speed interface (QTE-060-01) for data communication.

The upper computer sends the image from the graphics card to the DVI and HDMI interface in TMDS format, and the image data is decoded by the DVI and HDMI decoding chip and then sent to the FPGA of the control core board through the QTE-060-01 interface. According to the received data, FPGA completes the operation of DMD grayscale modulation and frame reduction algorithm in combination with DDR2 SDRAM, and drives the DMD and HDMI encoding chips to output and display the algorithm results.

The DMD driving instruction is sent to the DMD controller DLPC410 in the DMD chipset, and the DMD is jointly controlled by the DLPC410 and the DMD driver DAD2000 to display. The frame-down image data is sent to the HDMI encoding chip SII9136-3 of the interface board through the QTE-060-01 interface according to the VESA standard. After encoding the image data, the SII9136-3 sends it to the monitor in TMDS format for display.

For the DMD grayscale display algorithm, the grayscale is an important index to represent the image. The higher the grayscale, the richer the image layer and the softer the picture. For a black and white image, the gray scale reflects the brightness level of pixels from white to black. The human visual system's judgment on the intensity of brightness is determined by many factors, in addition to the brightness of the luminous object itself, it is also related to the luminous time and luminous area of the luminous object. For fast flickering illuminants, both human eyes and detectors will produce a certain "persistence of vision" effect. Using this "persistence of vision" effect, the purpose of generating different grayscale images can be achieved by changing the lighting time of the illuminant, thereby realizing the grayscale modulation of the image. At a certain distance, for a very weak illuminant, the effect of changing the visual gray scale can also be achieved by changing the area of the illuminated illuminant. The two working states of DMD "on" and "off" only represent "0" and "1" of the pixel value, and what is projected out is a binary image with a gray bit width of only 1 bit. To make the DMD display multi-bit gray levels, the DMD needs to be gray-scale modulated. DMD mainly performs grayscale modulation based on two aspects of time and space, so its grayscale modulation methods can be mainly divided into two types: spatial grayscale modulation and time grayscale modulation.

The advantage of spatial grayscale modulation is that it is easy to control. In a single frame image, the micromirror does not need to be flipped, and the frame rate of the image can reach a high level. But it has unavoidable defects. First, the pixel unit is divided into a limited number of "sub-pixels", which makes it unable to display higher gray levels. Secondly, it expands the pixel unit area to increase the gray level, resulting in a decrease in the resolution of the image. On the premise of maintaining high resolution, it is difficult for the existing specification DMD to increase too much gray level. Therefore, the present invention adopts time grayscale modulation.

Specifically, the present invention uses a PWM (Pulse Width Modulation) algorithm to perform grayscale modulation.

Generally, in the technical field of the present invention, a resolution greater than 1024×768, a frame frequency of 1 bit above 32000hz, an 8bit real-time synchronization of above 200hz, and a non-real-time synchronization of above 400hz can be regarded as high frame frequency and high resolution. The image grayscale requirement of the present invention is 8bit, and the display frame frequency is 200Hz, and the traditional PWM algorithm is difficult to meet the frame frequency requirement of the present invention, so the present invention provides a PWM optimization algorithm.

The main factor limiting DMD frame rate is the time consumed by DMD data loading and "resetting". The selected DMD data transmission clock is up to 400Mhz. It takes at least 30.72us for DMD to complete a complete data update. It takes 5us to reset after receiving the "micromirror timing pulse", and 8us for micromirror stabilization time after reset. No new data can be loaded within the micromirror stabilization time. Figure 4 shows the time relationship during the continuous loading of DMD. It can be seen from the figure that the minimum time for displaying a frame is 30.72us+8us=38.72us.

If the traditional PWM algorithm is used to display an 8-bit grayscale image, the original image needs to be divided into 8 "bit planes", and data loading and "resetting" of the DMD are performed 8 times. In order to ensure the continuity of the image display, the current bit plane needs to be The data loading work of the next bit plane is completed within the display time. Therefore, the display time t of the "basic bit plane" should satisfy t≥38.72us. In order to calculate the limit frame rate of 8bit image, it is assumed here that t=38.72us.

The DMD first loads the bit plane 0 data, and after the data is loaded, sends a "micromirror timing pulse" to the DMD to reset the micromirror and enter the "micromirror stabilization time", wait for the micromirror to stabilize and start loading the bit plane 1 data, During this period, DMD displays the data of bit plane 0. After the data loading of bit plane 1 is completed, the display time of bit plane 0 is just over. Immediately send a "micromirror timing pulse" to the DMD to reset the micromirror. After the reset, enter the display time of bit plane 1. This time is according to the principle of PWM algorithm. It should be 2t((30.72us×2)us), which is enough time to complete the loading of bit plane 2 data. After the display time of bit plane 1 is over, the data loading of bit plane 2 has already been completed, and a "micromirror timing pulse" is sent to the DMD immediately to reset the micromirror, and enter the display time of bit plane 2. By analogy, the data loading work of the next bit plane is completed within the display time of the previous bit plane, so as to ensure the continuity of image display. The timing relationship of the traditional PWM algorithm is shown in Figure 5.

After waiting for the display of bit plane 7 to be completed, the PWM modulation of an 8-bit grayscale image is considered to be completed. In the whole process, the consumption time t _p1 is equal to the sum of all bit plane display time t _d and reset time t _r . Its calculation method is:

t _p1 =t _r +t _d

=(5×8+255×38.72)us

=9913.6us

The available frame rate is:

f _p1 =1/t _p1 =100.9Hz

Can draw by analysis, traditional PWM algorithm, the display limit of 8bit grayscale image frame frequency is 100.9Hz, is difficult to satisfy the design requirement of the present invention. So it must be optimized on the basis of PWM algorithm.

The invention optimizes the PWM algorithm by adopting a zero-resetting method.

In the global reset mode, set the display time of the basic bit plane as t=18us, and use the "block clear" operation to clear the entire DMD to consume 0.64us. After each reset, it is necessary to wait for the micromirror stabilization time of 8us, during which the DMD cannot perform data update. Only when the display time of the bit plane is longer than 38.72us, can the loading work of the next bit plane data be completed during the display period of the current bit plane. Otherwise, at the end of the display time of the bit plane, the data of the micromirror is cleared and reset, so that the micromirror is in the closed state, and the image display is in the blanking area. Starting from bit plane 2, the bit plane display time will be greater than 38.72us, so it is only necessary to perform the "block clear" operation when the first two bit planes are displayed. The operation flow of the clear reset method is shown in Figure 6.

Figure 7 shows the timing relationship of the clear reset method. First load the data of bit plane 0 to the DMD, and then send the "block clear" operation to all blocks of the DMD when it displays 17.36us, and the clear operation is completed after 0.64us, and then send the "micromirror timing pulse" to the DMD to enable It is reset, and at this time the display of DMD bit plane 0 ends, DMD is in BLANK state, and the display is completely black. Wait for 8us for the micromirror to stabilize after clearing and resetting the micromirror, and then load the data of bit plane 1 to the DMD, which also takes 30.72us. After 35.36us, the "block clear" operation is also performed on all blocks of the DMD. Load the data of bit plane 2 in the second BLANK section of DMD, the display time of bit plane 2 is 72us, and the display time is longer than 38.72us, so there is no need to perform "block clear" operation in the subsequent bit plane display process.

Under the clear reset method, the calculation formula of the minimum time t _p3 consumed by displaying 8bit images is:

t _p3 =t _r +t _d

＝(5×8+255×18+43.72×2)us

=4717.44us

The frame rate is:

f _p3 =1/t _p3 =211.9Hz

It can be obtained through calculation that after adopting the method of resetting and clearing, the frame frequency of DMD displaying 8bit images reaches 211.9Hz, which meets the design requirements. Reset reset method, although there will be a brief BLANK interval during the display process of the lower two bits of data, but the BLANK time is very short, accounting for 3.5% of the effective display time, so the impact on the image grayscale accuracy is not great, you can can be ignored. Therefore, the invention uses the reset and clear method as the 8-bit grayscale modulation algorithm of the DMD. In order to match the 200Hz image frame rate of the upper computer, the present invention sets the display time of the basic bit plane to 19.11us during the implementation process. The formula for calculating the image display time t _p4 is:

t _p4 =t _r +t _d

=(5×8+255×19.11+43.72×2)us

=5000.49us

The limit frame rate is:

f _p4 =1/t _p4 =200.0Hz

The existing PWM algorithm’s basic bit-level display time is too long, which limits the frame rate of the DMD to display high-gray images. to 19.11us, making the image frame frequency reach more than 200Hz, which meets the design requirements of the system.

Because the display principle of DMD based on PWM algorithm requires data loading in the form of bit planes, a frame of image is divided into several bit planes to be displayed sequentially, and the number of bit planes determines the gray level of the image. Since the data formats of the input and output images are different, it is necessary to convert the format of the image received from the host computer before the DMD display, and convert the image signal based on the VESA standard "pixel packet" format into a "pixel packet" format suitable for DMD display. bit plane” format image signal.

Figure 8 is a schematic diagram of format conversion. On the left is an image in the “Pixel Pack” format with a pixel gray value bit width of 8 bits and following the VESA timing sequence. After format conversion, 8 bit planes are obtained. Bit plane 0 is equivalent to a binary image formed by combining the lowest bits of all pixels in the original image, and other bit planes are essentially binary images composed of "bits" corresponding to the original image.

Converting the image format is equivalent to reorganizing the image data, so it is inevitable to cache the data during the data reorganization process. There is a certain Block RAM inside the FPGA, which has the characteristics of convenient operation, strong controllability, simple logic, and stable reading and writing. It is very suitable for high-speed data cache. However, Block RAM is an embedded resource of FPGA after all, and its storage space is limited. As mentioned above, the system of the present invention also has a piece of DDR2 SDRAM outside the FPGA. Its capacity is sufficient and its reading and writing speed is fast. The operation is relatively complicated, and coupled with the particularity of the PWM algorithm, it is also difficult to implement using an external memory.

The system requires that the amount of image data processed in real time is XGA@200Hz, and the bit width of the image gray value is 8bit. For the received host computer image data, the first thing to do is to store it. In the implementation of the data storage method, one way to deal with it is to store it as a whole, store it together directly, and read each data bit by bit when it needs to be output, so that the entire storage space can be read repeatedly 8 times to get 8 corresponding bit planes. Another approach is to block storage, first split it, and then store separately. Each bit plane is stored in a separate memory space.

When the overall storage is used, since the bit width of the DDR2 SDRAM data bus is 64 bits, and the bit width of the pixel data is 8 bits, if the memory only stores 8 bits of data each time, it will cause a waste of idle bandwidth in the data bus during work. In order to fully utilize the transmission bandwidth of the memory, the present invention performs serial-to-parallel conversion on the pixel data before data storage, that is, data merging. Combine 8 consecutive pixels into one 64bit data, and write every 8 pixels, so there are 98304 data in one frame of image. When DMD loads data, what needs to be obtained is the data in the bit plane format, while the read operation of DDR2 SDRAM is aimed at the address, and each time an address data is read, a DQ[63:0] will be obtained. DQ[63:0] has a total of 64bit data, but not all of them are required by the system, so data selection must be performed. For example, when loading bit plane 0, only DQ[0], DQ[8], DQ[16], DQ[24], DQ[32], DQ[40], DQ[48], DQ[56] belong to the first 8 pixels of bit plane 0, and the rest are the data of the other 7 bit planes. The same holds true for other bitplane loads. In a complete PWM algorithm time, the storage space of the entire image frame needs to be read 8 times to obtain 8 bit planes respectively.

Since there are 56 bits of invalid data in the data obtained each time during the memory reading process, this causes a great waste of data transmission bandwidth. In fact, the effective utilization rate of the data transmission bandwidth is only 12.5%. In this mode of operation, to meet the DMD loading requirements, the transmission rate of DDR2 SDRAM needs to be 98304÷30.72us=3.2GHz, which has exceeded the upper limit of the transmission rate of DDR2 SDRAM, even the data transmission of the highest level DDR4 SDRAM The speed is also difficult to meet the demand. Therefore, although the overall storage logic is simple, the utilization rate of DDR2 SDRAM transmission bandwidth is too low when data is read.

In order to solve the problem of low utilization rate of the data transmission bandwidth in the above scheme, the present invention also proposes a method of data block storage. In the way of block storage, it is necessary to split the data by bits before storing the data, and store the split data separately in the DDR2SDRAM. Similarly, in order to make full use of the read-write bandwidth of DDR2 SDRAM, before data is written, serial-to-parallel conversion is also required for the split data, and 64 consecutive 1-bit data are merged into one 64-bit data for storage and reading operations. In order to ensure the continuity of data processing, the present invention uses a ping-pong storage method to divide the entire memory into two subspaces. During the process of writing data to subspace 1, the last frame of data in subspace 2 is read, and the data is reversed. In the process of writing to subspace 2, the previous frame of data in subspace 1 is read, and the two subspaces read and write alternately to ensure the continuity of data processing. Each subspace is further divided into 8 bit plane spaces. A bit plane contains 1024×768×1bit data, and a storage unit in the bit plane space can store 64bit data, so a bit plane space contains at least 12288 storage units. Figure 9 shows the storage space division of DDR2 SDRAM in the case of block storage.

The peak of DDR2 SDRAM data transmission is also in the process of DMD data loading, using the method of block storage, because the original data is divided and reorganized, so that when DMD data is loaded, all the data obtained by reading DDR2 SDRAM every time is valid data , only need to read 12288 addresses to get a complete bit plane. In this process, the data transfer rate of DDR2 SDRAM is 12288÷30.72us＝400MHz. This rate is less than the upper limit of DDR2 SDRAM data transmission, so although the block storage method is complex in logic, it can greatly reduce the bandwidth pressure of DDR2 SDRAM data transmission, so the present invention uses block storage as the data in the PWM algorithm The way of caching. Its data flow block diagram is shown in Figure 10.

Firstly, serial-to-parallel conversion is performed on each bit of the 8-bit data received from the host computer, and this process can be realized with RAM. Because the conversion ratio of a RAM can reach 1:32 at most, so the present invention has used the mode of two-stage FIFO cascading, and the conversion ratio of each stage RAM is respectively 1:16 and 1:4, and the conversion ratio of two-stage cascading is 1:64. The serial-to-parallel converted data should be sent to DDR2 SDRAM. First, the ping-pong operation selection unit will select the subspace, select the free subspace to store the data in, and the 8 bit plane spaces in the selected subspace will be accessed one by one. , and store the 8 pieces of 64-bit data obtained by the first serial-to-parallel conversion into the corresponding bit-plane space sequentially in 8 times. While the current frame data is stored in DDR2 SDRAM, another subspace is also outputting the bit plane in conjunction with DMD loading. There is also a ping-pong operation selection unit at the output end, which will select the subspace that has updated the data and stopped the input for output. , each time the data of one bit plane space is output to DMD, and the data from bit plane space 0 to bit plane space 7 are read sequentially within the loading time of 8 bit planes of a frame of image.

In the use of DDR2 SDRAM, the present invention adopts the built-in MIG3.61 DDR2 controller of FPGA, and the use of DDR2 core controller can make the system save the complicated process of pre-charging and refreshing in the process of SDRAM reading and writing in the process of controlling the work of DDR2 SDRAM. Logical operations, only need to read and write according to the read and write timing of the user interface.

When performing data input and output, the DMD loading rate can reach up to 800MHz. At this rate, it takes 30.72us for DMD to load a bit plane. This time is the limit of DMD data update, if the DMD loading rate is less than 800MHz, then the DMD data loading time will be extended, that is, the time consumed by DMD loading will be increased, which will reduce the DMD display frame rate. At the same time, it can be seen from the PWM algorithm that the extension of the DMD loading time will also increase the blanking time during the reset reset process, thus affecting the accuracy of the DMD high grayscale display.

The present invention utilizes the method of duplicating a plurality of processing modules to reduce the operating speed of the FPGA, so that the total data processing rate will not be reduced. The present invention performs parallel-to-serial conversion before the output of image data and control signals, and the conversion ratio is 4:1. The two LVDS buses with a bit width of 16 bits during the DMD data loading process correspond to two data signals DATA_B[63:0] and DATA_B[63:0] with a bit width of 64 bits during the operation process inside the FPGA. After parallel-to-serial conversion, the FPGA only needs a running speed of 200MHz to satisfy the data output of 800MHz. For details, refer to the schematic diagram of the parallel-to-serial conversion shown in Figure 11 .

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (8)

1. A DMD high frame rate high resolution synchronous dynamic display system is characterized in that, comprising: host computer, interface module, control module, digital micromirror device; The host computer is connected to the interface module for sending image data with a specific frame rate; The interface module is connected to the control module for receiving the image data of the specific frame rate and decoding the image data; The control module is connected to the digital micromirror device, and is used to perform grayscale modulation and format conversion processing on the decoded image data, so as to meet the display frame rate and display format of the digital micromirror device, and convert the processed image data loaded into said digital micromirror device; The digital micromirror device is used to display the processed image data. 2. DMD high frame rate and high resolution synchronous dynamic display system according to claim 1, is characterized in that, described control module comprises control processor, DMD drive unit, storage unit; The control processor is used to perform grayscale modulation on the decoded image data, and convert the modulated grayscale value image into a bit plane image; The DMD driving unit is connected to the control processor for loading the bit plane image to the digital micromirror device; The storage unit is connected to the control processor and used for storing at least one of the decoded image data, the multi-gray value image data, and the bit plane image data. 3. DMD high frame rate high resolution synchronous dynamic display system according to claim 2, is characterized in that, described grayscale modulation algorithm is PWM algorithm. 4. DMD high frame rate high resolution synchronous dynamic display system according to claim 2, is characterized in that, described storage unit comprises at least two subspaces, and each described subspace comprises a plurality of bit plane spaces, wherein, The number of bit plane spaces is determined according to the bit width of the pixel data. 5. DMD high frame rate high resolution synchronous dynamic display system according to claim 2, is characterized in that, It also includes a display connected to the interface module; The control module is also used to perform frame reduction processing on the decoded image data, and send the frame reduction processed image data to the display through the interface module; The display is used for displaying the image data of the down-frame processing. 6. DMD high frame rate high resolution synchronous dynamic display system according to claim 2, is characterized in that, described control processor is FPGA. 7. DMD high frame rate high resolution synchronous dynamic display system according to claim 2, is characterized in that, described storage unit is DDR2SDRAM high-speed memory. 8. DMD high frame rate high resolution synchronous dynamic display system according to claim 2, is characterized in that, described interface module comprises DVI interface and HDMI interface.