CN107644878A - Phase inverter and preparation method thereof - Google Patents

Abstract

The invention discloses an inverter, which includes a transistor and a resistor, wherein the transistor includes: an electric double layer gate dielectric layer, a gate electrode located on one side of the electric double layer gate dielectric layer, and a gate electrode located on the electric double layer gate dielectric layer At least one lateral control terminal, channel, source and drain on the other side, wherein the channel is in contact with the source and drain respectively; and none of the lateral control terminals is in contact with the channel, source and drain and one end of the resistor is electrically connected to the drain, and the other end is used to apply the power supply voltage V _DD ; the gate electrode of the transistor is used as the input end, the drain is used as the output end, the source is grounded, and at least one side regulation end is used to apply The fixed bias voltage V _{m is} used to adjust the threshold voltage of the transistor. The invention can greatly reduce the operating voltage of the inverter, reduce the manufacturing cost, realize the balanced noise tolerance of the inverter, and improve the electrical characteristics of the inverter.

Description

Inverter and method of making the same

technical field

The invention relates to the technical field of microelectronics, in particular to a low working voltage inverter with an improved structure and a manufacturing method thereof.

Background technique

In recent years, logic circuits have been widely used in various semiconductor integrated circuits, for example, Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), Static Random Access Memory (Static Random Access Memory, SRAM), and Liquid Crystal Display (Liquid Crystal Display, LCD), etc. Among them, the inverter is the basis of the logic circuit.

Traditional complementary metal-oxide-semiconductor (Complementary metal-oxide-semiconductor, CMOS) inverters are usually implemented with silicon channels, which are formed by doping group III elements (such as boron) in silicon to form p-type channels, or An n-type channel is formed by doping silicon with a Group V element such as phosphorus. Due to the mature silicon-based integrated circuit technology, this type of inverter has been commonly used in a large number of electronic products. Furthermore, in view of the comprehensive advantages of oxide semiconductor materials, oxide thin film transistors using it as the active channel layer are becoming the star of the electronic information industry, and are used in the fields of new generation transparent and flexible flat panel displays or wearable and portable electronic products. It has a strong application prospect.

Although the performance of the oxide thin film transistor is good, and its field-effect electron mobility is as high as 10-100 cm ² /Vs, there is still a lack of an oxide thin film transistor with p-type conductivity matching it. Specifically, the p-type oxide thin film transistors reported so far not only have poor device performance (hole mobility<1cm ² /Vs), but also need to improve the stability, and the process is relatively complicated. Therefore, the electrical performance of the all-oxide based CMOS inverter circuit is greatly affected. Although some CMOS inverter circuits have been made by combining p-type organic transistors and n-type oxide transistors, the problem of p-type organic transistors is that their mobility is also small (<1cm ² /Vs) and their stability is poor. In view of this, people also use two kinds of n-type oxide thin film transistors with different threshold voltages to design inverter circuits.

However, the transistors used in the above-mentioned inverters usually use traditional gate dielectric films, and their capacitance per unit area is small, usually less than tens of nF/cm ² . The converter circuit has the disadvantage of relatively large operating voltage. In addition, the manufacturing process of this inverter requires multiple photolithography mask steps, which has the disadvantages of high complexity and high process cost. The above disadvantages limit the application of the above inverters in low power consumption and portable electronic products.

For example, the traditional double-gate thin film transistor usually adopts a top-down structure, that is, a bottom-gate transistor and a top-gate transistor are combined, and at least 5 layers of "bottom gate/gate dielectric/channel/gate dielectric/top gate" need to be used in key parts. structure, the two sides of the channel layer need to use additional conductive layers to obtain electrical contact. This structure requires a multi-step photolithography mask process, the process flow is complex, each step requires a strict alignment process, and the cost is high.

Contents of the invention

The purpose of the present invention is to address the deficiencies of the current state of the art of the above-mentioned inverter, and propose a low-voltage inverter and a new manufacturing process thereof. effect, effectively improving the electrical performance of the inverter. The manufacturing process is simple and easy, can greatly reduce the manufacturing cost of the inverter, and is suitable for large-area continuous production.

In one aspect of the present invention, an inverter is provided, including: a transistor and a resistor, wherein,

The transistor includes: an electric double layer gate dielectric layer, a gate electrode located on one side of the electric double layer gate dielectric layer, and at least one lateral regulation terminal located on the other side of the electric double layer gate dielectric layer, a channel, a source and a drain, wherein the channel is in contact with the source and the drain respectively; and none of the lateral control terminals is in electrical communication with the channel, the source and the drain; and

One end of the resistor is electrically connected to the drain, and the other end is used to apply the power supply voltage VDD;

The gate electrode of the transistor is used as an input terminal, the drain is used as an output terminal, and the source is grounded. At least one lateral regulating terminal is used for applying a fixed bias voltage V _m , and the fixed bias voltage Vm is used for adjusting the threshold voltage of the transistor.

In a preferred embodiment of the present invention, the transistor is a bottom-gate transistor, wherein the conductive layer on the insulating substrate serves as a bottom-gate electrode on one side of the electric double layer gate dielectric layer.

In a preferred example of the present invention, the lateral control terminal is used to adjust the fixed bias voltage Vm and the input voltage applied on the bottom gate electrode, and realize the control of the channel through the electric double layer effect of the electric double layer gate dielectric layer. Conductivity control.

In a preferred example of the present invention, the channel layer is independently selected from the group consisting of indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide, and the thickness of the channel layer is 10 nm˜100 nm.

In a preferred embodiment of the present invention, the source electrode, the drain electrode, the lateral regulation terminal or the bottom gate electrode are independently selected from the following group: InZnO thin film, Ag thin film, Au thin film, Cu thin film, InSnO thin film.

In a preferred embodiment of the present invention, the gate dielectric layer adopts a solid electrolyte with an electric double layer regulation effect, and is independently selected from the following group: loose oxide dielectric film, sodium alginate film, and chitosan film.

In a preferred embodiment of the present invention, the solid electrolyte having the effect of regulating the electric double layer is independently selected from the group consisting of loose silicon oxide film and loose aluminum oxide film.

In a preferred example of the present invention, the capacitance per unit area of the solid electrolyte with electric double layer regulation effect is 0.1-100 μF/cm2.

In a preferred example of the present invention, the number of lateral control terminals included in the transistor is 1-4.

In a preferred example of the present invention, the area of the lateral regulating end is 0.1 to 10 times the area of the channel.

In a preferred example of the present invention, the distance between the lateral regulating end and the channel is 0.5 to 10 times the size of the channel.

In another aspect of the present invention, a method for manufacturing an inverter is provided, comprising the following steps:

Step 1: Provide an insulating substrate,

Step 2: forming a bottom gate electrode on the surface of the insulating substrate;

Step 3: forming an electric double layer gate dielectric layer on the surface of the bottom gate electrode;

Step 4: Forming a patterned channel layer, patterned source and drain, and at least one patterned lateral control terminal on the electric double layer gate dielectric layer, wherein the channel is connected to the source and drain respectively Contact, the lateral control terminal is not electrically connected with the channel, source and drain;

Step 5: Connect one end of a resistor to the drain.

In another aspect of the present invention, an electronic product is also provided, which includes the above-mentioned inverter.

It should be understood that within the scope of the present invention, the above-mentioned technical features of the present invention and the technical features specifically described in the following (such as embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, we will not repeat them here.

Description of drawings

FIG. 1 is a schematic structural diagram of an inverter according to an embodiment of the present invention;

Fig. 2a-2c is the electrical characteristic test result of the inverter that obtains according to the present invention;

3 is a schematic flow diagram of a method for manufacturing an inverter according to an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of an inverter according to the present invention.

In each drawing, 1: insulating substrate; 2: bottom gate electrode; 3: electric double layer gate dielectric layer; 4a and 4b: first and second lateral control terminals; 5a: drain; 5b: source ;6: resistance; 7: channel. V _DD : applied power supply voltage; V _In : applied voltage at the input terminal; V _Out : detected voltage at the output terminal; V _m : applied bias voltage at the control terminal.

detailed description

After extensive and in-depth research, the inventors have found that the use of an electric double layer solid electrolyte in the gate dielectric layer of the transistor of the inverter can significantly reduce the operating voltage of the inverter and have high voltage gain. At the same time, in A lateral regulating terminal is arranged on the transistor, and by applying a bias voltage at the regulating terminal, the electrical performance of the transistor can be effectively regulated, thereby regulating the electrical performance of the inverter. Therefore, the low working voltage inverter and the preparation method thereof proposed by the present invention can further reduce the production cost while obtaining low working voltage and high voltage gain, and can be used in biochemical sensing, low-power portable electronic products and bionic electronics. The product field has broad application prospects.

Typical technical solutions of the present invention include:

A conductive layer is deposited on an insulating substrate as a bottom gate electrode, a solid electrolyte with an electric double layer control effect deposited on the bottom gate electrode serves as a gate dielectric, and a patterned semiconductor film deposited on the gate dielectric serves as a thin film transistor channel. The channel layer; the source and drain electrodes are deposited at appropriate positions on the channel layer, and at the same time, a patterned conductive layer that is not connected to each other is deposited synchronously as a lateral control terminal. The source of the thin film transistor is grounded, the drain of the transistor is connected in series with the resistor, the power supply voltage V _DD is applied to the other end of the resistor, the gate electrode of the transistor is used as the input terminal, the drain of the transistor is used as the output terminal, and at the same time A fixed bias voltage is applied to one or more lateral regulation terminals provided on the transistor to regulate the electrical performance of the inverter, so as to obtain a low operating voltage inverter with an improved structure.

inverter

The present invention provides an inverter, including: a transistor and a resistor, wherein,

The transistor includes: an electric double layer gate dielectric layer, a gate electrode located on one side of the electric double layer gate dielectric layer, and at least one lateral regulation terminal located on the other side of the electric double layer gate dielectric layer, a channel, a source and The drain, wherein the channel is in contact with the source and the drain respectively; and none of the lateral control terminals is electrically connected to the channel, the source and the drain; and,

One end of the resistor is electrically connected to the drain, and the other end is used to apply the power supply voltage V _DD ;

The gate electrode of the transistor is used as an input terminal, the drain is used as an output terminal, the source is grounded, and at least one lateral regulation terminal is used to apply a fixed bias voltage V _m , and the fixed bias voltage V _m is used to adjust the threshold voltage of the transistor.

In the present invention, the fixed bias voltage V _m is used to regulate the electrical performance of the transistor, more specifically to regulate the threshold voltage of the transistor, so as to further realize the balanced noise margin of the inverter. In other words, the lateral control terminal is used to control the conductivity of the channel through the electric double layer effect of the electric double layer gate dielectric layer by adjusting the fixed bias voltage V _m and the input voltage applied to the bottom gate electrode.

For ease of understanding, the structural principle of the inverter of the present invention will be further described below. Fig. 4 is a schematic circuit diagram of an example of an inverter of the present invention. It should be understood that the protection scope of the present invention is not limited by the principles described.

In the present invention, the thickness of the channel layer is not particularly limited, and is generally 10 nm to 100 nm.

The gate dielectric layer adopts a solid electrolyte with an electric double layer regulating effect, and can be independently selected from the following group: loose oxide dielectric film, sodium alginate film, and chitosan film. More specifically, the solid electrolyte with the electric double layer regulation effect can be independently selected from the group consisting of loose silicon oxide films and loose aluminum oxide films.

In the present invention, the capacitance per unit area of the above-mentioned solid electrolyte having the effect of regulating the electric double layer is 0.1-100 μF/cm ² .

In the present invention, the input voltage V _In may range from -1V to 3V, and the power supply voltage V _DD may range from 0V to 3V.

In the present invention, the electric double-layer solid electrolyte involved has the following properties. Under the action of an external electric field, the ions present in the solid electrolyte migrate to the electrolyte/electrode interface or the electrolyte/channel interface, and then on one side of the electrode or in the channel. A layer of carrier accumulation layer with the opposite charge to the ion and the same charge is induced on the side, thereby inducing an interface double layer at the interface. The thickness of this interface double layer is extremely small (~1nm), and its capacitance per unit area Extremely large (0.1-100μF/cm ² ), so this solid-state electrolyte has a strong electrostatic regulation ability, and the working voltage of an oxide thin film transistor using this solid-state electrolyte as a gate dielectric is extremely small (<2V).

Furthermore, a lateral control terminal is provided on the bottom-gate oxide thin film transistor, and the device performance of the thin film transistor can be effectively controlled by setting the bias voltage of the lateral control terminal, so as to facilitate the realization of the balanced noise tolerance of the inverter.

In the present invention, the number of lateral control ends is not particularly limited. From the perspective of practical application, the number can be 1 to 10, preferably 1-4; the area of the lateral control terminal is not particularly limited. From the perspective of practical application, the area It should be 0.1 to 50 times the channel area, and the preferred area should be 0.5 to 10 times the channel area; the distance between the lateral control end and the channel is not particularly limited, which is based on the electric double layer gate dielectric For the control effect of the electric double layer, from the perspective of practical application, the spacing should be 0.1 to 1000 times the channel size, preferably 0.5 to 10 times.

It should be pointed out that, in other preferred embodiments of the present invention, under the condition that multiple lateral regulation terminals are provided, one or several lateral regulation terminals can be selected to apply a fixed bias voltage.

In the present invention, the insulating substrate is not particularly limited. Preferred insulating substrates include (but are not limited to): single crystal silicon substrates deposited with thermally oxidized SiO ₂ , glass substrates, plastic substrates, paper substrates, ceramic substrates.

In the present invention, the solid electrolyte is not particularly limited. The preferred solid electrolyte with electric double layer regulating effect can be loose oxide dielectric film, sodium alginate film, chitosan film, or a combination thereof, preferably loose SiO ₂ film and loose Al ₂ O ₃ film.

In the present invention, preferred channel layers include (but are not limited to): indium zinc oxide composite film (InZnO), indium gallium zinc oxide composite film (InGaZnO), indium tungsten oxide film (IWO), or combination.

In a preferred example, the source electrode, the drain electrode, the lateral regulation terminal or the bottom gate electrode can be independently selected from the following group: InZnO thin film, Ag thin film, Au thin film, Cu thin film, InSnO thin film.

In the present invention, an electronically conductive oxide semiconductor thin film is used as the channel of thin film transistors (TFTs), and a solid electrolyte with electric double layer control effect is used as a gate dielectric to manufacture n-type oxide TFTs.

According to the present invention, by changing the conductivity of the channel (or changing the resistance value of the resistor), the distribution mode of the power supply voltage V _DD on the resistor and the channel can be changed. Therefore, the area where the resistance of the channel changes with the bias voltage of the gate electrode (or input voltage) directly affects the voltage transfer curve of the inverter. There is a voltage transfer threshold voltage (V _Inv ) on the voltage transfer curve of the inverter. If V _Inv = V _DD /2, the balanced noise margin condition can be achieved. However, if the region where the channel resistance varies with gate electrode bias (or input voltage) is poor, the balanced noise margin condition cannot be achieved. Therefore, in combination with the lateral control terminal technology of the present invention, the effective control of the area where the channel resistance changes with the gate electrode bias (or input voltage) can be realized, thereby achieving a balanced noise margin condition.

Production Method

The present invention also provides a manufacturing method of the inverter, which comprises the following steps:

Step 1: Provide an insulating substrate,

Step 2: forming a bottom gate electrode on the surface of the insulating substrate;

Step 3: forming an electric double layer gate dielectric layer on the surface of the bottom gate electrode;

Step 4: Forming a patterned channel layer, a patterned source and drain, and at least one patterned lateral control terminal on the electric double layer gate dielectric layer, wherein the channel is respectively connected to the The source and the drain are in contact, and the lateral control terminal is not electrically connected to the channel, the source and the drain;

Step 5: Connect one end of a resistor to the drain.

In the present invention, the conventional manufacturing equipment in the field can be selected, the above-mentioned suitable materials can be selected, and the inverter of the present invention can be prepared by existing methods. Representative preparation methods include, but are not limited to: deposition, sputtering, thermal evaporation, or combinations thereof.

application

The inverter of the present invention can be applied to various occasions.

The present invention provides an electronic product, which includes the inverter described in the present invention.

Typically, the electronic products include: various sensors (such as biochemical sensors), low-power or portable electronic products and bionic electronic products.

The main advantages of the present invention include:

1) The present invention uses a solid electrolyte with an electric double layer control effect as the gate medium, and its capacitance per unit area is extremely large, so it has a strong electrostatic control characteristic, which can greatly reduce the operating voltage of the oxide thin film transistor, thereby obtaining a low working voltage inverter.

2) Due to the super-capacitive coupling effect of the solid electrolyte, the alignment requirements for device manufacturing are low, and the source, drain electrodes, and lateral control terminals can be obtained simultaneously, which can greatly reduce the process cost of device manufacturing, and is suitable for large-area continuous Production.

3) A lateral control terminal is set on the bottom gate oxide thin film transistor, and the device performance of the thin film transistor can be effectively regulated by setting the bias voltage of the lateral control terminal. Therefore, the electrical performance of the inverter can be biased by the lateral control terminal. It is regulated by the voltage setting, so as to facilitate the balanced noise margin of the inverter.

4) Due to the low operating voltage of the inverter circuit, a larger inverter voltage gain can be obtained at a lower operating voltage, and the voltage transition region of the voltage transfer curve characteristic is narrow, which is conducive to improving the dynamic electrical characteristics of the inverter.

5) In the present invention, the transistor adopts a bottom-gate structure combined with a side-gate structure, and the lateral control terminal can be deposited synchronously with the source, which reduces the requirements for the alignment process, and the lateral control terminal can effectively control the electrical properties of the bottom-gate transistor. performance, which cannot be achieved by thin-film transistors using traditional gate dielectrics.

Therefore, the manufacturing method of the low operating voltage inverter provided by the present invention greatly reduces the operating voltage of the inverter circuit, improves the electrical characteristics of the inverter, and has a simple manufacturing process and low cost. Power consumption portable electronic products and bionic electronic products have very broad application prospects.

Below in conjunction with specific embodiment, further illustrate the present invention. It should be understood that these examples are only used to illustrate the present invention and are not intended to limit the scope of the present invention. For the experimental methods without specific conditions indicated in the following examples, usually follow the conventional conditions or the conditions suggested by the manufacturer. Percentages and parts are by weight unless otherwise indicated.

Example: Inverter 1

The inverter according to this embodiment includes: a transistor and a resistor, wherein,

The transistor includes: an electric double layer gate dielectric layer, a gate electrode located on one side of the electric double layer gate dielectric layer, and at least one lateral regulation terminal located on the other side of the electric double layer gate dielectric layer, a channel, a source and The drain, wherein the channel is in contact with the source and the drain respectively; and none of the lateral control terminals is electrically connected to the channel, the source and the drain; and,

One end of the resistor is electrically connected to the drain, and the other end is used to apply the power supply voltage V _DD ;

The gate electrode of the transistor is used as an input terminal, the drain is used as an output terminal, and the source is grounded. One of the lateral control terminals is used to apply a fixed bias voltage V _m , and the fixed bias voltage V _m is used to adjust the threshold voltage of the transistor.

Specifically, the fixed bias voltage V _m is used to regulate the electrical performance of the transistor, more specifically, to regulate the threshold voltage of the transistor, so as to further realize the balanced noise margin of the inverter. In other words, the lateral control terminal is used to control the conductivity of the channel through the electric double layer effect of the electric double layer gate dielectric layer by adjusting the fixed bias voltage V _m and the input voltage applied to the bottom gate electrode.

In this embodiment, the channel layer may be independently selected from the group consisting of indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide, and the thickness of the channel layer is 10 nm˜100 nm.

The source electrode, the drain electrode, the lateral regulating terminal or the bottom gate electrode can be independently selected from the following group: InZnO thin film, Ag thin film, Au thin film, Cu thin film, InSnO thin film.

The gate dielectric layer adopts a solid electrolyte with an electric double layer regulating effect, and can be independently selected from the following group: loose oxide dielectric film, sodium alginate film, and chitosan film. More specifically, the solid electrolyte with the electric double layer regulation effect can be independently selected from the group consisting of loose silicon oxide films and loose aluminum oxide films.

The capacitance per unit area of the above-mentioned solid electrolyte with electric double layer regulating effect is 0.1-100 μF/cm ² .

The input voltage V _In may range from -1V to 3V, and the power supply voltage V _DD may range from 0V to 3V.

In this embodiment, the electric double layer solid electrolyte involved has the following properties. Under the action of an external electric field, the ions present in the solid electrolyte migrate to the electrolyte/electrode interface or the electrolyte/channel interface, and then on one side of the electrode or in the channel One side induces a layer of carrier accumulation layer that is opposite to the ionic charge and has the same charge, thereby inducing an interface double layer at the interface. The thickness of this interface double layer is extremely small (~1nm), and its unit area The capacitance is extremely large (0.1-100μF/cm ² ), so this solid electrolyte has a strong electrostatic regulation ability, and the working voltage of an oxide thin film transistor using this solid electrolyte as a gate dielectric is extremely small (<2V).

In this embodiment, a lateral regulating terminal is provided on the bottom-gate oxide thin film transistor.

Taking the channel length and channel width as 80 μm and 1 mm respectively as an example, the number of lateral control terminals can be selected as one, the size of the lateral control terminals is 150 μm×1 mm, and the distance between the lateral control terminals and the drain is 300 μm.

Example: Inverter 2

The inverter in this embodiment is basically the same as the above-mentioned embodiments, and will not be described again. The difference between them is that the inverter in this embodiment uses a bottom-gate transistor.

More specifically, as shown in FIG. 1, the inverter of this embodiment includes a transistor and a resistor 6, wherein,

The transistor includes: an electric double layer gate dielectric layer 3, a bottom gate electrode 2 located on one side of the electric double layer gate dielectric layer, and a first lateral regulating terminal 4a and a second lateral control terminal 4a located on the other side of the electric double layer gate dielectric layer 3 Two lateral control terminals 4b, channel layer 7, source 5b and drain 5a, wherein the channel layer 7 is in contact with source 5b and drain 5a respectively; and the first and second lateral control terminals 4a, 4b are not in electrical communication with the channel layer 7, the source 5b and the drain 5a; and,

One end of the resistor 6 is electrically connected to the drain 5a, and the other end is used to apply the power supply voltage V _DD ;

The bottom gate electrode 2 of the transistor is used as an input terminal, the drain 5a is used as an output terminal, the source 5b is grounded, and the first lateral regulation terminal 4a is used to apply a fixed bias voltage V _m , and the fixed bias voltage V _m is used to adjust the threshold voltage of the transistor . In other preferred embodiments of the present invention, the second lateral regulating end 4b can also be used to apply the internal fixed bias voltage V _m .

In this embodiment, the fixed bias voltage V _m is used to regulate the electrical performance of the transistor, specifically, to regulate the threshold voltage of the transistor, so as to further realize the balanced noise margin of the inverter. In other words, the first and second lateral regulating terminals 4a, 4b are used to adjust the fixed bias voltage V _m and the input voltage applied to the bottom gate electrode 2, through the electric double layer effect of the electric double layer gate dielectric layer 3 , to control the conductivity of the channel layer 7 .

In this embodiment, the channel layer 7 may be independently selected from the group consisting of indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide, and the thickness of the channel layer is 10 nm˜100 nm. The source electrode 5b, the drain electrode 5a, the first and second lateral regulating terminals 4a, 4b or the bottom gate electrode 2 can be independently selected from the following group: InZnO thin film, Ag thin film, Au thin film, Cu thin film, InSnO thin film. The electric double layer gate dielectric layer 3 adopts a solid electrolyte with an electric double layer regulating effect, and can be independently selected from the following group: loose oxide dielectric film, sodium alginate film, and chitosan film. More specifically, it may be independently selected from the group consisting of loose silicon oxide films and loose aluminum oxide films. The capacitance per unit area of the above-mentioned solid electrolyte with electric double layer regulating effect is 0.1-100 μF/cm ² . The input voltage V _In may range from -1V to 3V, and the power supply voltage V _DD may range from 0V to 3V.

In this embodiment, a fixed bias voltage V _m is applied to the first lateral regulating terminal 4a. In a bottom-gate transistor, the bias voltage applied on the bottom gate electrode 2 realizes the control of the conductivity of the channel layer 7 through the electric double layer effect of the electric double layer gate dielectric 3. When the first lateral control terminal 4a When a fixed bias voltage V _m is applied, the strength of this electric double layer effect is effectively changed, and thus the performance of the bottom-gate thin film transistor drifts.

In this embodiment, a resistance-loaded inverter is obtained by connecting the bottom-gate oxide thin film transistor to the resistor 6, and the bottom-gate oxide thin film transistor uses a solid electrolyte with an electric double layer control effect as a double electric Layer gate dielectric layer 3. Wherein, the source 5b of the transistor is grounded, the drain 5a is connected in series with one end of the resistor 6, the other end of the resistor 6 is applied with a power supply voltage V _DD , the bottom gate electrode 2 of the transistor is used as the input terminal, and the drain 5a of the transistor is used as the output At the same time, the first and second lateral regulation terminals 4a, 4b are set on the transistor to regulate the electrical performance of the inverter.

The structure of the bottom-gate oxide thin film transistor of this embodiment can be formed in the following manner:

A conductive layer is deposited on an insulating substrate 1 as a bottom gate electrode 2 . Thereafter, a solid electrolyte having an electric double layer control effect is deposited on the insulating substrate 1 as the electric double layer gate dielectric layer 3 . Then, a patterned semiconductor thin film is deposited on the electric double layer gate dielectric layer 3 as the channel layer 7 of the thin film transistor. Thereafter, the source electrode 5b and the drain electrode 5a are deposited on appropriate positions of the channel layer 7, and at the same time, a conductive layer that is not connected to each other is deposited as the first and second lateral regulation terminals 4a, 4b.

Embodiment: the manufacture method 1 of inverter

As shown in Figure 3, the manufacturing method of the inverter of this embodiment includes the following steps:

Step 101: providing an insulating substrate,

Step 102: forming a bottom gate electrode on the surface of the insulating substrate;

Step 103: forming an electric double layer gate dielectric layer on the surface of the bottom gate electrode;

Step 104: Form a patterned channel layer, a patterned source and drain, and at least one patterned lateral regulation terminal on the electric double layer gate dielectric layer, wherein the channel is connected to the source and drain respectively Contact, the lateral control terminal is not electrically connected with the channel, source and drain;

Step 105: Connect one end of a resistor to the drain.

In the above steps, the channel layer may be independently selected from the group consisting of indium zinc oxide, indium gallium zinc oxide, and indium tungsten oxide, and the thickness of the channel layer is 10 nm˜100 nm. The source electrode, the drain electrode, the lateral regulating terminal or the bottom gate electrode are independently selected from the following group: InZnO thin film, Ag thin film, Au thin film, Cu thin film, InSnO thin film. The gate dielectric layer adopts a solid electrolyte with an electric double layer regulation effect, and is independently selected from the following group: loose oxide dielectric film, sodium alginate film, chitosan film, more specifically, can be independently selected from the following Group: loose silicon oxide film and loose aluminum oxide film. The capacitance per unit area of the above-mentioned solid electrolyte with electric double layer regulating effect is 0.1-100 μF/cm ² .

Embodiment: the manufacturing method 2 of inverter

Referring to Fig. 1, in the present embodiment, the insulating substrate 1 adopts a glass substrate, the conductive layer used as the bottom gate electrode 2 adopts indium tin oxide (InSnO), the electric double layer gate dielectric layer 3 selects chitosan film, and the source The drain electrodes 5a and 5b and the first and second lateral regulating terminals 4a and 4b are made of InZnO thin film, the channel layer 7 is made of InZnO thin film, and the resistance value of the resistor 6 is 4MΩ.

The manufacturing method of the inverter comprises the following steps:

Step 1: Strictly clean the insulating substrate 1, immerse the insulating substrate 1 in alcohol and deionized water for 10 minutes, then rinse it repeatedly with deionized water, and finally dry it with a nitrogen gun for use.

Step 2: using magnetron sputtering technology to deposit an InSnO conductive thin film layer on the surface of the insulating substrate 1 as the bottom gate electrode 2 of the thin film transistor;

Step 3: Using the solution method, spin-coat the chitosan solution on the insulating substrate 1 deposited with the InSnO conductive film as the bottom gate electrode 2, and dry it to obtain the chitosan film as the electric double layer of the thin film transistor Gate dielectric layer 3.

Step 4: Using magnetron sputtering technology, deposit a patterned InZnO channel layer 7, patterned source and drain electrodes 5a and 5b, patterned The first and second lateral control ends 4a and 4b of BL.

Step 5: Connect a resistor with a resistance value of 4MΩ to the drain 5a through a wire.

Step 6: Apply an input voltage V _In on the bottom gate electrode 2, apply a fixed bias voltage on the resistor 6 as the power supply voltage V _DD , apply a fixed bias voltage V _m on the lateral regulation terminal 4a, and detect the output on the drain 5a Voltage V _Out , so as to obtain an inverter circuit with a side regulation terminal, and the performance of the inverter can be adjusted by V _m bias voltage.

Embodiment: the manufacturing method 3 of inverter

Referring to Fig. 1, in the present embodiment, the insulating substrate 1 adopts a paper substrate, the conductive layer used as the bottom gate electrode 2 adopts indium tin oxide (InSnO), the electric double layer gate dielectric layer 3 adopts a loose _SiO2 film, and the source The drain electrodes (5a and 5b) and the first and second lateral control terminals 4a and 4b are made of InZnO thin film, the channel layer 7 is made of InZnO thin film, and the resistance value of the resistor 6 is 10MΩ.

The manufacturing method of the inverter comprises the following steps:

Step 1: Deposit SiO ₂ thin film on paper for flattening treatment, and the obtained paper deposited with SiO ₂ thin film is used as insulating substrate 1 .

Step 2: using magnetron sputtering technology, depositing an InSnO conductive thin film layer on the surface of the insulating substrate 1 as the bottom gate electrode 2 of the thin film transistor;

Step 3: Deposit a layer of loose SiO ₂ film 3 on the InSnO conductive layer as the bottom gate electrode 2 by using plasma enhanced chemical vapor deposition technology, using silane and oxygen as the reaction gas, as the electric double layer gate dielectric layer 3 .

Step 4: Using magnetron sputtering technology, deposit a patterned InZnO channel layer 7 and a patterned source-drain electrode 5a on the insulating substrate 1 deposited with a loose _SiO2 film 3 as an electric double layer gate dielectric layer 3 and 5b, patterned first and second lateral regulation ends 4a, 4b.

Step 5: Connect a resistor with a resistance value of 10MΩ to the drain 5a through a wire.

Step 6: Apply an input voltage V _In on the bottom gate electrode 2, apply a fixed bias voltage on the resistor 6 as the power supply voltage V _DD , apply a fixed bias voltage V _m on the lateral regulation terminal 4a, and detect the output on the drain 5a Voltage V _Out , so as to obtain an inverter circuit with a side regulation terminal, and the performance of the inverter can be adjusted by V _m bias voltage.

Embodiment: the manufacturing method 4 of inverter

Referring to Fig. 1, in the present embodiment, the insulating substrate 1 adopts a plastic substrate, the conductive layer used as the bottom gate electrode 2 adopts gold, the electric double layer gate dielectric layer ₃ adopts a loose _Al2O3 thin film, the source drain electrode 5a and 5b and the first and second lateral control terminals 4a and 4b are made of Ag thin film, the channel layer 7 is made of InGaZnO thin film, and the resistance value of the resistor 6 is 6MΩ.

The manufacturing method of the inverter comprises the following steps:

Step 1: Strictly clean the insulating substrate 1, immerse the substrate in alcohol and deionized water and ultrasonically clean it for 10 minutes, then rinse it repeatedly with deionized water, and finally dry it with a nitrogen gun for use.

Step 2: using thermal evaporation technology, depositing an Au thin film layer on the surface of the insulating substrate 1 as the bottom gate electrode 2 of the thin film transistor;

Step 3: Using plasma-enhanced chemical vapor deposition technology, using trimethylaluminum and oxygen as the reaction gas, the trimethylaluminum gas is brought into the reaction chamber using Ar as the carrier gas, and the Au conductive film used as the bottom gate electrode 2 A layer of loose aluminum oxide film is deposited on the layer as the electric double layer gate dielectric layer 3;

Step 4: Deposit a patterned InGaZnO channel layer 7 on the insulating substrate 1 deposited with a loose aluminum oxide (Al ₂ O ₃ ) film as the electric double layer gate dielectric layer 3 by using magnetron sputtering technology;

Step 5: Using thermal evaporation technology, deposit a patterned Ag thin film on the channel layer 7 as the source and drain electrodes 5a and 5b, and at the same time obtain an isolated mutual isolation on the loose aluminum oxide (Al ₂ O ₃ ) film Unicom patterned Ag thin films, as the first and second lateral control terminals 4a and 4b;

Step 6: Connect a resistor with a resistance value of 6MΩ to the drain 5a through a wire.

Step 7: Apply an input voltage V _In on the bottom gate electrode 2, apply a fixed bias voltage on the resistor 6 as the power supply voltage V _DD , apply a fixed bias voltage V _m on the lateral regulation terminal 4a, and detect the output on the drain 5a Voltage V _Out , so as to obtain an inverter circuit with a side regulation terminal, and the performance of the inverter can be adjusted by V _m bias voltage.

test case

The test results of the inverter of the present invention will be described below by taking FIGS. 2a-2c as examples.

Figures 2a-2c show the test results of the electrical characteristics of the inverter of the present invention, wherein the electric double layer gate dielectric layer 3 is a chitosan film, which has a very strong electric double layer regulation effect, so the prepared bottom gate oxide The transistor can work in a lower voltage range (<2V), and at the same time, when an appropriate fixed bias voltage is applied to the regulation terminal 4a, 4b on the first or second side, the threshold voltage of the transistor can be effectively regulated, so the inverter The electrical properties of can also be effectively regulated by setting this side regulation terminal. An inverter with balanced noise margin is obtained by applying the bias voltage to the control terminal sideways.

In Fig. 2a-2c, the power supply voltage V _DD is set to 1V, the load resistance is 4MΩ, and the scanning range of the input voltage V _in is -0.6V～1V. When the side regulation terminal voltage V _m is set to 1V, the transition threshold voltage V _Inv of the voltage transfer curve of the inverter is -0.1V, and the inverter has not yet reached the requirement of balanced noise margin. When the side regulation terminal voltage V _m is set to -2V, the transition threshold voltage V _Inv of the inverter voltage transfer curve is ~ 0.5V (= V _DD /2), and the inverter has reached the balance noise margin at this time Require. Figure 2c shows the relationship between V _Out and V _In when V _m is set to -2V, and the relationship between V _In and V _Out . It can also be seen that when V _m is set to -2V, the reverse phase The device meets the requirement of balanced noise margin. Figure 2b shows the result of the voltage gain. The voltage gain is obtained by deriving V _out to V _in , which is |dV _out /dV _in |. When V _m is set to 1V, the voltage gain is about 8.3; when V _m is set to -2V, the voltage gain is about 9.5. It can be seen that, through the inverter of the present invention, the balanced noise margin can be effectively achieved, which also shows the beneficial effect of the application of the bias voltage V _m at the lateral regulation terminal in the present invention.

comparative example

When the electric double-layer gate dielectric layer 3 is changed to a high-density gate dielectric film (that is, a solid electrolyte that does not have ion-conducting properties, such as: thermally oxidized SiO ₂ or dense Al ₂ O ₃ film, etc.), the thin film transistor operates at a lower In the voltage range (<3V), effective transistor electrical performance cannot be achieved, and the control of the gate voltage on the conductivity of the channel layer is invalid, that is, under the condition of fixed channel source and drain electrode bias, the channel current does not follow the gate changes with changes in voltage. At the same time, under the existing process and technical conditions, the lateral control electrode 4 is introduced on the side of the thin film transistor fabricated on the dense gate dielectric film. When different fixed bias voltages are applied to the lateral control electrode 4, it is impossible to realize the bottom gate type Effective regulation of thin film transistor performance.

Application prospects

The inverter of the invention not only obtains low operating voltage and high voltage gain value, but also significantly reduces production cost, and has important application prospects in the fields of biochemical sensing, low-power portable electronic products, bionic electronic products and the like.

In the claims and specification of this patent, relative terms such as first and second, etc. are used only to distinguish one entity or operation from another, and do not necessarily require or imply that these entities or operations There is no such actual relationship or order between the operations. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element. In the claims and description of this patent, if it is mentioned that an action is performed according to a certain element, it means that the action is performed according to the element at least, which includes two situations: performing the action only based on the element, and performing the action based on the element. This element and other elements perform the behavior.

Although the present invention has been illustrated and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the present invention. The spirit and scope of the invention.

Claims (10)

1. An inverter, characterized in that it comprises: a transistor and a resistor, wherein, The transistor includes: an electrical double layer gate dielectric layer, a gate electrode located on one side of the electrical double layer gate dielectric layer, and at least one lateral regulating terminal located on the other side of the electrical double layer gate dielectric layer, a channel, a source and a drain, wherein the channel is in contact with the source and the drain respectively; Electrode Unicom; and One end of the resistor is electrically connected to the drain, and the other end is used to apply a power supply voltage V _DD ; The gate electrode of the transistor is used as an input terminal, the drain is used as an output terminal, the source is grounded, and at least one of the lateral regulation terminals is used to apply a fixed bias voltage V _m , and the fixed bias voltage V _m is used for Adjust the threshold voltage of the transistor. 2. The inverter according to claim 1, wherein the transistor is a bottom-gate transistor, wherein the conductive layer on the insulating substrate serves as a layer on one side of the electric double layer gate dielectric layer bottom gate electrode. 3. The inverter according to claim 2, wherein the lateral regulating terminal is used to adjust the fixed bias voltage V _m and the input voltage applied on the bottom gate electrode, through the The electric double layer effect of the electric double layer gate dielectric layer realizes the control of the conductivity of the channel. 4. The inverter according to claim 1, wherein the channel layer is independently selected from the group consisting of indium zinc oxide, indium gallium zinc oxide, indium tungsten oxide, and the channel layer The thickness is 10 nm to 100 nm. 5. The inverter according to claim 1, wherein the source, the drain, the side regulation terminal or the bottom gate electrode are independently selected from the following group: InZnO thin film, Ag thin film, Au thin film, Cu thin film, InSnO thin film. 6. The inverter according to claim 1, wherein the gate dielectric layer adopts a solid electrolyte having an electric double layer regulation effect, and is independently selected from the group consisting of loose oxide dielectric film, alginic acid Sodium film, chitosan film. 7. The inverter according to claim 6, characterized in that, the solid electrolyte having an electric double layer control effect is independently selected from the group consisting of loose silicon oxide films and loose aluminum oxide films. 8 . The inverter according to claim 7 , wherein the capacitance per unit area of the solid electrolyte with electric double layer regulating effect is 0.1˜100 μF/cm ² . 9. A manufacturing method of an inverter, comprising the following steps: Step 1: Provide an insulating substrate, Step 2: forming a bottom gate electrode on the surface of the insulating substrate; Step 3: forming an electric double layer gate dielectric layer on the surface of the bottom gate electrode; Step 4: Forming a patterned channel layer, a patterned source and drain, and at least one patterned lateral regulation terminal on the electric double layer gate dielectric layer, wherein the channel is respectively connected to the The source and the drain are in contact, and the lateral control terminal is not electrically connected to the channel, the source and the drain; Step 5: Connect one end of a resistor to the drain. 10. An electronic product, characterized in that the electronic product comprises the inverter according to any one of claims 1-5.