CN107632949A - Data line identification circuit, method and terminal - Google Patents

Abstract

The application relates to a data line identification circuit, a method and a terminal, wherein the data line identification circuit is used for identifying the type of an accessed data line, and the type of the data line comprises an OTG data line, a charging data line and an OTG charging data line. An interface identification circuit, comprising: the interface module is used for accessing an OTG data line, a charging data line and an OTG charging data line; the debugging module is connected with the interface module, comprises a first output end and a second output end and is used for correspondingly outputting corresponding level signals to the first output end and the second output end respectively according to different types of data lines accessed by the interface module; and the processor is respectively connected with the first output end and the second output end and is used for acquiring the level signals output by the first output end and the second output end and identifying the type of the data line accessed by the interface module according to the output level signals. Through above-mentioned data line identification circuit, can realize data transmission function and charging function simultaneously, improve user's experience degree.

Description

Data line identification circuit, method and terminal

technical field

The present application relates to the field of data interface technology, in particular to a data line identification circuit, method and terminal.

Background technique

At present, the vast majority of mobile terminals (electronic devices such as mobile phones or tablet computers) use Micro-USB interfaces, and users can use the OTG function through the Micro-USB interface to realize data transmission or charge them. The USD_ID pin of the Micro-USB interface is used to identify whether the connected data line is used for charging or data transmission.

However, the traditional Micro-USB interface only uses one USB_ID pin. When the OTG function is used, the charging cannot be realized, which brings inconvenience to the user.

Contents of the invention

Embodiments of the present application provide a data line identification circuit, method, and terminal, which can realize the functions of charging and data transmission at the same time.

A data line identification circuit, used to identify the type of data line connected, the type of data line includes OTG data line, charging data line and OTG charging data line;

The interface identification circuit includes:

An interface module, used to access the OTG data line, the charging data line and the OTG charging data line;

The debugging module is connected with the interface module, and the debugging module includes a first output terminal and a second output terminal, which are used to connect different data line types according to the interface module, and respectively output corresponding level signals to the Describe the first output end and the second output end;

a processor, connected to the first output terminal and the second output terminal respectively, and used to obtain the level signals output by the first output terminal and the second output terminal, and identify the The type of the data line connected to the interface module.

A data line identification method, used to identify the type of data line connected, the type of the data line includes OTG data line, charging data line and OTG charging data line; the identification method is based on the data line identification circuit, the The data line identification circuit includes an interface module, a debugging module and a processor connected in sequence; the debugging module includes a first output terminal and a second output terminal;

When the interface module is respectively connected to the OTG data line, the charging data line and the OTG charging data line, the debugging module outputs corresponding level signals to the first output terminal and the second output terminal respectively;

The processor obtains the level signals output by the first output terminal and the second output terminal;

The processor identifies the type of the data line connected to the interface module according to the preset data line type and the truth table of the level signals output by the first output terminal and the second output terminal.

A terminal includes the above-mentioned data line identification circuit.

Through the above data line identification circuit, method and terminal, the OTG charging data line that can simultaneously realize the charging function and data transmission function can be identified without affecting the normal identification of the charging data line and the OTG data line of the interface module. That is, through the above-mentioned data line identification circuit, the data transmission function and the charging function can be realized at the same time, which improves user experience.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is a structural frame diagram of a data line identification circuit in an embodiment;

Fig. 2 is a circuit schematic diagram of a data line identification circuit in an embodiment;

Fig. 3 is a flowchart of an embodiment of a data line identification method;

FIG. 4 is a block diagram of a partial structure of a mobile phone related to a terminal.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

As shown in Figure 1, the present application provides a data line identification circuit, which is used to identify the type of data line connected, wherein the type of data line includes: OTG data line, charging data line and OTG charging data Wire. The data line identification circuit is applied to a terminal with an OTG function, wherein the terminal can be a mobile phone, a tablet computer or other electronic devices with an OTG function. The data line identification circuit can realize the parallel execution of the OTG function and the charging function.

Among them, in the OTG data cable, OTG is the abbreviation of On-The-Go, and the OTG data cable is mainly used to connect the OTG device to realize the OTG function to transmit data. The charging data cable can be used to connect the power adapter to realize the charging function; the OTG charging data cable is used to connect special devices that can realize both charging and data transmission functions.

In one embodiment, the interface identification circuit includes an interface module 110 , a debugging module 120 and a processor 130 . Wherein, the interface module 110 is used to access the OTG data line, the charging data line and the OTG charging data line; the debugging module 120 is connected to the interface module 110, and the debugging module 120 includes a first output terminal TP1 and a second output terminal TP2 for use in According to the different data line types connected to the interface module 110, the corresponding level signals are respectively output to the first output terminal TP1 and the second output terminal TP2; the processor 130 is respectively connected to the first output terminal TP1 and the second output terminal The TP2 connection is used to identify the level signals output by the first output terminal TP1 and the second output terminal TP2, and identify the type of the data line connected to the interface module 110 according to the output level signals.

Through the above-mentioned data line identification circuit, the OTG charging data line that can simultaneously realize the charging function and the data transmission function can be identified without affecting the normal identification of the charging data line and the OTG data line of the interface module 110 . That is, the data transmission function and the charging function can be realized simultaneously through the above-mentioned data line identification circuit.

In one embodiment, the interface module 110 at least includes an identification interface for an OTG data line and a charging data line, and the identification interface is connected to the debugging module 120 .

It should be noted that the interface module 110 is a Micro-USB interface, wherein the Micro-USB interface has 5 signal pins in total, which are: a power supply pin (VBUS), an identification data line pin (USB_ID), and a pin for forward transmission Data pin (D+), negative transfer data pin (D-), and ground pin (GND). That is, the identification interface in the interface module 110 is the identification data line pin (USB_ID) in the Micro-USB interface.

When the OTG data line connected to the OTG device is connected to the interface module 110, it is equivalent to the USB_ID pin being grounded in the OTG device; when the charging data line connected to the power adapter is connected to the interface module 110, it is equivalent to being in the power adapter The USB_ID pin is floating; when the OTG charging data line connected to the special device is connected to the interface module 110, it is equivalent to the USB_ID pin being grounded through the resistor R6 in the special device.

As shown in FIG. 2 , in one embodiment, the debugging module 120 further includes a first switching transistor Q1 , a second switching transistor Q2 and a debugging unit 121 . The first switching tube Q1 includes a first control terminal, a first connection terminal and a second connection terminal, the first control terminal is connected to the interface module 110 via the debugging unit 121; the first connection terminal is connected to the first power supply module 140, the first output The terminal TP1 is connected; the second connection terminal is grounded. The second switching tube Q2 includes a second control terminal, a third connection terminal and a fourth connection terminal, the second control terminal is respectively connected to the interface module 110 and the debugging unit 121, and the third connection terminal is respectively connected to the first power supply module 140, the second The output terminal TP2 is connected; the fourth connection terminal is grounded.

The debugging unit 121 controls the working states of the first switch Q1 and the second switch Q2 according to the type of the data line connected to the interface module 110 to output corresponding level signals to the first output terminal TP1 and the second output terminal TP2 .

Further, both the first switch tube Q1 and the second switch tube Q2 are MOS tubes. Wherein, the gate of the first switching transistor Q1 is the first control terminal, the drain of the first switching transistor Q1 is the first connecting terminal, the source of the first switching transistor Q1 is the second connecting terminal; the gate of the second switching transistor Q2 is the second connecting terminal. Two control terminals, the drain of the second switch transistor Q2 is the third connection terminal, and the source of the second switch transistor Q2 is the fourth connection terminal. That is, the gate of the first switching transistor Q1 is connected to the USB_ID pin of the interface module 110, the drain of the first switching transistor Q1 is respectively connected to the first power module 140 and the first output terminal TP1, and the first switching transistor Q1 Source ground. The gate of the second switching tube Q2 is connected to the USB_ID pin of the interface module 110, the drain of the second switching tube Q2 is respectively connected to the first power module 140 and the second output terminal TP2, and the source of the second switching tube Q2 is grounded . Wherein, the first power supply module 140 is used to supply power to the processor 130 to meet the power supply requirements of the processor 130 .

It can be further understood that both the first switch tube Q1 and the second switch tube Q2 are MOS tubes, and the conduction voltage drop of the MOS tubes is V ₀ . When the voltage drop V _GS of the gate and source of the MOS transistor is less than V ₀ , the MOS transistor is not turned on and is in an off state. At this time, the resistance of the drain and source of the MOS transistor is equivalent to infinite. When the voltage drop V _GS of the gate and source of the MOS transistor is greater than V ₀ , the MOS transistor is turned on. At this time, the impedance of the drain and source of the MOS transistor is equivalent to 0ohm.

Wherein, when the first switch tube Q1 is turned on, the level signal output by its first output terminal TP1 is a low level signal; when the first switch tube Q1 is turned off, the level signal output by its first output terminal TP1 is high level signal. Correspondingly, when the second switch tube Q2 is turned on, the level signal output by its second output terminal TP2 is a low level signal; when the second switch tube Q2 is turned off, the level signal output by its second output terminal TP2 is a high level signal.

The debugging unit 121 controls the working state (on or off) of the first switch tube Q1 and the second switch tube Q2 according to the type of the data line connected to the interface module 110 to output corresponding level signals to the first output terminal TP1, the second output terminal TP1, and the second switch tube Q2. Two output terminals TP2.

Optionally, the first switching tube Q1 and the second switching tube Q2 may also be triodes or other electronic switching tubes with conduction voltage.

In one embodiment, the processor 130 is provided with multiple GPIO interfaces, and the first output terminal TP1 and the second output terminal TP2 of the processor 130 are respectively connected to the two GPIO interfaces on the processor 130 .

The processor 130 receives the level signals output by the first output terminal TP1 and the second output terminal TP2, and the processor 130 can be based on the type of the stored data line and the true level signal output by the first output terminal TP1 and the second output terminal TP2. A table of values (shown in Table 1 ), identifying the type of data line plugged into the interface module 110 .

Table 1 is the truth table of the data line type and the level signals output by the first output terminal TP1 and the second output terminal TP2

Type of data cable First output terminal TP1 Second output TP2 OTG data cable 1 1 charging data cable 0 0 OTG charging data cable 0 1

Specifically, when the level signals output by the first output terminal TP1 and the second output terminal TP2 are both high level, the data line is an OTG data line; when the level signals output by the first output terminal TP1 and the second output terminal TP2 When both are low level, the data line is the charging data line; when the level signal output by the first output terminal TP1 is low level, and the level signal output by the second output terminal TP2 is high level, the data line is OTG charging data line.

Through the above-mentioned data line identification circuit, the processor 130 can identify the type of the data line inserted into the interface module 110 according to the level signals output by the first output terminal TP1 and the second output terminal TP2, that is, it can identify the OTG data cable with transmission function, charging data cable with charging function, and OTG charging data cable with both data transmission function and charging function. That is, through the above-mentioned data line identification circuit, the parallel execution of the data transmission function and the charging function can be realized at the same time.

In one embodiment, the debugging module includes a first resistor R1 , a second resistor R2 and a third resistor R3 connected in sequence, and the first resistor R1 , the second resistor R2 and the third resistor R3 are used for voltage division. One end of the first resistor R1 is connected to the second power module 140, the common end of the first resistor R1 and the second resistor R2 are connected to the first control end; the common ends of the second resistor R2 and the third resistor R3 are respectively connected to the interface module 110 , the second control end, and the other end of the third resistor R3 is grounded. Wherein, the second power supply module 140 is a direct current power supply module, and its output direct current voltage is denoted by V2, and V2 may be 3.3 volts.

When the USB_ID pin of the interface module 110 interfaces with the OTG data line, the voltage V _G1 of the gate of the first switching transistor Q1 = V2*R2/(R1+R2), the gate voltage of the second switching transistor Q2 is 0V, and the second The switch tube Q2 is not turned on.

When the USB_ID pin interface charging data line of the interface module 110, the voltage V _{G1 '} =V2*R3/(R1+R2+R3) of the gate voltage of the first switch tube Q1; the gate voltage of the second switch tube Q2 is V _G2' =V2*(R2+R3)/(R1+R2+R3).

Because, when the OTG charging data line connected to the special device is connected to the interface module 110, it is equivalent to grounding the USB_ID pin of the special device through the resistor R6. When the USB_ID pin of the interface module 110 interfaces with the OTG charging data line, the impedance R _X of the gate of the second switching transistor Q2 to ground = R6*R3/(R6+R3), at this time, the gate of the first switching transistor Q1 The voltage V _G1 ″=V2*(R2+Rx)/(R1+R2+Rx), the voltage V _G2 ″=V2*Rx/(R1+R2+Rx) on the gate of the second switching transistor Q2.

When the level signals output by the first output terminal TP1 and the second output terminal TP2 are both high level, it can be determined that the data line connected to the interface module 110 is an OTG data line; Both the second switch tubes Q2 are in a cut-off state (non-conductive), and the condition V _G1 =V2*R2/(R1+R2)<V ₀ can be satisfied.

When the level signals output by the first output terminal TP1 and the second output terminal TP2 are both low level, the data line is a charging data line; that is, it is necessary to make the first switching tube Q1 and the second switching tube Q2 both in conduction The state satisfies the condition V _G1' =V2*R3/(R1+R2+R3)>V ₀ ; V2*(R2+R3)/(R1+R2+R3)>V ₀ .

When the level signal output by the first output terminal TP1 is low level and the level signal output by the second output terminal TP2 is high level, the data line is an OTG charging data line. That is, it is necessary to make the first switching tube Q1 in the conduction state and the second switching tube Q2 in the off state (non-conducting), satisfying the condition: V _G1 "=V2*(R2+Rx)/(R1+R2+ Rx)>V ₀ ; V _G2 ″=V1*Rx/(R1+R2+Rx)<V ₀ .

By setting reasonable resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the resistor R6 in the voltage dividing unit, when the interface module 110 is plugged into different types of data lines, the processor 130 can use the first The level signal output by the output terminal TP1 and the second output terminal TP2 can determine the type of the data line inserted into the interface module 110 .

In one embodiment, the debugging module 120 further includes a first pull-up resistor R4 and a second pull-up resistor R5. One end of the first pull-up resistor R4 is connected to the first power module 140, and the other end of the first pull-up resistor R4 is respectively connected to the first output terminal TP1 and the first connection end; one end of the second pull-up resistor R5 is connected to the first The power module 140 is connected, and the other end of the second pull-up resistor R5 is respectively connected to the second output terminal TP2 and the third connection end. Wherein, the resistance values of the first pull-up resistor R4 and the second pull-up resistor R5 are both 10k ohms.

The present application also provides a data line identification method, which is used to identify the type of the connected data line, and the types of the data line are OTG data line, charging data line and OTG charging data line.

It should be noted that in the OTG data cable, OTG is the abbreviation of On-The-Go, and the OTG data cable is mainly used to connect OTG devices to realize the OTG function for data transmission. The charging data cable can be used to connect the power adapter to realize the charging function; the OTG charging data cable is used to connect special devices that can realize both charging and data transmission functions.

The data line identification method is based on a data line identification circuit. The data line identification circuit includes an interface module, a debugging module and a processor connected in sequence; the debugging module includes a first output terminal and a second output terminal.

Data line identification methods include:

Step 302: When the interface module is respectively connected to the OTG data line, the charging data line and the OTG charging data line, the debugging module outputs corresponding level signals to the first output end and the second output end respectively.

Specifically, the interface module is a Micro-USB interface, wherein the Micro-USB interface has a total of 5 signal pins, which are: a power supply pin (VBUS), an identification data line pin (USB_ID), and a pin for transmitting data. (D+), negative transfer data pin (D-), and ground pin (GND). That is, the identification interface in the interface module is the identification data line pin (USB_ID) in the Micro-USB interface, which is connected to the debugging module.

When the OTG data line connected to the OTG device is connected to the interface module, it is equivalent to the USB_ID pin being grounded in the OTG device; when the charging data line connected to the power adapter is connected to the interface module, it is equivalent to the USB_ID pin in the power adapter. The pin is floating; when the OTG charging data line connected to the special device is connected to the interface module, it is equivalent to the USB_ID pin in the special device being grounded through a resistor.

When the interface module is respectively connected to any one of the OTG data line, the charging data line and the OTG charging data line, the debugging module will output corresponding level signals to the first output terminal, the second Two output terminals.

Step 304: The processor acquires level signals output from the first output terminal and the second output terminal.

In one embodiment, the processor is provided with a plurality of GPIO interfaces, and the first output end and the second output end thereof are correspondingly connected to two GPIO interfaces on the processor.

The processor correspondingly receives the level signals output from the first output terminal and the second output terminal through the two GPIO interfaces.

Step 306: The processor identifies the type of the data line connected to the interface module according to the preset data line type and the truth table of the level signals output by the first output terminal and the second output terminal.

The processor receives the level signals output by the first output terminal and the second output terminal, and the processor can use the stored data line type and the truth table of the level signals output by the first output terminal and the second output terminal (as shown in Table 1) shown), to identify the type of data cable plugged into the interface module.

Specifically, when the level signals output by the first output terminal and the second output terminal received by the processor are both high level, the data line is an OTG data line; when the first output terminal and the second output terminal received by the processor When the level signals output by the terminal are all low level, the data line is the charging data line; when the level signal output by the first output terminal received by the processor is low level, and the level signal output by the second output terminal is When the level is high, the data line is an OTG charging data line.

Through the above data line identification method, the processor can identify the type of data line inserted into the interface module according to the level signals output by the first output terminal and the second output terminal, that is, it can identify the OTG with data transmission function. Data cable, charging data cable with charging function, and OTG charging data cable with both data transmission function and charging function. That is, through the above-mentioned data line identification method, the parallel execution of the data transmission function and the charging function can be realized at the same time.

In one embodiment, the debugging module further includes a first switch tube, a second switch tube, and a debugging unit; wherein, the first switch tube includes a first control terminal, a first connection terminal, and a second connection terminal, and the first control terminal is connected via The debugging unit is connected to the interface module; the first connection terminal is respectively connected to the first power module and the first output terminal; the second connection terminal is grounded; the second switch tube includes a second control terminal, a third connection terminal and a fourth connection terminal, The second control terminal is respectively connected with the interface module and the debugging unit; the third connection terminal is respectively connected with the first power supply module and the second output terminal; the fourth connection terminal is grounded.

Further, both the first switch tube and the second switch tube are MOS tubes. Wherein, the gate of the first switch tube is the first control terminal, the drain of the first switch tube is the first connection terminal, and the source of the first switch tube is the second connection terminal; the gate of the second switch tube is the second control terminal, The drain of the second switch transistor is the third connection end, and the source of the second switch transistor is the fourth connection end. That is, the gate of the first switch tube is connected to the USB_ID pin of the interface module, the drain of the first switch tube is connected to the first power module and the first output terminal respectively, and the source of the first switch tube is grounded. The gate of the second switch tube is connected to the USB_ID pin of the interface module, the drain of the second switch tube is respectively connected to the first power module and the second output terminal, and the source of the second switch tube is grounded. Wherein, the first power supply module is used to supply power to the processor, so as to meet the power supply requirement of the processor.

Specifically, when the first switch tube is turned on, the level signal output by the first output terminal is low level; when the first switch tube is turned off, the level signal output by the first output terminal is high level; When the two switch tubes are turned on, the level signal output by the second output terminal is low level; when the second switch tube is turned off, the level signal output by the second output terminal is high level.

The debugging unit controls the working state (on or off) of the first switch tube and the second switch tube according to the type of the data line connected to the interface module to output corresponding level signals to the first output terminal and the second output terminal.

In one embodiment, the debugging module includes a first resistor R1 , a second resistor R2 and a third resistor R3 connected in sequence, and the first resistor R1 , the second resistor R2 and the third resistor R3 are used for voltage division. One end of the first resistor R1 is connected to the second power module, the common end of the first resistor R1 and the second resistor R2 are connected to the first control end; the common ends of the second resistor R2 and the third resistor R3 are respectively connected to the interface module, the second The two control terminals are connected, and the other end of the third resistor R3 is grounded. Wherein, the second power supply module is a DC power supply module, and its output DC voltage is denoted by V2, and V2 may be 3.3 volts.

When the USB_ID pin of the interface module interfaces with the OTG data line, the voltage V _G1 of the gate of the first switch tube = V2*R2/(R1+R2), the gate voltage of the second switch tube is 0V, and the second switch tube does not conduction.

When the USB_ID pin of the interface module 110 interfaces with the charging data line, the voltage V _G1' of the gate of the first switch tube = V2*R3/(R1+R2+R3); the gate voltage of the second switch tube is V _G2' =V2*(R2+R3)/(R1+R2+R3).

Because, when the OTG charging data line connected to the special device is connected to the interface module, it is equivalent to grounding the USB_ID pin in the special device through the resistor R6. When the USB_ID pin of the interface module is connected to the OTG charging data line, the impedance R _X of the grid of the second switching tube to ground = R6*R3/(R6+R3), at this time, the voltage V of the grid of the first switching tube _G1 ″=V2*(R2+Rx)/(R1+R2+Rx), the voltage V _G2 ″=V2*Rx/(R1+R2+Rx) on the gate of the second switching tube.

When the level signals output by the first output terminal and the second output terminal are both high level, it can be judged that the data line connected to the interface module is an OTG data line; that is, it is necessary to make the first switch tube and the second switch tube All are in the cut-off state (non-conductive), and condition 1 is satisfied: V _G1 =V2*R2/(R1+R2)<V ₀ .

When the level signals output by the first output terminal and the second output terminal are both low level, the data line is a charging data line; that is, it is necessary to make the first switch tube and the second switch tube both in the conducting state, so as to obtain the satisfaction Condition 2: V _G1' = V2*R3/(R1+R2+R3)>V ₀ ; V2*(R2+R3)/(R1+R2+R3)>V ₀ .

When the level signal output by the first output terminal is low level and the level signal output by the second output terminal is high level, the data line is an OTG charging data line. That is, it is necessary to make the first switch tube in the conduction state and the second switch tube in the off state (non-conduction), so as to obtain and satisfy the condition 3: V _G1 "=V2*(R2+Rx)/(R1+R2+ Rx)>V ₀ ; V _G2 ″=V1*Rx/(R1+R2+Rx)<V ₀ .

When the conditions 1, 2, and 3 are met simultaneously, calculate the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, and the resistor R6 in the voltage dividing unit, and assign the corresponding resistors. When the interface module is plugged into different types of data lines, the processor can identify the OTG data line with data transmission function, the charging data line with charging function and simultaneously according to the level signals output by the first output terminal and the second output terminal OTG charging data cable with data transmission function and charging function. That is, through the above-mentioned data line identification method, the parallel execution of the data transmission function and the charging function can be realized at the same time.

The present application also provides a terminal, which has an OTG function, and the terminal includes the data line identification circuit in any one of the above embodiments. By setting the data line identification circuit in the terminal, the OTG data line with data transmission function, the charging data line with charging function and the OTG charging data line with both data transmission function and charging function can be identified. That is to say, the terminal simultaneously implements the parallel transmission of the data transmission function and the charging function through the OTG charging data line.

As shown in FIG. 4 , for the convenience of description, only the parts related to the embodiment of the present application are shown. For specific technical details not disclosed, please refer to the method part of the embodiment of the present application. The terminal can be any terminal device including mobile phone, tablet computer, PDA (Personal Digital Assistant, personal digital assistant), POS (Point of Sales, sales terminal), vehicle-mounted computer, wearable device, etc. Taking the terminal as a mobile phone as an example:

Fig. 4 is a block diagram of a partial structure of a mobile phone related to a terminal provided by an embodiment of the present application. Referring to FIG. 4 , the mobile phone includes: a radio frequency (Radio Frequency, RF) circuit 410, a memory 420, an input unit 430, a display unit 440, a sensor 450, an audio circuit 460, a wireless fidelity (wireless fidelity, WiFi) module 470, and a processor 480 , and power supply 490 and other components. Those skilled in the art can understand that the structure of the mobile phone shown in FIG. 4 does not constitute a limitation to the mobile phone, and may include more or less components than shown in the figure, or combine some components, or arrange different components.

Among them, the RF circuit 410 can be used for sending and receiving information or receiving and sending signals during a call. After receiving the downlink information from the base station, it can be processed by the processor 480; it can also send uplink data to the base station. Generally, an RF circuit includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (Low Noise Amplifier, LNA), a duplexer, and the like. In addition, RF circuitry 410 may also communicate with networks and other devices via wireless communications. The above-mentioned wireless communication can use any communication standard or protocol, including but not limited to Global System of Mobile Communication (Global System of Mobile communication, GSM), General Packet Radio Service (General Packet Radio Service, GPRS), Code Division Multiple Access (Code Division Multiple Access, CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), etc.

The memory 420 can be used to store software programs and modules, and the processor 480 executes various functional applications and data processing of the mobile phone by running the software programs and modules stored in the memory 420 . The memory 420 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required by at least one function (such as an application program for a sound playback function, an application program for an image playback function, etc.), etc.; The data storage area can store data created according to the use of the mobile phone (such as audio data, address book, etc.) and the like. In addition, the memory 420 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage devices.

The input unit 430 can be used to receive input numbers or character information, and generate key signal input related to user settings and function control of the mobile phone 400 . Specifically, the input unit 430 may include a touch panel 431 and other input devices 432 . The touch panel 431, which can also be referred to as a touch screen, can collect touch operations of the user on or near it (for example, the user uses any suitable object or accessory such as a finger or a stylus on the touch panel 431 or near the touch panel 431 operation), and drive the corresponding connection device according to the preset program. In one embodiment, the touch panel 431 may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch orientation, and detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and sends it to the to the processor 480, and can receive and execute commands sent by the processor 480. In addition, the touch panel 431 can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 431 , the input unit 430 may further include a data line identification circuit 432 . The display unit 440 may be used to display information input by or provided to the user and various menus of the mobile phone. The display unit 440 may include a display panel 441 . In one embodiment, the display panel 441 may be configured in the form of a Liquid Crystal Display (Liquid Crystal Display, LCD), an Organic Light-Emitting Diode (Organic Light-Emitting Diode, OLED), or the like. In one embodiment, the touch panel 431 can cover the display panel 441, and when the touch panel 431 detects a touch operation on or near it, it transmits to the processor 480 to determine the type of the touch event, and then the processor 480 according to The type of touch event provides a corresponding visual output on the display panel 441 . Although in FIG. 4 , the touch panel 431 and the display panel 441 are used as two independent components to realize the input and input functions of the mobile phone, in some embodiments, the touch panel 431 and the display panel 441 can be integrated to form a mobile phone. Realize the input and output functions of the mobile phone.

Cell phone 400 may also include at least one sensor 450, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor can include an ambient light sensor and a proximity sensor, wherein the ambient light sensor can adjust the brightness of the display panel 441 according to the brightness of the ambient light, and the proximity sensor can turn off the display panel 441 and/or when the mobile phone is moved to the ear. or backlight. The motion sensor can include an acceleration sensor, through which the magnitude of acceleration in various directions can be detected, and the magnitude and direction of gravity can be detected when stationary, and can be used for applications that recognize the attitude of a mobile phone (such as switching between horizontal and vertical screens), vibration recognition related functions (such as pedometer, tap), etc.; in addition, the mobile phone can also be equipped with gyroscope, barometer, hygrometer, thermometer, infrared sensor and other sensors.

Audio circuitry 460, speaker 461 and microphone 462 may provide an audio interface between the user and the handset. The audio circuit 460 can transmit the electrical signal converted from the received audio data to the loudspeaker 461, and the loudspeaker 461 converts it into an audio signal output; After being received, it is converted into audio data, and after being processed by the output processor 480, the audio data can be sent to another mobile phone through the RF circuit 410, or the audio data can be output to the memory 420 for subsequent processing.

WiFi is a short-distance wireless transmission technology. The mobile phone can help users send and receive emails, browse web pages, and access streaming media through the WiFi module 470, which provides users with wireless broadband Internet access. Although FIG. 4 shows the WiFi module 470, it can be understood that it is not an essential component of the mobile phone 400 and can be omitted as required.

The processor 480 is the control center of the mobile phone. It uses various interfaces and lines to connect various parts of the entire mobile phone. By running or executing software programs and/or modules stored in the memory 420, and calling data stored in the memory 420, execution Various functions and processing data of the mobile phone, so as to monitor the mobile phone as a whole. In one embodiment, processor 480 may include one or more processing units. In one embodiment, the processor 480 may integrate an application processor and a modem processor, wherein the application processor mainly processes operating systems, user interfaces, and application programs, etc.; the modem processor mainly processes wireless communications. It can be understood that the foregoing modem processor may not be integrated into the processor 480 .

The mobile phone 400 also includes a power supply 490 (such as a battery) for supplying power to various components. Preferably, the power supply can be logically connected to the processor 480 through the power management system, so that functions such as charging, discharging, and power consumption management can be realized through the power management system.

In one embodiment, the mobile phone 400 may also include a camera, a Bluetooth module, and the like.

Any reference to memory, storage, database, or other medium as used herein may include non-volatile and/or volatile memory. Suitable nonvolatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is relatively specific and detailed, but should not be construed as limiting the patent scope of the present application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the scope of protection of the patent application should be based on the appended claims.

Claims (10)

1. a kind of data wire identification circuit, it is characterised in that for the type for the data wire for identifying access, the class of the data wire Type includes OTG data wires, charging data line and OTG charging data lines；

The interface identification circuit, including：

Interface module, for accessing the OTG data wires, charging data line and OTG charging data lines；

Debugging module, it is connected with the interface module, the debugging module includes the first output end and the second output end, for root Different data wire types is accessed according to the interface module, corresponds to the corresponding level signal of output respectively to the described first output End, the second output end；

Processor, it is connected respectively with first output end, the second output end, for obtaining first output end, second defeated Go out to hold the level signal of output, and the data wire accessed according to the level signal of the output identification interface module Type.

2. data wire identification circuit according to claim 1, it is characterised in that the debugging module, in addition to first open Guan Guan, second switch pipe and debugging unit；

The first switch pipe includes the first control terminal, the first connection end and second connection end, described in the first control terminal warp Debugging unit is connected with the interface module；First connection end is connected with the first power module, the first output end respectively；Institute State second connection end ground connection；

The second switch pipe includes the second control terminal, the 3rd connection end and the 4th connection end, second control terminal respectively with The interface module, debugging unit connection, the 3rd connection end connect with first power module, the second output end respectively Connect；The 4th connection end ground connection；

The debugging unit, the type of the data wire for being accessed according to the interface module control the first switch respectively Pipe, the working condition of second switch pipe are to export corresponding level signal to first output end, the second output end.

3. data wire identification circuit according to claim 2, it is characterised in that the debugging module debugging unit include according to First resistor, second resistance and the 3rd resistor of secondary connection；

One end of the first resistor is connected with second source module, the first resistor, second resistance common port with it is described First control terminal connects；The second resistance, the common port of 3rd resistor connect with the interface module, the second control terminal respectively Connect, the other end ground connection of the 3rd resistor.

4. data wire identification circuit according to claim 2, it is characterised in that the first switch pipe, second switch pipe It is metal-oxide-semiconductor；

The grid of the first switch pipe is first control terminal, and the drain electrode of the first switch pipe is the described first connection End, the source electrode of the first switch pipe are the second connection end；

The grid of the second switch pipe is second control terminal, and the drain electrode of the second switch pipe is the described 3rd connection End, the source electrode of the second switch pipe are the 4th connection end.

5. data wire identification circuit according to claim 2, it is characterised in that the debugging module also includes the first pull-up Resistance and the second pull-up resistor；

One end of first pull-up resistor is connected with first power module, the other end difference of first pull-up resistor It is connected with first output end, first connection end；

One end of second pull-up resistor is connected with first power module, the other end difference of second pull-up resistor It is connected with second output end, the 3rd connection end.

6. data wire identification circuit according to claim 1, it is characterised in that the interface module, which comprises at least, to be used to know Not described OTG data wires, the identification interface of charging data line, the identification interface are connected with the debugging module.

7. a kind of data wire recognition methods, it is characterised in that for the type for the data wire for identifying access, the class of the data wire Type includes OTG data wires, charging data line and OTG charging data lines；The recognition methods is based on data wire identification circuit, described Data wire identification circuit, including interface module, debugging module and the processor being sequentially connected；It is defeated that the debugging module includes first Go out end and the second output end；

When the interface module is respectively connected to OTG data wires, charging data line and OTG charging data lines, the debugging module The corresponding level signal of output is corresponded to respectively to first output end, the second output end；

The processor obtains first output end, the level signal of the second output end output；

The level signal that the processor exports according to default data wire type and first output end, the second output end Truth table, identify the type of the data wire of the interface module access.

8. data wire recognition methods according to claim 7, it is characterised in that the identification interface module access The type of the data wire, including：

When the level signal that first output end, the second output end export is high level, the data wire is OTG data Line；

When the level signal that first output end, the second output end export is low level, the data wire is charging number According to line；

When the level signal of first output end output is that the level signal that low level and the second output end export is high level When, the data wire is OTG charging data lines.

9. data wire recognition methods according to claim 8, it is characterised in that the debugging module also includes first switch Pipe, second switch pipe and debugging unit；Wherein, the first switch pipe includes the first control terminal, the first connection end and second connects End is connect, first control terminal is connected through the debugging unit with the interface module；First connection end is respectively with first Power module, the connection of the first output end；The second connection end ground connection；The second switch pipe includes the second control terminal, the 3rd Connection end and the 4th connection end, second control terminal are connected with the interface module, debugging unit respectively, the 3rd connection End is connected with first power module, the second output end respectively；The 4th connection end ground connection；

When the first switch pipe turns on, the level signal of the first output end output is low level；

When the first switch pipe ends, the level signal of the first output end output is high level；

When the second switch pipe turns on, the level signal of the second output end output is low level；

When the second switch pipe ends, the level signal of the second output end output is high level.

10. a kind of terminal, it is characterised in that including the data wire identification circuit as described in any in claim 1~6.