CN107611045A - A kind of three-dimensional chip encapsulating structure and its method for packing - Google Patents

Abstract

The invention provides a three-dimensional chip packaging structure and a packaging method thereof. The packaging structure adopts a packaging form of a packaging substrate, a perforated silicon interposer, and stacked bare chips, and uses a plastic sealing layer to realize the protection of the bare chips, wherein the bare chip and the through hole The silicon interposer can be connected through conductive bumps and redistribution layers. The packaging structure has the advantages of simple structure, higher I/O density, and faster transmission efficiency. The encapsulation method firstly adheres a perforated silicon interposer on a carrier substrate, and then mounts the die face down on the perforated silicon interposer, and forms an adhesive layer covering the die and the perforated silicon interposer on the adhesive layer. Layer plastic encapsulation layer, then remove the carrier substrate and adhesive layer to obtain a three-dimensional chip module including perforated silicon interposer, die and plastic encapsulation layer, and finally provide a packaging substrate, and install the three-dimensional chip module on the side with perforated silicon interposer on the packaging substrate. The encapsulation method has low process complexity, which is beneficial to reduce production cost and improve encapsulation yield.

Description

A three-dimensional chip packaging structure and packaging method thereof

technical field

The invention belongs to the field of semiconductor packaging and relates to a packaging method for a three-dimensional chip packaging structure.

Background technique

The semiconductor industry continues to increase the integration density of various electronic components by continuously reducing the minimum feature size, so that more electronic components can be integrated in a given area. Currently, the most advanced packaging solutions include wafer level chip-scale package (Wafer level chip-scale package), fan-out wafer level package (Flip chip) and stacked package ( Package on Package, POP) and so on.

Traditional fan-out wafer level packaging (FOWLP) generally includes the following steps: First, a single microchip is cut from the wafer, and the chip is attached face-down to the carrier using standard pick-and-place equipment On the adhesive layer; then form a plastic sealing layer, embed the chip in the plastic sealing layer; after the plastic sealing layer is cured, remove the carrier and the adhesive layer, then perform the redistribution lead layer process and ball planting reflow process, and finally cut and test. The redistribution layer (Redistribution Layers, RDL) is the interface between the chip and the package in the flip chip assembly. The redistribution lead layer is an additional metal layer consisting of core metal top traces used to bond out the I/O pads of the die to other locations such as bump pads. The bumps are typically arranged in a grid pattern, and each bump is molded with two pads (one on top and one on the bottom) that connect the redistribution lead layer and the package substrate, respectively. Traditional fan-out wafer-level packaging is prone to misalignment between the chip and the RDL layer, resulting in lower yield.

Stacked packaging (Package on Package, PoP) can vertically stack multiple chips in a single package, combine vertically separated logic and storage ball grid arrays, and transmit signals through standard interfaces between stacked packages to realize component The doubling of density enables a single package to achieve more functions, and is widely used in mobile phones, personal digital assistants (PDAs), digital cameras and other fields.

In advanced packaging, through-silicon via (TSV) technology has a significant impact, which is a vertical electrical connection technology that penetrates a substrate (especially a silicon substrate). TSV can replace wire bonding (Wire-Bonding) in almost all packages, and improve the electrical performance of all types of chip packages, including improving integration and reducing chip size, especially in System-in-Packaging (System-in-Packaging, SiP), wafer-level packaging (Wafer-Level Packaging-WLP) and three-dimensional vertical stack packaging (3D Packaging) among these advanced packages. The manufacture of TSV includes the manufacture of through holes, the deposition of insulating layers, the filling of through holes, and the subsequent processes of chemical mechanical planarization (CMP) and redistribution (RDL). The traditional stacked packaging is related to the TSV process, which requires a series of complicated manufacturing processes, resulting in higher production costs and lower yields.

Therefore, how to provide a new three-dimensional chip packaging structure and its packaging method to increase I/O density, reduce production costs, and improve yield has become an important technical problem to be solved urgently by those skilled in the art.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional chip packaging structure and its packaging method, which are used to solve the problems of low I/O density and complicated packaging methods in the prior art.

In order to achieve the above purpose and other related purposes, the present invention provides a packaging method for a three-dimensional chip packaging structure, comprising the following steps:

providing a carrier substrate;

forming an adhesive layer on the carrier substrate;

adhering a perforated silicon interposer on the adhesive layer, the perforated silicon interposer comprising an insulating substrate and a plurality of conductive pillars penetrating the insulating substrate up and down;

providing at least one die mounted face down on the TSIF;

forming a plastic encapsulation layer covering the die and the perforated silicon interposer on the adhesive layer;

removing the carrier substrate and the adhesive layer to obtain a three-dimensional chip module including the perforated silicon interposer, the die and the plastic encapsulation layer;

An encapsulation substrate is provided, and the side of the three-dimensional chip module having the perforated silicon interposer is installed on the encapsulation substrate.

Optionally, there is a gap between the three-dimensional chip module and the packaging substrate; after the three-dimensional chip module is mounted on the packaging substrate, a step of forming a protective layer in the gap is also included.

Optionally, after adhering the perforated silicon interposer on the adhesive layer, further comprising the step of forming a rewiring layer on the perforated silicon interposer, so that the die passes through the rewiring layer It is electrically connected with the through-silicon interlayer.

Optionally, the rewiring layer includes at least one patterned dielectric layer and at least one patterned metal wiring layer.

Optionally, conductive bumps are provided on the front side of the bare chip, and the bare chip is electrically connected to the rewiring layer through the conductive bumps.

Optionally, after forming a rewiring layer on the through-hole silicon interposer, further comprising the step of forming a bump structure on the rewiring layer, so that the die passes through the bump structure and the rewiring layer. The wiring layer is electrically connected.

Optionally, the bump structure includes metal pillars and solder bumps connected above the conductive pillars, or the bump structure only includes solder bumps.

Optionally, a conductive bump is connected to a side of the conductive column facing the adhesive layer, and when the perforated silicon interposer is adhered on the adhesive layer, the conductive bump is embedded in the adhesive layer.

Optionally, the punctured silicon interposer is obtained by cutting a punctured silicon interposer wafer.

The present invention also provides a three-dimensional chip packaging structure, including a packaging substrate and a three-dimensional chip module electrically connected above the packaging substrate, wherein the three-dimensional chip module includes:

The perforated silicon interposer includes an insulating substrate and a plurality of conductive pillars penetrating the insulating substrate up and down, and the conductive pillars are electrically connected to the packaging substrate;

at least one die mounted face down on the TSIL;

The plastic encapsulation layer covers the die and the perforated silicon interposer.

Optionally, there is a gap between the three-dimensional chip module and the packaging substrate, and a protective layer is formed in the gap.

Optionally, a rewiring layer is formed between the die and the TSIF, so that the die is electrically connected to the TSIF through the rewiring layer.

Optionally, the rewiring layer includes at least one patterned dielectric layer and at least one patterned metal wiring layer.

Optionally, conductive bumps are provided on the front side of the bare chip, and the bare chip is electrically connected to the rewiring layer through the conductive bumps.

Optionally, a bump structure is provided on the rewiring layer, so that the die is electrically connected to the rewiring layer through the bump structure; the bump structure includes a metal column and is connected to the Solder bumps above the metal pillars, or the bump structure includes only solder bumps.

Optionally, the conductive pillars are electrically connected to the package substrate through conductive bumps.

As mentioned above, the three-dimensional chip packaging structure and its packaging method of the present invention have the following beneficial effects: the three-dimensional chip packaging structure of the present invention adopts the packaging form of packaging substrate, TSI perforated silicon interposer, and die stacking, and uses a plastic sealing layer to realize The protection of the die, wherein the die and the TSI through-silicon interposer can be connected through conductive bumps and rewiring layers. The three-dimensional chip packaging structure of the present invention has the advantages of simple structure, higher I/O density and faster transmission efficiency. The packaging method of the three-dimensional chip packaging structure of the present invention first adheres the TSI perforated silicon interposer on the carrier substrate, and then mounts the die face down on the perforated silicon interposer, and forms a chip on the adhesive layer. Covering the die and the plastic encapsulation layer of the perforated silicon interposer, and then removing the carrier substrate and the adhesive layer to obtain a three-dimensional chip module including the perforated silicon interposer, the die and the plastic encapsulation layer, Finally, an encapsulation substrate is provided, and the side of the three-dimensional chip module having the perforated silicon interposer is mounted on the encapsulation substrate. The encapsulation method of the three-dimensional chip encapsulation structure of the present invention has low process complexity, which is beneficial to reduce production cost and improve encapsulation yield.

Description of drawings

FIG. 1 shows a process flow chart of the packaging method of the three-dimensional chip packaging structure of the present invention.

FIG. 2 is a schematic diagram of providing a carrier substrate for the packaging method of the three-dimensional chip packaging structure of the present invention.

FIG. 3 is a schematic diagram of forming an adhesive layer on the carrier substrate by the packaging method of the three-dimensional chip packaging structure of the present invention.

FIG. 4 is a schematic diagram of adhering a perforated silicon interposer on the adhesive layer according to the packaging method of the three-dimensional chip packaging structure of the present invention.

FIG. 5 shows a schematic diagram of obtaining the perforated silicon interposer by cutting the perforated silicon interposer wafer for the packaging method of the three-dimensional chip packaging structure of the present invention.

FIG. 6 shows a schematic diagram of providing at least one die for the packaging method of the three-dimensional chip packaging structure of the present invention, and mounting the die face down on the perforated silicon interposer.

7 is a schematic diagram of forming a plastic encapsulation layer covering the die and the perforated silicon interposer on the adhesive layer in the packaging method of the three-dimensional chip packaging structure of the present invention.

FIG. 8 shows a schematic diagram of a three-dimensional chip module including the perforated silicon interposer, the die and the plastic sealing layer obtained by removing the carrier substrate and the adhesive layer in the packaging method of the three-dimensional chip packaging structure of the present invention.

FIG. 9 shows a schematic diagram of providing a packaging substrate for the packaging method of the three-dimensional chip packaging structure of the present invention, and installing the side of the three-dimensional chip module having the perforated silicon interposer on the packaging substrate.

FIG. 10 is a schematic diagram of forming a protective layer in the gap between the three-dimensional chip module and the packaging substrate in the packaging method of the three-dimensional chip packaging structure of the present invention.

Component designation description

S1～S7 steps

1 Carrier substrate

2 Adhesive layer

3 Perforated Silicon Interposer

301 insulating substrate

302 conductive column

303 conductive bumps

4 Through-hole silicon interposer wafer

5 die

6 Conductive bumps

7 plastic layer

8 Package Substrate

9 solder balls

10 layers of protection

detailed description

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 10. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Embodiment one

The present invention provides a packaging method for a three-dimensional chip packaging structure, please refer to Figure 1, which shows a process flow chart of the packaging method, including the following steps:

As shown in FIG. 2 , step S1 is performed: providing a carrier substrate 1 .

Specifically, the carrier substrate 1 can provide a rigid structure or substrate for the subsequent fabrication of the adhesion layer 2 and the adhesion through-hole silicon interposer 3, and its material can be selected from metals, semiconductors (such as Si), polymers or glass. at least one. As an example, the carrier 1 is made of glass.

As shown in FIG. 3 , step S2 is performed: forming an adhesive layer 2 on the carrier substrate 1 .

Specifically, the adhesive layer 2 is used as a separation layer between the perforated silicon interposer 3 and the carrier substrate 1 in the subsequent process, and it is preferably made of an adhesive material with a smooth surface. 3 has a certain bonding force to ensure that the perforated silicon interposer 3 will not move in the subsequent process. In addition, it also has a strong bonding force with the carrier substrate 1. Generally speaking, its connection with the carrier substrate 1 The bonding force needs to be greater than the bonding force with the perforated silicon interposer. The adhesive layer 2 can be a single-layer or multi-layer structure, and FIG. 3 shows a double-layer structure. As an example, the material of the adhesive layer 2 is selected from a double-sided adhesive tape or an adhesive produced by a spin-coating process. The adhesive tape is preferably a UV adhesive tape, which can be easily torn off after being irradiated by UV light.

As shown in FIG. 4 , step S3 is performed: adhering a through silicon interposer 3 (TSI for short) on the adhesive layer 2 , the through silicon interposer 3 includes an insulating substrate 301 and a plurality of through silicon interposers up and down. The conductive pillars 302 of the insulating substrate.

Specifically, as shown in FIG. 5 , the punctured silicon interposer 3 can be obtained by cutting the punctured silicon interposer wafer 4 .

As an example, a conductive bump 303 is connected to the side of the conductive pillar 302 facing the adhesive layer 2, and when the perforated silicon interposer 3 is adhered on the adhesive layer 2, the conductive bump 303 is embedded In the adhesive layer 2.

As shown in FIG. 6 , step S4 is performed: at least one die 5 (Die) is provided, and the die 5 is mounted face down on the perforated silicon interposer 3 . Here, the front side of the bare chip 5 refers to the side of the bare chip 5 on which devices and electrode leads are formed.

Specifically, the types and quantities of the bare chips 5 can be varied. For example, the bare chip 5 includes but not limited to storage devices, display devices, input components, discrete components, power supplies, voltage regulators and other devices. The number of dies 5 may be one or more, up to the number of dies 5 that one perforated silicon interposer 3 can carry.

As an example, after adhering the perforated silicon interposer 3 on the adhesive layer 2 in the above step S3, it also includes forming a redistribution layer (Redistribution layer, RDL for short) on the perforated silicon interposer 3 (not shown). As shown in the figure), the die 5 is electrically connected to the through-silicon interposer 3 through the rewiring layer.

As an example, the following steps are alternately performed for making the rewiring layer: using a chemical vapor deposition process or a physical vapor deposition process to form a dielectric layer on the perforated silicon interposer 3, and etching the dielectric layer to form a pattern The dielectric layer; the metal layer is formed on the surface of the patterned dielectric layer by physical vapor deposition process, chemical vapor deposition process, evaporation process, sputtering process, electroplating process or electroless plating process, and the metal layer is etched to form A patterned metal wiring layer, the metal wiring layer passes through the patterned dielectric layer to be electrically connected to the through-hole silicon interlayer 3 . The material of the dielectric layer includes one or more combinations of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phospho-silicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes copper, aluminum , nickel, gold, silver, titanium or a combination of two or more.

Specifically, the rewiring layer includes at least one patterned dielectric layer and at least one patterned metal wiring layer. That is to say, the rewiring layer may include a plurality of dielectric layers and a plurality of metal wiring layers stacked in sequence. According to the wiring requirements, the connection between the metal wiring layers of each layer is realized by patterning each dielectric layer or making through holes. interconnection to meet the wiring requirements of different functions.

Specifically, the bare chip 5 may be a bare chip (Bumped Die) with conductive bumps 6 on the front, and the bare chip is electrically connected to the rewiring layer through the conductive bumps.

As an example, a bumped die (Bumpeddie) is bonded on the rewiring layer by a bond-on-trace (BOT) method. The material of the conductive bumps may include but not limited to copper (Cooper), nickel (Nickel), tin-silver (Tin-Silver).

In another embodiment, after the rewiring layer is formed on the through-hole silicon interposer 3, a step of forming a bump structure on the rewiring layer is further included, so that the die 5 passes through the bump The structure is electrically connected to the redistribution layer.

As an example, the method for preparing the bump structure includes the steps of: a) forming a copper pillar on the surface of the metal wiring layer exposed on the top of the rewiring layer by electroplating; b) forming a metal barrier on the surface of the copper pillar by electroplating layer (the metal barrier layer may not be made); c) forming solder metal on the surface of the metal barrier layer by electroplating, and forming solder bumps on the surface of the metal barrier layer by using a high temperature reflow process. Further, the metal barrier layer includes a nickel layer, and the material of the solder bump includes one of lead, tin and silver or an alloy containing any one of the above solder metals.

In other embodiments, the bump structure may only include solder bumps, for example, the bump structure is a solder ball, which is directly fabricated on the surface of the metal wiring layer exposed on the top of the rewiring layer.

As shown in FIG. 7 , step S5 is performed to form a plastic encapsulation layer 7 covering the die 5 and the perforated silicon interposer 3 on the adhesive layer 2 .

Specifically, the plastic encapsulation layer 7 is used to protect the die 5 and the perforated silicon interposer 3 so that the encapsulation structure is not easy to crack. As an example, the plastic sealing layer 7 is made of a thermosetting material, such as a commonly used plastic sealing material such as silicone, epoxy resin, or polyimide. The method of forming the plastic sealing layer 7 can be selected from but not limited to compression molding (compressive molding), printing (paste printing), transfer molding (transfer molding), liquid sealing molding (liquidencapsulant molding), vacuum lamination (vacuum lamination), spinning Any one of methods such as spin coating.

For example, transfer molding (transfer molding) is one of the forming methods of plastics. It is a method of heating the closed metal model and pressing molten resin from the thin tube gate to make it harden and form. It has higher forming precision than compression molding. , and can produce molded products of very complex shapes. In addition, resin can be filled in one place and several molded products can be obtained in the continuous metal mold at the same time. This molding method is mainly used for the molding of thermosetting resins such as phenolic resin, urea resin, melamine, epoxy resin and polyester, so it is also called injection molding of thermosetting resin.

As shown in FIG. 8 , step S6 is performed: removing the carrier substrate 1 and the adhesive layer 2 to obtain a three-dimensional chip module including the perforated silicon interposer 3 , the die 5 and the plastic encapsulation layer 7 .

Specifically, the method for separating the adhesion layer 2 from the perforated silicon interposer 3 and the plastic sealing layer 7 is selected from but not limited to chemical corrosion, mechanical peeling, mechanical grinding, thermal baking, ultraviolet light irradiation, laser ablation, chemical mechanical At least one of polishing and wet stripping. For example, if the adhesive layer 2 is made of UV adhesive tape, the UV adhesive tape can be irradiated with ultraviolet light to reduce the viscosity, and then the carrier substrate 1 and the adhesive layer 2 can be separated from the adhesive layer 2 by tearing off. The perforated silicon interposer 3 and the plastic encapsulation layer 7, compared with the thinning process, such as grinding, corrosion, etc., this separation method is simpler and easier to operate, which can greatly reduce the process cost.

As shown in FIG. 9 , step S7 is performed: providing a packaging substrate 8 , and mounting the side of the three-dimensional chip module having the TSIM layer 3 on the packaging substrate 8 .

Specifically, the packaging substrate 8 includes, but is not limited to, a PCB board, in which a conductive interconnection structure is provided, and solder balls 9 leading out of the conductive interconnection structure are provided on the back side.

Specifically, after the three-dimensional chip module is installed on the packaging substrate 8, there is a gap between the three-dimensional chip module and the packaging substrate 8; in the packaging method of the three-dimensional chip packaging structure of the present invention, the After the three-dimensional chip module is installed on the packaging substrate 8, a step of forming a protective layer 10 in the gap is also included (as shown in FIG. 10 ). The protective layer 10 can be made of a polymer material, which surrounds the conductive bump 303, on the one hand, it can increase the bonding strength between the conductive bump 303 and the packaging substrate 8, and prevent it from shaking or falling, and on the other hand On the one hand, it can be protected to prevent oxidation and water vapor from affecting the conductive bumps 303 and the packaging substrate 8 below.

So far, the packaging of the three-dimensional chip packaging structure is completed. The packaging method of the three-dimensional chip packaging structure of the present invention first adheres the TSI perforated silicon interposer on the carrier substrate, and then mounts the die face down on the perforated silicon interposer, and forms a chip on the adhesive layer. Covering the die and the plastic encapsulation layer of the perforated silicon interposer, and then removing the carrier substrate and the adhesive layer to obtain a three-dimensional chip module including the perforated silicon interposer, the die and the plastic encapsulation layer, Finally, an encapsulation substrate is provided, and the side of the three-dimensional chip module having the perforated silicon interposer is mounted on the encapsulation substrate. The encapsulation method of the three-dimensional chip encapsulation structure of the present invention has low process complexity, which is beneficial to reduce production cost and improve encapsulation yield.

Embodiment two

The present invention also provides a three-dimensional chip packaging structure, as shown in FIG. 10 , which is a schematic structural diagram of the three-dimensional chip packaging structure, including a packaging substrate 8 and a three-dimensional chip module electrically connected above the packaging substrate 8, wherein, The three-dimensional chip module includes:

The perforated silicon interposer 3 includes an insulating substrate 301 and a plurality of conductive pillars 302 penetrating the insulating substrate 301 up and down, and the conductive pillars 302 are electrically connected to the packaging substrate 8;

at least one die 5, the die 5 is mounted face down on the perforated silicon interposer 3;

The plastic encapsulation layer 7 covers the die 5 and the perforated silicon interposer 3 .

As an example, the packaging substrate 8 includes, but is not limited to, a PCB board, in which a conductive interconnection structure is provided, and solder balls 9 leading out of the conductive interconnection structure are provided on the back side.

As an example, there is a gap between the three-dimensional chip module and the packaging substrate 8 , and a protective layer 10 is formed in the gap. The protective layer 10 can be made of a polymer material, which surrounds the conductive bump 303, on the one hand, it can increase the bonding strength between the conductive bump 303 and the packaging substrate 8, and prevent it from shaking or falling, and on the other hand On the one hand, it can be protected to prevent the impact of oxidation and water vapor on the conductive bump 303 and the package substrate 8 below.

It should be pointed out that the front side of the bare chip 5 refers to the side of the bare chip 5 on which devices and electrodes are drawn out. As an example, a rewiring layer is formed between the die 5 and the through-hole silicon interposer 3 , so that the die is electrically connected to the through-hole silicon interposer 3 through the rewiring layer. The rewiring layer may include at least one patterned dielectric layer and at least one patterned metal wiring layer. For example, the rewiring layer may include multiple dielectric layers and multiple metal wiring layers stacked in sequence. According to the wiring requirements, the interconnection between the metal wiring layers is realized by patterning each dielectric layer or making through holes. Connect to meet the connection requirements of different functions.

As an example, the type and number of said dice 5 may vary. For example, the bare chip 5 includes but not limited to storage devices, display devices, input components, discrete components, power supplies, voltage regulators and other devices. The number of dies 5 may be one or more, up to the number of dies 5 that one perforated silicon interposer 3 can carry.

As an example, the bare chip 5 may be a bumped die with conductive bumps 6 on the front side, and the bare chip is electrically connected to the rewiring layer through the conductive bumps 6 .

As an example, a bump structure (not shown) is disposed on the rewiring layer, so that the die 5 is electrically connected to the rewiring layer through the bump structure. The bump structure includes a metal post and a solder bump connected to the metal post, or the bump structure only includes a solder bump.

As an example, the conductive pillars 302 are electrically connected to the package substrate through conductive bumps 303 .

The three-dimensional chip packaging structure of the present invention adopts a packaging form of packaging substrate, TSI perforated silicon interposer, and die stack, and uses a plastic sealing layer to realize the protection of the die, wherein the die and the TSI perforated silicon interposer can pass through the conductive bump and Rewire layer connections. The three-dimensional chip packaging structure of the present invention has the advantages of simple structure, higher I/O density and faster transmission efficiency.

To sum up, the packaging method of the three-dimensional chip packaging structure of the present invention first adheres the TSI perforated silicon interposer on the carrier substrate, and then mounts the die face down on the perforated silicon interposer, and on the said perforated silicon interposer. A plastic sealing layer covering the die and the perforated silicon interposer is formed on the adhesive layer, and then the carrier substrate and the adhesive layer are removed to obtain the perforated silicon interposer, the die and the plastic sealant layer The three-dimensional chip module finally provides a packaging substrate, and the side of the three-dimensional chip module having the perforated silicon interposer is installed on the packaging substrate. The encapsulation method of the three-dimensional chip encapsulation structure of the present invention has low process complexity, which is beneficial to reduce production cost and improve encapsulation yield. The three-dimensional chip packaging structure of the present invention adopts a packaging form of packaging substrate, TSI perforated silicon interposer, and die stack, and uses a plastic sealing layer to realize the protection of the die, wherein the die and the TSI perforated silicon interposer can pass through the conductive bump and Rewire layer connections. The three-dimensional chip packaging structure of the present invention has the advantages of simple structure, higher I/O density and faster transmission efficiency. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (16)

1. a kind of method for packing of three-dimensional chip encapsulating structure, it is characterised in that comprise the following steps：

One bearing substrate is provided；

In forming adhesion layer on the bearing substrate；

In adhesion perforation silicon intermediary layer on the adhesion layer, the perforation silicon intermediary layer includes insulated substrate and multiple run through up and down The conductive pole of the insulated substrate；

At least one nude film is provided, the nude film face down is installed on the perforation silicon intermediary layer；

In the plastic packaging layer that the covering nude film and the perforation silicon intermediary layer are formed on the adhesion layer；

The bearing substrate and adhesion layer are removed, obtains including the perforation silicon intermediary layer, the nude film and the plastic packaging layer Three-dimensional chip module；

One package substrate is provided, the one side that the three-dimensional chip module has the perforation silicon intermediary layer is installed in the encapsulation On substrate.

2. the method for packing of three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：The three-dimensional chip mould There is gap between block and the package substrate；After the three-dimensional chip module is installed on the package substrate, also wrap Include the step of protective layer is formed in the gap.

3. the method for packing of three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：In on the adhesion layer After adhering to the perforation silicon intermediary layer, also it is included in the step of forming re-wiring layer on the perforation silicon intermediary layer, so that The nude film is electrically connected with by the re-wiring layer and the perforation silicon intermediary layer.

4. the method for packing of three-dimensional chip encapsulating structure according to claim 3, it is characterised in that：The re-wiring layer Including at least one layer of patterned dielectric layer and at least one layer of patterned metal wiring layer.

5. the method for packing of three-dimensional chip encapsulating structure according to claim 3, it is characterised in that：The front of the nude film With conductive projection, the nude film is electrically connected with by the conductive projection and the re-wiring layer.

6. the method for packing of three-dimensional chip encapsulating structure according to claim 3, it is characterised in that：In the perforation silicon Formed on interlayer after re-wiring layer, be also included on the re-wiring layer the step of forming projection cube structure, so that described Nude film is electrically connected with by the projection cube structure and the re-wiring layer.

7. the method for packing of three-dimensional chip encapsulating structure according to claim 6, it is characterised in that：The projection cube structure bag Metal column and the solder bump being connected to above the conductive pole are included, or the projection cube structure only includes solder bump.

8. the method for packing of three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：The conductive pole towards The one side of the adhesion layer is connected with conductive salient point, when adhesion perforation silicon intermediary layer on the adhesion layer, the conductive salient point In the embedded adhesion layer.

9. the method for packing of three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：By cutting silicon of perforating Intermediary's wafer obtains the perforation silicon intermediary layer.

10. a kind of three-dimensional chip encapsulating structure, including package substrate and the three-dimensional core that is electrically connected above the package substrate Piece module, it is characterised in that the three-dimensional chip module includes：

Perforate silicon intermediary layer, including insulated substrate and it is multiple up and down run through the insulated substrate conductive pole, the conductive pole with The package substrate is electrically connected with；

At least one nude film, the nude film face down are installed on the perforation silicon intermediary layer；

Plastic packaging layer, cover the nude film and the perforation silicon intermediary layer.

11. three-dimensional chip encapsulating structure according to claim 10, it is characterised in that：The three-dimensional chip module with it is described There is gap between package substrate, matcoveredn is formed in the gap.

12. three-dimensional chip encapsulating structure according to claim 10, it is characterised in that：In the nude film and the perforation silicon Formed with re-wiring layer between interlayer, so that the nude film is electrical by the re-wiring layer and the perforation silicon intermediary layer Connection.

13. three-dimensional chip encapsulating structure according to claim 12, it is characterised in that：The re-wiring layer is included at least The dielectric layer of one layer pattern and at least one layer of patterned metal wiring layer.

14. three-dimensional chip encapsulating structure according to claim 12, it is characterised in that：The front of the nude film is with conduction Projection, the nude film are electrically connected with by the conductive projection and the re-wiring layer.

15. three-dimensional chip encapsulating structure according to claim 12, it is characterised in that：It is provided with the re-wiring layer Projection cube structure, so that the nude film is electrically connected with by the projection cube structure and the re-wiring layer；The projection cube structure bag Metal column and the solder bump being connected to above the metal column are included, or the projection cube structure only includes solder bump.

16. three-dimensional chip encapsulating structure according to claim 1, it is characterised in that：The conductive pole passes through conductive salient point It is electrically connected with the package substrate.