CN107608824A - A kind of non-volatile computing device and its method of work - Google Patents

Abstract

The present invention relates to a non-volatile computing device, including a processing unit and an off-chip storage unit, the processing unit includes a central processing unit and an on-chip storage unit, the off-chip storage unit includes a non-volatile storage device, the The on-chip storage unit includes a non-volatile storage device and a volatile storage device.

Description

A non-volatile computing device and its working method

technical field

The invention relates to the field of computer technology, in particular to a non-volatile computing device and a working method thereof.

Background technique

Generally speaking, according to the storability of information, memory can be divided into volatile memory and non-volatile memory, wherein the data in volatile memory will disappear after power off, such as static random access memory or dynamic random access memory Memory, etc., the data in the non-volatile memory will not disappear after being disconnected, such as flash memory or hard disk.

Generally, compared with non-volatile memory, volatile memory has fast read and write speed but is expensive. Therefore, in computing devices, non-volatile memory is generally used as off-chip memory, such as tape, disk or flash memory; The on-chip memory generally adopts volatile memory, such as cache or memory. Since the data in the volatile memory cannot be saved after power failure, when the computing device is powered off (abnormally), problems such as data loss or too long backup/recovery time may easily occur.

Therefore, there is a need for a computing device capable of preventing data loss after a power failure and having short backup/restore times.

Contents of the invention

The present invention provides a non-volatile computing device and its working method, including a processing unit and an off-chip storage unit, the processing unit includes an on-chip storage unit, and the off-chip storage unit includes a non-volatile storage device and a volatile A storage device, the on-chip storage unit includes a non-volatile storage device.

Preferably, the volatile storage device and the non-volatile storage device in the off-chip storage unit are integrated in a single core.

Preferably, the volatile storage device and the non-volatile storage device in the off-chip storage unit adopt a stack structure.

Preferably, the processor further includes a non-volatile flip-flop.

Preferably, the non-volatile flip-flops include master-slave flip-flops and backup modules.

Preferably, the backup module includes a ferroelectric capacitor.

Preferably, the computing device further includes a power supply unit for supplying power to the computing device after the computing device is powered off.

Preferably, the power supply unit includes an electric energy collection module capable of collecting electric energy from the outside.

According to another aspect of the present invention, there is also provided a working method using the above computing device, including:

the computing device is in normal mode for normal operation;

When an abnormal power failure occurs or a sleep signal is triggered, the computing device enters a backup mode;

After the backup is completed, the computing device enters into a dormant mode, and each unit stops working;

When the wake-up signal occurs, the computing device enters the recovery mode, and after all the data backed up in the previous time is restored, the computing device re-enters the normal mode;

Wherein, in the backup mode, the computing device stores the current data in the system into the non-volatile storage device in the off-chip memory; in the recovery mode, the computing device stores the current data in the off-chip memory The data in the non-volatile memory device in the system is restored to the system.

According to another aspect of the present invention, a working method using the above-mentioned non-volatile trigger is also provided, including:

When the non-volatile flip-flop in the normal working mode is abnormally powered off or triggers a sleep signal, the non-volatile flip-flop saves the data in the master-slave flip-flop to the backup module in; and

When a wake-up signal occurs, the non-volatile flip-flop restores the data stored in the backup module to the master-slave flip-flop.

Compared with the prior art, the present invention achieves the following beneficial technical effects: the non-volatile computing device provided by the present invention adopts a two-level storage structure of on-chip storage and off-chip storage, which simplifies the storage hierarchy; wherein, the on-chip storage Non-volatile memory devices with low energy consumption and high scalability are used, and non-volatile memory devices and volatile memory devices are used for off-chip storage, which improves the stability and reliability of the system; at the same time, the present invention uses non-volatile trigger The flip-flop replaces the traditional flip-flop and realizes the local storage of data at the register level, so that when the computing device is powered off, the data in the register will not be lost, effectively ensuring the security of data storage and reducing the time loss of data backup. Saves system wake-up time.

Description of drawings

FIG. 1 is a schematic structural diagram of a non-volatile computing device according to a preferred embodiment of the present invention.

FIG. 2 is a schematic structural diagram of a computing device according to another embodiment of the present invention.

FIG. 3 is a schematic structural diagram of a computing device according to another embodiment of the present invention.

FIG. 4 is a schematic structural diagram of a non-volatile flip-flop used by the computing device shown in FIG. 1 .

FIG. 5 is a schematic diagram of a working mode switching process of the computing device shown in FIG. 1 .

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, further detailed descriptions provided in the embodiments according to the present invention will be provided below in conjunction with the accompanying drawings.

In recent years, with the development of storage technology, many new types of non-volatile memory have appeared, and their performance has been greatly improved, whether in terms of non-volatility or energy consumption, or access speed or scalability. Great progress, the read and write speed of some non-volatile memories can reach the nanosecond level, even comparable to the read and write speed of DRAM memory, and it is more power-saving and storage dense than traditional DRAM memory, and has Anti-radiation interference and other advantages.

The inventor has made full use of the characteristics of the non-volatile memory that can store data for a long time in the case of power failure, and adopted the non-volatile memory as the on-chip storage and off-chip storage in the computing device, and also adopted a non-volatile memory. Functional triggers replace traditional triggers in order to solve problems such as data loss in computing devices and long data recovery times.

Fig. 1 is a schematic structural view of a non-volatile computing device according to a preferred embodiment of the present invention. As shown in Fig. 1, the non-volatile computing device of the present invention includes a processor, off-chip memory and other conventional devices, for example, input/ Output (I/O) unit (not shown in Figure 1). Among them, the processor includes a control unit, a logical operation unit and an on-chip memory, and the on-chip memory (equivalent to the cache of a traditional computing device) adopts a non-volatile storage device; Combined) uses both volatile and non-volatile devices.

Fig. 2 is a schematic structural diagram of an off-chip memory and other devices of a computing device according to an embodiment of the present invention. As shown in Fig. 2, the off-chip memory includes a non-volatile memory and a volatile memory packaged in a single core sexual memory. When working normally, the processor communicates with the volatile memory in the off-chip memory via the bus, and when the power is off, the processor backs up the data in the volatile memory to the non-volatile memory through the bus control, so that Data recovery after power-on.

Fig. 3 is a schematic structural diagram of an off-chip memory and other devices of another embodiment of the computing device provided by the present invention. As shown in Fig. 3, the off-chip memory includes a volatile memory and a volatile memory integrated together in a 3D stacking manner. For non-volatile memory, for example, the bits of two storage devices can be set in a one-to-one correspondence, so that when the computing device performs data backup, the data in the corresponding position can be transmitted at the same time, thereby realizing parallel backup.

In one embodiment of the present invention, the above computing device may also include I/O equipment. The I/O device is connected to the computing device through an input and output interface, and is an important part for information exchange between the outside world and the computing device. The processor utilizes a bus to communicate with the computing device. I/O devices such as monitors, mice, and keyboards are controlled.

As shown in Figure 2 and Figure 3, in one embodiment of the present invention, the above-mentioned computing device may also include a power supply device, which can supply power to the system for a period of time after the system is powered off, so that the processor can perform data backup . The power supply device can adopt, for example, a battery, an external power supply or other power collection modules (such as solar panels, etc.) that can collect electric energy from the outside.

In another embodiment of the present invention, the non-volatile memory device used in the above-mentioned computing device, for example, the non-volatile memory device used in the on-chip memory and the non-volatile memory in the off-chip memory, can be phase change Phase change memory (PCM), Magnetic Random Access Memory (MRAM), Spin Torque Transfer Random Access Memory (STT-RAM), Ferroelectric RAM (FeRAM) Or resistive random access memory (RRAM), etc.

Fig. 5 is a schematic diagram of the working mode switching process of the computing device shown in Fig. 1. As shown in Fig. 5, according to an embodiment of the present invention, a working method of a non-volatile computing device is provided, and the method of the computing device specifically includes The following four modes:

Normal mode: In normal mode, the power supply of the computing device is normally supplied, and the system is in a normal working mode. Wherein, the power supply mode of the power supply can adopt, for example, battery power supply, mains power supply, or use of an electric energy collection module to collect electric energy from the outside;

Backup mode: In backup mode, the computing device is switched from being powered by the power supply to being powered by the power supply unit, and the system is in the data backup mode, which stores various data executed when the power is supplied to the non-volatile storage device, for example, in the non-volatile In the flip-flop, save the data in the master-slave flip-flop to its backup module; in the off-chip memory, save the data running in the volatile memory device to the non-volatile memory device;

Sleep mode: In sleep mode, all units of the computing device stop working;

Recovery mode: In recovery mode, when the computing device is switched from power failure or power supply unit to power supply, the system first restores data from the backup mode closest to the recovery mode, that is, stores the data in the backup mode to the non-volatile Various data in the storage device are restored, for example, in the non-volatile flip-flop, the data saved in the backup module is restored to the master-slave flip-flop; in the off-chip memory, the data saved in the non-volatile memory device The data in the memory is restored to the volatile memory device.

The computing device provided by the present invention is usually in the normal mode of normal operation. When an abnormal power failure occurs or a dormancy signal is triggered, the computing device enters a backup mode; after the backup is completed, the computing device shuts down or enters a dormant mode, stops power supply, and does not perform any work ; When the computing device is turned on again or a wake-up signal occurs, the computing device enters the recovery mode, and after all the data backed up in the previous time is restored, the computing device enters the normal mode again.

Fig. 4 is a schematic structural diagram of a non-volatile flip-flop of the computing device shown in Fig. 1, as shown in Fig. 4, the flip-flop in the above-mentioned processor adopts a non-volatile flip-flop, for example, the flip-flop can be A flip-flop (ferroelectric flip-flop) based on a ferroelectric memory includes a flip-flop with a traditional master-slave structure and a backup module with a ferroelectric capacitor. Wherein, when the computing device is working normally, the trigger of the traditional master-slave structure is adopted, and when the computing device needs to be backed up, the operation data in the trigger of the master-slave structure can be backed up to the backup module.

The present invention also provides a data backup method of a non-volatile trigger. Taking a ferroelectric trigger as an example, when the computing device is in the above normal mode, the RW signal is at a low level, and the working mode of the ferroelectric trigger is Consistent with traditional flip-flops; when the computing device is in backup mode, the RW signal is at high level and the pch signal is at low level, the ferroelectric flip-flop can be configured, at this time the Clk signal is at high level, and the PL signal generates a A high-level pulse can store the data in the master-slave flip-flops in the ferroelectric capacitors C1 and C2; when the computing device is in recovery mode, it is necessary to perform a read operation on the backup module, that is, the Din signal and the Clk signal remain low , the Pch signal generates a high-level pulse to discharge the capacitor, and the PL signal generates a high-level pulse to drive the pair of ferroelectric capacitors, thereby restoring the data to the master-slave flip-flop.

Among them, the Din signal is the input signal of the flip-flop, Pch is the charging control signal, PL is the pulse control signal, and RW is the mode selection signal.

Although in the foregoing embodiments, a flip-flop based on a ferroelectric memory is used as an example to describe the non-volatile flip-flop provided by the present invention and the computing device using the flip-flop, those skilled in the art should understand that, The non-volatile flip-flops here are not limited to flip-flops based on ferroelectric random access memory (Ferroelectric RAM, FeRAM), and can also be, for example, based on spin torque conversion random access memory (Spin Torque Transfer Random Access Memory, STT-RAM) ) flip-flops or flip-flops based on resistive random access memory (RRAM) and other types.

Compared with the prior art, the non-volatile computing device provided in the embodiment of the present invention adopts a two-level non-volatile storage structure, which can effectively guarantee the safety of operating data, reduce the time loss of data backup, and save The wake-up time of the system, this storage structure can create a new design concept for the data storage mechanism of the computing device.

Although the present invention has been described in terms of preferred embodiments, the present invention is not limited to the embodiments described herein, and various changes and changes are included without departing from the scope of the present invention.

Claims (10)

1. A non-volatile computing device, comprising a processing unit and an off-chip storage unit, the processing unit comprising an on-chip storage unit, the off-chip storage unit comprising a non-volatile storage device and a volatile storage device, the The on-chip memory unit includes a non-volatile memory device. 2. The nonvolatile computing device according to claim 1, wherein the volatile storage device and the nonvolatile storage device in the off-chip storage unit are integrated in a single core. 3. The non-volatile computing device according to claim 2, wherein the volatile storage device and the non-volatile storage device in the off-chip storage unit adopt a stack structure. 4. The non-volatile computing device according to claim 1, wherein the processor further comprises a non-volatile flip-flop. 5 . The non-volatile computing device according to claim 4 , wherein the non-volatile flip-flops include a master-slave flip-flop and a backup module. 6. The non-volatile computing device according to claim 5, wherein the backup module comprises a ferroelectric capacitor. 7. The non-volatile computing device according to claim 1, wherein the computing device further comprises a power supply unit for supplying power to the computing device after the computing device is powered off. 8 . The non-volatile computing device according to claim 7 , wherein the power supply unit comprises an electric energy collection module capable of collecting electric energy from the outside. 9. A working method of the computing device according to any one of claims 1 to 8, comprising: the computing device is in normal mode for normal operation; When an abnormal power failure occurs or a sleep signal is triggered, the computing device enters a backup mode; After the backup is completed, the computing device enters into a dormant mode, and each unit stops working; When the wake-up signal occurs, the computing device enters the recovery mode, and after all the data backed up in the previous time is restored, the computing device re-enters the normal mode; Wherein, in the backup mode, the computing device stores the current data in the system into the non-volatile storage device in the off-chip memory; in the recovery mode, the computing device stores the current data in the off-chip memory The data in the non-volatile memory device in the system is restored to the system. 10. A working method of the nonvolatile flip-flop according to any one of claims 4 or 6, comprising: When the non-volatile flip-flop in the normal working mode is abnormally powered off or triggers a sleep signal, the non-volatile flip-flop saves the data in the master-slave flip-flop to the backup module in; and When a wake-up signal occurs, the non-volatile flip-flop restores the data stored in the backup module to the master-slave flip-flop.