CN107579108A - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN107579108A CN107579108A CN201610516729.3A CN201610516729A CN107579108A CN 107579108 A CN107579108 A CN 107579108A CN 201610516729 A CN201610516729 A CN 201610516729A CN 107579108 A CN107579108 A CN 107579108A
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- 238000000034 method Methods 0.000 title claims abstract description 89
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 239000010410 layer Substances 0.000 claims abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 120
- 239000011241 protective layer Substances 0.000 claims abstract description 111
- 238000002955 isolation Methods 0.000 claims abstract description 63
- 150000002500 ions Chemical class 0.000 claims abstract description 38
- 238000000137 annealing Methods 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 36
- 239000002019 doping agent Substances 0.000 claims description 25
- 238000002347 injection Methods 0.000 claims description 16
- 239000007924 injection Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- -1 phosphonium ion Chemical class 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910052785 arsenic Inorganic materials 0.000 claims description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 238000005530 etching Methods 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000000926 separation method Methods 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 239000007787 solid Substances 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- BIXHRBFZLLFBFL-UHFFFAOYSA-N germanium nitride Chemical compound N#[Ge]N([Ge]#N)[Ge]#N BIXHRBFZLLFBFL-UHFFFAOYSA-N 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of forming method of semiconductor structure, including：Substrate is formed, the substrate includes：First area and second area；Isolation structure is formed in the substrate；Protective layer is formed on the second area isolation structure；Doped layer is formed in the first area substrate surface, there are Doped ions in the doped layer；The doped layer is made annealing treatment, the Doped ions in the doped layer is diffused into first area substrate；After forming the protective layer and being made annealing treatment, the doped layer is removed.Wherein, the protective layer can protect second area isolation structure not to be thinned, so as to ensure that second area isolation structure has enough thickness during the doped layer is removed; and then the leakage current of semiconductor structure is reduced, improve semiconductor body structural behaviour.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of semiconductor structure.
Background technology
With the continuous progress of semiconductor technology, semiconductor devices develops towards the direction of high integration, high quality, partly led
The characteristic size of body device accordingly reduces.
The reduction of the reduction of feature sizes of semiconductor devices, particularly grid structure width, make grid structure lower channels
Length constantly reduce.The reduction of channel length adds the possibility of electric charge break-through between source and drain doping area in transistor, and
Easily cause channel leakage stream.In order to reduce channel leakage stream, in the forming process of semiconductor structure, often to grid structure two
The substrate of side is doped, and substrate surface is turned into amorphous state, lightly doped district is formed, so as to reduce channel leakage stream.
In semiconductor technology, generally require and be infused in fin by being lightly doped and form the lightly doped district, however, ion is noted
Enter the performance for easily making fin top amorphization influence semiconductor devices.Ion implanting is to fin during in order to reduce to form lightly doped district
The influence in portion, the forming method of semiconductor structure introduce solid source doping process.Solid source doping process is by partly leading
Doped layer is formed on body substrate, there are Doped ions in the doped layer；Mixing in the doped layer is made by annealing process again
Heteroion diffuses into the substrate and forms lightly doped district；Formed after lightly doped district, remove the doped layer.
However, the forming method of the semiconductor structure, easily reduces the separation layer thickness in semiconductor structure, influences half
Conductor structure performance.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of forming method of semiconductor structure, semiconductor structure can be improved
Energy.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is formed, it is described
Substrate includes：First area and second area；Isolation structure is formed in the first area and second area substrate；Described
Protective layer is formed on second area isolation structure；Doped layer is formed in the first area substrate surface, is had in the doped layer
There are Doped ions；The doped layer is made annealing treatment, the Doped ions in the doped layer is diffused into first area
Substrate；After forming the protective layer and being made annealing treatment, the doped layer is removed.
Optionally, formed on the second area isolation structure after protective layer, in the first area substrate surface
Form doped layer.
Optionally, formed on the second area isolation structure before protective layer, in the first area substrate surface
Form doped layer.
Optionally, the substrate includes：Substrate and the fin on substrate.
Optionally, the step of forming substrate includes：Initial substrate is provided；The graphical initial substrate, formed substrate and
Fin on substrate；The isolation structure covers the fin partial sidewall on the substrate between the fin
Surface.
Optionally, include in the step of formation protective layer on the second area isolation structure：In the substrate and isolation
Initial protective layers are formed in structure；Remove the initial protective layers in the substrate of first area.
Optionally, formed before the protective layer, in addition to：The shape in the first area substrate or second area substrate
Into grid structure；In the step of removing the initial protective layers in the substrate of first area, retain the first area grid structure side
The initial protective layers of wall, form the first side wall.
Optionally, the material of the protective layer is silicon nitride or silicon oxynitride.
Optionally, the thickness of the protective layer is 10 angstroms~40 angstroms.
Optionally, forming the technique of the initial protective layers includes：Chemical vapor deposition method or atomic layer deposition
Technique.
Optionally, removing the technique of the initial protective layers in the substrate of first area includes：Anisotropic dry etch.
Optionally, after removing the doped layer, in addition to the protective layer is removed.
Optionally, the material of the protective layer is photoresist, removes the technique of the protective layer and includes cineration technics.
Optionally, the material of the protective layer is organic antireflective coating, removes the method for the protective layer and includes：Pass through
Bath in photoetching process removes the protective layer.
Optionally, the material of the doped layer is silica or silicon oxynitride；In the doped layer doped with phosphonium ion or
Arsenic ion.
Optionally, include the step of the first area substrate surface forms doped layer：In the first area substrate
Initial dopant layer is formed on surface and the second area substrate；Remove the initial dopant layer in the second area substrate.
Optionally, removing the technique of the initial dopant layer in the second area substrate includes：Dry etching or wet method are carved
Erosion.
Optionally, the first area is used to form NMOS；The second area is used to form PMOS；The Doped ions
For phosphorus or arsenic.
Optionally, after removing the doped layer, in addition to：The second area substrate is carried out injection is lightly doped, noted
Entering ion includes boron ion or BF2 ions.
Optionally, the second area substrate is carried out after injection is lightly doped, in addition to：Remove the protective layer.
Compared with prior art, technical scheme has advantages below：
In the forming method of the semiconductor structure of the present invention, before the doped layer is removed, the second area every
From forming protective layer in structure.The protective layer can protect second area isolation junction during the doped layer is removed
Structure is not thinned, and so as to ensure that second area isolation structure has enough thickness, and then reduces the leakage of semiconductor structure
Electric current, improve semiconductor body structural behaviour.
Brief description of the drawings
Fig. 1 to Fig. 2 is a kind of structural representation of each step of the forming method of semiconductor structure；
Fig. 3 to Figure 16 is the structural representation of each step of the embodiment of forming method one of semiconductor structure of the present invention.
Embodiment
Problems be present in the forming method of semiconductor structure, such as：The forming method of the semiconductor structure easily subtracts
Small semiconductor structure interval influences semiconductor structure performance from structural thickness.
In conjunction with a kind of forming method of semiconductor structure, the forming method for analyzing the semiconductor structure easily reduces half
In conductor structure the reason for separation layer thickness：
Fig. 1 and Fig. 2 is a kind of structural representation of each step of the forming method of semiconductor structure.
It refer to Fig. 1, there is provided substrate, the substrate, which includes first area A and second area B, the substrate, to be included：Substrate
100；Fin 111 on the substrate 100.
With continued reference to Fig. 1, isolation structure 101 is formed on the substrate between the fin 111.
With continued reference to Fig. 1, doped layer 112 is formed on the surface of first area I fins 111, is had in the doped layer 112
There are Doped ions.
With continued reference to Fig. 1, the doped layer 112 is made annealing treatment, the Doped ions is diffused into the firstth area
Domain I fins 111 form lightly doped district.
It refer to Fig. 2, after the annealing, remove the doped layer 112 (as shown in Figure 1).
Wherein, during etching removes the doped layer 112, the second area B isolation structures 101 also easy quilt
Etching, so that second area B isolation structures 101 are thinned, and then easily influence the isolation of second area B isolation structures 101
Energy.Therefore, the forming method of the semiconductor structure easily influences the performance of semiconductor structure.
To solve the technical problem, the invention provides a kind of forming method of semiconductor structure, including：Form base
Bottom, the substrate include：First area and second area；Isolation structure is formed in the substrate；The second area every
From forming protective layer in structure；Doped layer is formed in the first area substrate surface, there are Doped ions in the doped layer；
The doped layer is made annealing treatment, the Doped ions in the doped layer is diffused into first area substrate；Form institute
After stating protective layer and being made annealing treatment, the doped layer is removed.
Wherein, before the doped layer is removed, protective layer is formed on the second area isolation structure.The protection
Layer can protect second area isolation structure not to be thinned, so as to ensure second during the doped layer is removed
Zone isolation structure has enough thickness, and then reduces the leakage current of semiconductor structure, improves semiconductor body structural behaviour.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 16 is the structural representation of each step of the embodiment of forming method one of semiconductor structure of the present invention.
It should be noted that in CMOS forming process, when due to pair nmos transistor carrying out that injection is lightly doped, doping
Ion is arsenic.The atomic weight of arsenic is larger, easily produces damage to substrate.Therefore, for nmos pass transistor, solid source is typically passed through
The substrate of doping process pair nmos transistor is doped.The mistake of the doped layer formed in the solid source doping process is removed
Cheng Zhong, isolation structure are easily etched, and reduce thickness, easily influence the electrical property of semiconductor structure.Therefore, the present embodiment
In, exemplified by being doped by the substrate of solid source doping process pair nmos transistor, to semiconductor structure of the present invention
Forming method is described in detail.In other embodiments, the substrate of solid source doping process pair pmos transistor can also be passed through
It is doped.
Fig. 3 is refer to, forms substrate, the substrate includes：First area I and second area II.
In the present embodiment, the substrate is used to form fin formula field effect transistor.In other embodiments, the substrate is also
It can be used for forming planar transistor.
In the present embodiment, the first area I is used to form nmos pass transistor；The second area II is used to form PMOS
Transistor.
In the present embodiment, the step of forming the substrate, includes：Initial substrate is provided；The graphical initial substrate, shape
Fin 211 into substrate 200 and on substrate 200.
In the present embodiment, the material of the initial substrate is silicon.In other embodiments, the initial substrate can also be
The Semiconductor substrates such as germanium substrate, silicon-Germanium substrate, silicon-on-insulator or germanium on insulator.
In the present embodiment, the fin 211 is located at the surface of substrate 200.In other embodiments, the fin and institute
Oxide layer can also be had by stating between substrate.
Fig. 4 is refer to, isolation structure 201 is formed in the substrate.
The isolation structure 201 is used to realize the electric insulation between different semiconductor devices.
In the present embodiment, the substrate includes：Substrate 200；Fin 211 on the substrate 200.The isolation junction
Structure 201 is on the substrate 200 between the fin 211.
In the present embodiment, the material of the isolation structure 201 is silica.In other embodiments, the isolation structure
Material can also be silicon oxynitride.
As shown in Figure 5 and Figure 6, in the present embodiment, formed after the isolation structure 201, the forming method also includes：
Separation layer (not shown) is formed on the surface of fin 211；As shown in figure 5, formed after separation layer, to firstth area
Domain I fins 211 carry out the first ion implanting；As shown in fig. 6, the second ion implanting is carried out to the second area II fins 211.
The separation layer is used in first ion implantation process, and protection first area I fins 211 are injury-free,
And in second ion implantation process, protection second area II fins 211 are injury-free.
First ion implanting is used for the threshold voltage for adjusting nmos pass transistor；Second ion implanting is used to adjust
The threshold voltage of PMOS transistor.
In the present embodiment, the material of the separation layer is silica.In other embodiments, the material of the separation layer is also
Can be silicon nitride or silicon oxynitride.
In the present embodiment, the injection ion of first ion implanting is boron ion；The injection ion of second ion implanting
For phosphonium ion.
It should also be noted that, as shown in Figure 7 and Figure 8, Fig. 8 is side sectional views of the Fig. 7 along 1-1 ' lines.The formation side
Method also includes：The grid structure 230 of the fin 211 is developed across, the grid structure 230 covers the part of fin 211
Side wall and top surface.
In the present embodiment, the grid structure 230 includes：Across the gate dielectric layer (not shown) of the fin 211,
The gate dielectric layer covers the partial sidewall of fin 211 and top surface；Grid positioned at the gate dielectric layer surface；It is located at
The mask layer of gate surface.
In the present embodiment, the material of the gate dielectric layer is silica.In other embodiments, the material of the gate dielectric layer
Material can also be silicon nitride or silicon oxynitride.
In the present embodiment, the material of the grid is polysilicon, and in other embodiments, the grid can also be metal
Grid.
Fig. 9, Figure 10 and Figure 11 are refer to, Figure 11 is side sectional views of the Figure 10 along 2-2 ' lines, in the second area II
Protective layer 222 is formed on isolation structure 201.
In the present embodiment, the step of forming protective layer 222, includes：Formed in the substrate and isolation structure 201
Initial protective layers 202；The initial protective layers 202 in the I substrates of first area are removed, form the protective layer 222.
The step of below in conjunction with accompanying drawing to forming protective layer 222, elaborates.
Fig. 9 is refer to, initial protective layers 202 are formed in the substrate and isolation structure 201.
In the present embodiment, the surface of substrate 200 has grid structure 230.Described in the initial protective layers 202 also cover
The top of grid structure 230 and sidewall surfaces.
In the present embodiment, the material of the material and the isolation structure of the initial protective layers 202 differs.Initial protection
The material of layer 202 and isolation structure 201 differs, and initial protective layers 202 are different from the etch rate of isolation structure 201, so as to
During first area I initial protective layers 202 are removed, the loss to the isolation structure 201 is small.In other embodiment
In, the material of the initial protective layers can also be identical with the material of the isolation structure.
In the present embodiment, the material of the initial protective layers 202 is silicon nitride.In other embodiments, the protective layer
Material can also be silicon oxynitride, germanium oxide, germanium oxynitride or germanium nitride.In addition, the material of the initial protective layers may be used also
Think ARC or photoresist.
If it should be noted that the thickness of the initial protective layers 202 is too small, it is difficult to subsequently remove the mistake of doped layer
The second area II isolation structures 201 are protected in journey；If the thickness of the initial protective layers 202 is excessive, easily after increase
The difficulty of the continuous etching initial protective layers 202.Specifically, in the present embodiment, the thickness of the initial protective layers 202 is 10 angstroms
~40 angstroms, such as 20 angstroms.
In the present embodiment, formed by chemical vapor deposition, ald or physical gas-phase deposition described initial
Protective layer 202.
Figure 10 and Figure 11 are refer to, removes the initial protective layers 202 (as shown in Figure 9) in the I substrates of first area, forms institute
State protective layer 222.
The protective layer 222 is used to protect second area II isolation structures 201 not during doped layer is subsequently removed
It is etched, so as to improve the isolation performance of second area II isolation structures 201, and then improves semiconductor structure performance.
In the present embodiment, the material of the protective layer 222 and the isolation structure 201 differs, therefore, in etching first
During initial protective layers 202 in the I substrates of region, the etch rate of the protective layer 222 and the isolation structure 201 is not
Together.Therefore, the damage to the isolation structure 201 during etching is small.In other embodiments, the protective layer and institute
The material for stating isolation structure can also be identical.
In the present embodiment, the initial protective layers 202 in the I substrates of first area are removed by anisotropic dry etch.Respectively
Anisotropy is dry-etched in horizontal etch rate less than etch rate in the vertical, and has good profile control.
In etching process, the initial protective layers 202 of the sidewall surfaces of first area I grid structures 230 can be retained, form side wall 212.
It should be noted that in the present embodiment, for simplification of flowsheet, etched by anisotropic dry etch described in
Initial protective layers 202, form the side wall 212.In other embodiments, side can also be formed before initial protective layers are formed
Wall.Then removing the technique of the initial protective layers in the substrate of first area can also include：Wet etching or isotropism dry method are carved
Erosion.
In the present embodiment, the material of the initial protective layers 202 is silicon nitride.Accordingly, the material of the protective layer is
Silicon nitride.In other embodiments, the material of the protective layer can also be silica, silicon oxynitride, germanium oxide, germanium oxynitride
Or germanium nitride.
In the present embodiment, the thickness of the protective layer 222 is identical with the thickness of the initial protective layers 202.Specifically, this
In embodiment, the thickness of the protective layer 222 is 10 angstroms~40 angstroms, such as 20 angstroms.
Figure 12 and Figure 13 are refer to, in first area I substrate surfaces formation doped layer 213, the doped layer 213
With Doped ions.
In the present embodiment, the step of forming doped layer 213, includes：In first area I substrate surfaces and described
The surface of protective layer 222 forms initial dopant layer 203；Remove the initial dopant layer 203 on the surface of protective layer 222.
In the present embodiment, after protective layer 222 is formed, doped layer 213 is formed.The protective layer 222 can remove
During the initial dopant layer 203, protection second area II isolation structures 201.In other embodiments, can also be in shape
Into before protective layer, doped layer is formed.
The step of below in conjunction with accompanying drawing to forming doped layer 213, elaborates.
Figure 12 is refer to, initial dopant layer is formed in the first area I substrate surfaces and the surface of the protective layer 222
203。
In the present embodiment, the substrate includes the fin 211 on substrate 200.Form the initial dopant layer 203
Step includes：Initial dopant layer 203 is formed on the surface of first area I fins 211.
In the present embodiment, the initial dopant layer 203 also covers the first area I isolation structures 201.
In the present embodiment, the material of the initial dopant layer 203 is silica.In other embodiments, the doping of beginning
The material of layer can also include silicon nitride or silicon oxynitride.
If it should be noted that the thickness of the initial dopant layer 203 is too small, it is difficult to 211 liang of the grid structure
The fin 211 of side carries out decrystallized；If the thickness of the initial dopant layer 203 is excessive, easily to follow-up etching process band
Come difficult.Specifically, in the present embodiment, the thickness of the initial dopant layer 203 is 10 angstroms~30 angstroms, such as 20 angstroms.
In the present embodiment, the first area I is used to form nmos pass transistor, and therefore, the Doped ions are phosphorus or arsenic.
In other embodiments, the first area can be also used for being formed PMOS transistor, the Doped ions can also be B or
BH2。
In the present embodiment, the initial dopant layer 203 is formed by atom layer deposition process, and carried out in deposition process
Doping.In other embodiments, can also be formed by chemical meteorology deposition technique or physical vapor deposition technique described initial
Doped layer.
In the present embodiment, the technological parameter of the initial dopant layer 203 is formed by atom layer deposition process to be included：Reaction
Thing includes：Organic precursor and PH3 gases containing Si；Gas flow is 10sccm5000sccm；
In the present embodiment, the concentration of Doped ions is 1.0E20atoms/cm in the initial dopant layer 2033~
1.0E22atoms/cm3。
Figure 13 is refer to, removes the initial dopant layer 203 (as shown in figure 12) on the surface of protective layer 222, forms doping
Layer 213.
During the initial dopant layer 203 for removing the surface of protective layer 222, the protective layer 222 can protect institute
Second area II isolation structures 201 are stated to be not etched, so as to reduce etching process to second area II isolation structures 201 every
From the influence of performance.
In the present embodiment, the protection is removed by the common application of dry etching, wet etching or dry method, wet etching
The initial dopant layer 203 on 222 surface of layer.
In the present embodiment, the doped layer 213 is formed by initial dopant layer 203, therefore, the doped layer 213 with it is described
The material of initial dopant layer 203 is identical with thickness.Specifically, the material of the doped layer 213 is silica, Doped ions are phosphorus
Or arsenic.The thickness of the doped layer 213 is 10 angstroms~30 angstroms, such as 20 angstroms.
With continued reference to Figure 13, the doped layer 213 is made annealing treatment, makes the Doped ions in the doped layer 213
Diffuse into the I substrates of first area, form lightly doped district.
The lightly doped district is used for the channel leakage stream for reducing transistor, reduces short-channel effect.
During being made annealing treatment to the doped layer 213, if the annealing temperature is too low, it is difficult to make described mix
Doped ions in diamicton 213 diffuse into first area I substrates, so as to be hardly formed lightly doped district；If state annealing temperature
It is too high, easily make the diffusion rate of Doped ions too fast, it is difficult to control the lightly doped district thickness of formation.Specifically, the present embodiment
In, the annealing temperature is 950 DEG C~1050 DEG C.
If annealing time is too short, it is difficult to make the Doped ions in the doped layer 213 diffuse into first area I bases
Bottom, so as to be difficult to reduce short-channel effect；If annealing time is long, easily makes the lightly doped district thickness to be formed excessive and influence
The electrical property of transistor.
Figure 14 is refer to, after forming the protective layer 222 and being made annealing treatment, removes the doped layer 213 (as schemed
Shown in 13).
During removing the doped layer 213, the protective layer 222 can protect the second area II isolation structures
201 are not etched, so as to reduce influence of the etching process to the isolation performance of second area II isolation structures 201.
In the present embodiment, removing the technique of the doped layer 213 can include：It is wet etching, dry etching or dry method, wet
The common application of method etching.
In other embodiments, if the material of the protective layer is photoresist.Removing the technique of the protective layer includes
Cineration technics；, can be by cineration technics or photoetching process if the material of the protective layer is organic antireflective coating
Bath removes the protective layer.
It refer to Figure 15, in the present embodiment, after removing the doped layer 213 (as shown in figure 13), the forming method
Also include：The second area II substrates are carried out that injection is lightly doped, second is formed in the second area II substrates and is gently mixed
Miscellaneous area.
Specifically, in the present embodiment, the second area II fins 211 are carried out that injection is lightly doped, in secondth area
The second lightly doped district is formed in domain II fins 211.The second area II is used to form PMOS transistor, to the second area
II fins 211 are carried out during injection is lightly doped, and injection ion is boron, and the mass fraction of boron is smaller, is injected being lightly doped
Cheng Zhong, the damage to second area II fins 211 are smaller.In other embodiments, institute can also be formed by solid source doping
State the second lightly doped district.
The step of carrying out ion implanting to the second area II fins 211 includes：Formed and cover the first area I fins
The photoresist 230 on the surface of portion 211；Ion implanting is carried out, forms the second lightly doped district；Remove the photoresist 230.
It refer to Figure 16, in the present embodiment, the second area II fins 211 carried out after injection is lightly doped, it is described
Forming method also includes：Remove the protective layer 222 (as shown in figure 15).
In the present embodiment, it can be applied by dry etching, wet etching or dry method, the common of wet etching described in removal
Protective layer 222.
In the present embodiment, the second area II fins 211 are carried out after injection is lightly doped, remove the protective layer
222, the protective layer 222 can be protected the second area II fins 211, reduce to described in injection process is lightly doped
The damage of second area II fins 211.In other embodiments, also to the second area fin can carry out that injection is lightly doped
Before, the protective layer is removed.
It should be noted that the forming method of the semiconductor structure of the present invention also provides another embodiment.
The present embodiment and the something in common of a upper embodiment will not be described here, and difference is included in the second area
Formed on isolation structure before protective layer, doped layer is formed in the first area substrate surface.Form the protective layer and institute
The step of stating doped layer is identical with a upper embodiment, will not be described here.To sum up, the forming method of semiconductor structure of the invention
In, before the doped layer is removed, protective layer is formed on the second area isolation structure.The protective layer can gone
During except the doped layer, second area isolation structure is protected not to be thinned, so as to ensure second area isolation junction
Structure has enough thickness, and then reduces the leakage current of semiconductor structure, improves semiconductor body structural behaviour.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (20)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Substrate is formed, the substrate includes：First area and second area；Isolation structure is formed in the first area and second area substrate；Protective layer is formed on the second area isolation structure；Doped layer is formed in the first area substrate surface, there are Doped ions in the doped layer；The doped layer is made annealing treatment, the Doped ions in the doped layer is diffused into first area substrate；After forming the protective layer and being made annealing treatment, the doped layer is removed.
- 2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that in the second area isolation structure After upper formation protective layer, doped layer is formed in the first area substrate surface.
- 3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that in the second area isolation structure Before upper formation protective layer, doped layer is formed in the first area substrate surface.
- 4. the forming method of the semiconductor structure as described in claims 1 to 3 any one claim, it is characterised in that institute Stating substrate includes：Substrate and the fin on substrate.
- 5. the forming method of semiconductor structure as claimed in claim 4, it is characterised in that the step of forming substrate includes：Carry For initial substrate；The graphical initial substrate, forms substrate and the fin on substrate；The isolation structure covers the fin partial sidewall surface on the substrate between the fin.
- 6. the forming method of the semiconductor structure as described in claims 1 to 3 any one claim, it is characterised in that The step of protective layer is formed on the second area isolation structure includes：Initial protection is formed in the substrate and isolation structure Layer；Remove the initial protective layers in the substrate of first area.
- 7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that formed before the protective layer, also Including：Grid structure is formed in the first area substrate and second area substrate；In the step of removing the initial protective layers in the substrate of first area, retain the initial of the first area gate structure sidewall Protective layer, form the first side wall.
- 8. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that the material of the protective layer is nitridation Silicon or silicon oxynitride.
- 9. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that the thickness of the protective layer is 10 angstroms ~40 angstroms.
- 10. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that form the initial protective layers Technique includes：Chemical vapor deposition method or atomic layer deposition technique.
- 11. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that remove in the substrate of first area The technique of initial protective layers includes：Anisotropic dry etch.
- 12. the forming method of the semiconductor structure as described in claims 1 to 3 any one claim, it is characterised in that go After the doped layer, in addition to remove the protective layer.
- 13. the forming method of semiconductor structure as claimed in claim 12, it is characterised in that the material of the protective layer is light Photoresist, removing the technique of the protective layer includes cineration technics.
- 14. the forming method of semiconductor structure as claimed in claim 12, it is characterised in that the material of the protective layer is to have Machine ARC, removing the method for the protective layer includes：The protective layer is removed by the bath in photoetching process.
- 15. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of the doped layer is oxygen SiClx or silicon oxynitride；Doped with phosphonium ion or arsenic ion in the doped layer.
- 16. the forming method of the semiconductor structure as described in claims 1 to 3 any one claim, it is characterised in that The step of first area substrate surface formation doped layer, includes：In the first area substrate surface and the second area Initial dopant layer is formed in substrate；Remove the initial dopant layer in the second area substrate.
- 17. the forming method of semiconductor structure as claimed in claim 16, it is characterised in that remove the second area substrate On the technique of initial dopant layer include：Dry etching or wet etching.
- 18. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the first area is used to be formed NMOS；The second area is used to form PMOS；The Doped ions are phosphorus or arsenic.
- 19. the forming method of semiconductor structure as claimed in claim 18, it is characterised in that after removing the doped layer, Also include：The second area substrate is carried out injection is lightly doped, injection ion includes boron ion or BF2Ion.
- 20. the forming method of semiconductor structure as claimed in claim 19, it is characterised in that enter to the second area substrate Row is lightly doped after injection, in addition to：Remove the protective layer.
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