CN107577438B - Method and device for dividing storage space of flash memory in field programmable gate array - Google Patents

Abstract

The embodiment of the invention provides a method and a device for dividing a storage space of a flash memory in a field programmable gate array, belonging to the technical field of Field Programmable Gate Arrays (FPGA). the method for dividing the storage space of the flash memory in the field programmable gate array comprises the steps of receiving the number of divided storage spaces of the flash memory in the input FPGA, wherein the number is a natural number larger than 0, receiving the size of each input storage space, correspondingly dividing the storage space of the flash memory in the FPGA according to the number of the received storage spaces and the size of each storage space, and storing a first address of each storage space in a register.

Description

Method and device for dividing storage space of flash memory in field programmable gate array

technical field

The invention relates to the technical field of field programmable gate array (FPGA), in particular to a method and device for dividing the storage space of flash memory in a field programmable gate array.

Background technique

The field-programmable gate array (FPGA: Field-Programmable Gate Array) is getting larger and larger, which puts forward higher requirements for the convenience of FPGA data storage and the cost of the system. Among many FPGA data storage methods, based on flash memory ( FLASH) FPGA data storage method, compared with other FPGA data storage methods, has been widely used due to its user convenience and lower system cost, and has become the mainstream FPGA data storage method in the industry.

At present, the FPGA storage space division method based on parallel FLASH, the FPGA divides the parallel FLASH into 2 ⁿ equal parts of 2, 4, 8, 16 and so on by controlling the high-order address of the parallel FLASH. The size and quantity of storage space are very limited, which seriously restricts the convenience and flexibility of FPGA data storage. In practical applications, there is often a large waste of space, which greatly increases the cost of the FPGA system.

SUMMARY OF THE INVENTION

The embodiments of the present invention provide a method and device for dividing the storage space of a flash memory in a field programmable gate array, which can improve the convenience and flexibility of FPGA data storage, reduce the waste of storage space in practical applications, and thereby reduce the FPGA system's storage space. cost.

The technical scheme adopted by the present invention to solve the above-mentioned technical problems is as follows:

According to an aspect of the present invention, there is provided a method for dividing a storage space of a flash memory in a field programmable gate array, the method comprising:

The number of divisions of the storage space of the flash memory in the FPGA receiving the input, which is a natural number greater than 0;

the size of each of the storage spaces received as input;

According to the received number of the storage spaces and the size of each storage space, the storage space of the flash memory in the FPGA is divided correspondingly.

Store the first address of each of the storage spaces in a register.

In one embodiment, the above-mentioned flash memory includes parallel flash memory.

In one of the embodiments, the method for dividing the storage space of the flash memory in the field programmable gate array further includes:

When this flash memory is selected, obtain the first address of this storage space stored in this register through the address bus interface of this FPGA;

The data stored in the storage space corresponding to the first address is read, or when the data is received, the data is stored in the storage space corresponding to the first address.

In one of the embodiments, the method for dividing the storage space of the flash memory in the field programmable gate array further includes:

On the falling edge of the first clock, select the flash memory according to the high-level signal of the chip select output port of the FPGA jumping;

At the falling edge of the next clock of the first clock, obtain the first address of the storage space stored in the register through the address bus output port of the FPGA;

On the falling edge of each clock within the clock cycle after the next clock, the data stored in the storage space corresponding to the first address is sent through the data bus output port of the FPGA;

On the rising edge of each clock within the clock cycle after the next clock, the received data is stored in the storage space corresponding to the first address through the data bus input port of the FPGA.

In one of the embodiments, the method for dividing the storage space of the flash memory in the field programmable gate array further includes:

When the flash memory is selected, the chip select output port of the FPGA jumps to a low level.

In one of the embodiments, the method for dividing the storage space of the flash memory in the field programmable gate array further includes:

After obtaining the first address of the storage space stored in the register, the address valid output port of the FPGA jumps to a high level.

According to another aspect of the present invention, a device for dividing a storage space of a flash memory in a field programmable gate array is provided, and the device for dividing a storage space of a flash memory in the field programmable gate array includes:

The first receiving module is used to receive the number of divided storage spaces of the flash memory in the input FPGA, and the number is a natural number greater than 0;

The second receiving module is used to receive the size of each input storage space;

The division module is configured to divide the storage space of the flash memory in the FPGA correspondingly according to the received number of the storage space and the size of each storage space.

The storage module is used for storing the first address of each storage space in the register.

In one embodiment, the above-mentioned flash memory includes parallel flash memory, and the device for dividing the storage space of the flash memory in the field programmable gate array includes:

The first address obtaining module is used to obtain the first address of the storage space stored in the register through the address bus interface of the FPGA when the flash memory is selected;

The data access module is used for reading the data stored in the storage space corresponding to the first address, or saving the data in the storage space corresponding to the first address when data is received.

In one of the embodiments, the device for dividing the storage space of the flash memory in the field programmable gate array further includes:

The flash memory selection module is used to select the flash memory according to the high-level signal of the chip selection output port of the FPGA on the falling edge of the first clock;

The first address obtaining module is specifically used to obtain the first address of the storage space stored in the register through the address bus output port of the FPGA at the falling edge of the next clock of the first clock;

The data access module includes:

A data storage unit, used for sending the data stored in the storage space corresponding to the first address through the data bus output port of the FPGA on the falling edge of each clock within the clock cycle after the next clock;

The data sending unit is used for storing the received data in the storage space corresponding to the first address through the data bus input port of the FPGA on the rising edge of each clock within the clock cycle after the next clock.

In one of the embodiments, the device for dividing the storage space of the flash memory in the field programmable gate array further includes:

The first level jumping module is used for jumping the address valid output port of the FPGA to a high level after obtaining the first address of the storage space stored in the register.

The invention divides the storage space of the flash memory according to the number of input storage spaces and the capacity of each divided storage space, so that the user can perform any number of storage operations on the storage space of the flash memory according to the actual data storage requirements. Arbitrary size division, compared with the traditional parallel FLASH-based FPGA storage space division method, solves the technical problem of limited storage space size and quantity, significantly improves the convenience and flexibility of FPGA data storage, and makes practical applications. The user can divide the storage space of parallel FLASH according to the size and quantity of the data to be stored, which completely avoids the space waste in the traditional FPGA storage space division method based on parallel FLASH, and significantly reduces the cost of the FPGA system.

Description of drawings

1 is a schematic diagram of the connection between a field programmable gate array FPGA and a flash memory FLASH according to an embodiment of the present invention;

2 is a flowchart of a method for dividing a storage space of a flash memory in a field programmable gate array according to an embodiment of the present invention;

3 is a flowchart of a method for dividing a storage space of a flash memory in a field programmable gate array according to another embodiment of the present invention;

4 is an operation sequence diagram of a method for dividing FPGA storage space based on parallel FLASH storage according to an embodiment of the present invention;

5 is a block diagram of an exemplary structure of an apparatus for dividing a storage space of a flash memory in a field programmable gate array according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

1 is a schematic diagram of the connection between a field programmable gate array FPGA and a flash memory FLASH according to an embodiment of the present invention, and the connection between the field programmable gate array FPGA and the flash memory FLASH according to an embodiment of the present invention will be described in detail below with reference to FIG. 1 Relationship, as shown in Figure 1, FPGA and parallel FLASH interconnection, where:

The clock output port CLK of the FPGA is connected to the clock input port of the parallel FLASH;

The chip select output port CE_N of the FPGA is connected to the chip select input port of the parallel FLASH;

The output enable output port OE_N of the FPGA is connected to the output enable input port of the parallel FLASH;

The address valid output port ADV_N of the FPGA is connected to the address valid input port of the parallel FLASH;

The address bus output port A[25:0] of the FPGA is connected to the address bus input port of the parallel FLASH;

The data bus input port D[15:0] of the FPGA is connected to the data bus output port of the parallel FLASH.

Among them, BPI (Business Process Improvement) in Figure 1 represents business process improvement.

The field programmable gate array FPGA, the flash memory FLASH and the connection relationship between the two provided in this embodiment provide hardware support for the following method for dividing the storage space of the flash memory in the field programmable gate array.

FIG. 2 is a flowchart of a method for dividing the storage space of a flash memory in a field programmable gate array according to an embodiment of the present invention. The flash memory in a field programmable gate array according to an embodiment of the present invention will be described in detail below with reference to FIG. 2 . The storage space division method of the invention is applied to a field programmable gate array FPGA including flash memory FLASH, and the method includes the following steps S101 to S104.

S101. Receive the number of divided storage spaces of the flash memory in the input FPGA, where the number is a natural number greater than 0.

According to an example of this embodiment, the above-mentioned number of divided storage spaces is no longer limited to 2 ⁿ in the traditional solution, but can be any number greater than 0. The user can divide the storage space of the flash memory by means of a mouse, a keyboard, etc. and by means of computer input.

S102. Receive the input size of each storage space.

According to an example of this embodiment, when the input size of each storage space is not received, the size of the storage space may be stored equally based on the received number, that is, the default value is each storage space. The storage spaces are all the same size. According to another example of this embodiment, the user may also customize the size of the divided storage space, and divide the corresponding number and size according to actual data storage requirements.

S103. According to the received number of the storage spaces and the size of each storage space, correspondingly divide the storage space of the flash memory in the FPGA.

S104: Store the first address of each storage space in a register.

In one embodiment, the above-mentioned flash memory includes parallel flash memory. Parallel flash memory has the characteristics of high data throughput and fast data access speed.

In this embodiment, the storage space of the flash memory is divided according to the number of input storage spaces and the capacity of each divided storage space, so that the user can perform any number of storage spaces of the flash memory according to actual data storage requirements. , Arbitrary size division, compared with the traditional parallel FLASH-based FPGA storage space division method, it solves the technical problem of limited storage space size and quantity, significantly improves the convenience and flexibility of FPGA data storage, and makes practical In the application, the user can divide the storage space of parallel FLASH according to the size and quantity of the data to be stored, which completely avoids the space waste in the traditional parallel FLASH-based FPGA storage space division method, and significantly reduces the cost of the FPGA system.

3 is a flowchart of a method for dividing the storage space of a flash memory in a field programmable gate array according to another embodiment of the present invention. In this embodiment, the above-mentioned division of the storage space of a flash memory in the field programmable gate array In addition to the above steps S101 to S104, the method further includes the following steps S201 and S202.

S201. When the flash memory is selected, obtain the first address of the storage space stored in the register through an address bus interface of the FPGA.

According to an example of this embodiment, the above-mentioned flash memory is selected by the transition of high and low levels. When the chip select output port signal CE_N of the FPGA changes from high level 1 to low level 0, the parallel FLASH is selected. When the chip select output port signal CE_N of the FPGA changes from a low level 0 to a high level 1, it indicates that the data access in the parallel flash memory is over, and the selection of the parallel FLASH is released.

S202. Read the data stored in the storage space corresponding to the first address, or save the data in the storage space corresponding to the first address when data is received.

According to an example of this embodiment, after reading the data in the storage space corresponding to the first address, the data may be sent to other electronic devices, such as computer devices, which is not limited here.

In one embodiment, the method further includes:

On the falling edge of the first clock, select the flash memory according to the high-level signal of the chip select output port of the FPGA jumping;

At the falling edge of the next clock of the first clock, obtain the first address of the storage space stored in the register through the address bus output port of the FPGA;

On the falling edge of each clock within the clock cycle after the next clock, the data stored in the storage space corresponding to the first address is sent through the data bus output port of the FPGA;

On the rising edge of each clock within the clock cycle after the next clock, the received data is stored in the storage space corresponding to the first address through the data bus input port of the FPGA.

In this embodiment, by adapting the level signals of various interfaces in different clocks, the field programmable gate array FPGA that is spatially divided according to the method for dividing the storage space of the flash memory in the field programmable gate array provided in this embodiment can be compatible with Various protocol specifications applicable to FPGA.

In one embodiment, the method further includes:

When the flash memory is selected, the chip select output port of the FPGA jumps to a low level.

In one embodiment, the method further includes:

After obtaining the first address of the storage space stored in the register, the address valid output port of the FPGA jumps to a high level.

According to an example of this embodiment, the labels of the above steps S101 to S202 are not used to limit the sequence of each step in this embodiment, and the numbers of each step are only for the convenience of referring to the labels of the steps when describing each step. It means that as long as the order in which each step is performed does not affect the logic of this embodiment, it is within the scope of protection claimed in this application.

4 is an operation sequence diagram of a method for dividing FPGA storage space based on parallel FLASH storage according to an embodiment of the present invention. After the FPGA chip is powered on, as shown in FIG. 4 , the FPGA fetches data from the parallel FLASH, and its specific sequence flow is as follows said.

On the falling edge of the clock, the chip select output port signal CE_N of the FPGA changes from 1 to 0, and the parallel FLASH is selected.

On the next clock falling edge, the FPGA address valid output port ADV_N changes from 1 to 0, and the parallel FLASH receives the address stored in the FPGA's address register 0 from the FPGA's address bus output port A[25:0] on the next clock rising edge.

At the next falling edge of the clock, the FPGA address valid output port ADV_N changes from 0 to 1, and the FPGA output enable output port OE_N changes from 1 to 0. Address transmission ends and data transmission begins.

At each subsequent falling edge of the clock, the FLASH takes the address received from the address bus output port A[25:0] of the FPGA as the first address, and sends data from the data bus output port of the parallel FLASH, sending 16 bits per clock cycle. data.

On each subsequent rising edge of the clock, the FPGA receives data from the FPGA's data bus input port D[15:0], 16 bits of data per clock cycle.

After the data in the first part of the space is received, on the falling edge of the clock, the output enable output port OE_N of the FPGA changes from 0 to 1, and the chip select output port signal CE_N of the FPGA changes from 0 to 1. When the data reception ends, the selection of parallel FLASH is released.

If the FPGA needs to read data in other parts of the parallel FLASH, on the falling edge of the clock, the FPGA chip select output port signal CE_N changes from 1 to 0, reselects the parallel FLASH, and repeats the above steps.

The FPGA storage space division method based on parallel FLASH storage provided by the present invention is based on the existing parallel FLASH-based FPGA storage space division method, and n address registers are added inside the FPGA for configuring the start of each storage space of the parallel FLASH. starting address.

In this embodiment, by selecting n address registers and allowing users to make arbitrary configurations as required, compared with the traditional FPGA storage space division method based on parallel FLASH storage, the problem of the limitation of the size and quantity of storage space is solved, and the FPGA is significantly improved. Convenience and flexibility of data storage. In practical applications, the parallel FLASH storage space can be divided according to the size and quantity of the data to be stored, which completely avoids the space waste in the traditional parallel FLASH-based FPGA storage space division method, and significantly reduces the cost of the FPGA system.

5 is a block diagram of an exemplary structure of an apparatus for dividing the storage space of a flash memory in a field programmable gate array according to an embodiment of the present invention. The following describes the field programmable gate array in an embodiment of the present invention in detail with reference to FIG. 5 . The device for dividing the storage space of flash memory, the device 10 for dividing the storage space of flash memory in the field programmable gate array includes the following first receiving module 11 , second receiving module 12 , dividing module 13 and storage module 14 .

The first receiving module 11 is configured to receive the number of divided storage spaces of the flash memory in the input FPGA, where the number is a natural number greater than 0.

According to an example of this embodiment, the above-mentioned number of divided storage spaces is no longer limited to 2 ⁿ in the traditional solution, but can be any number greater than 0. The user can divide the storage space of the flash memory by means of a mouse, a keyboard, etc. and by means of computer input.

The second receiving module 12 is configured to receive the input size of each storage space.

According to an example of this embodiment, when the input size of each storage space is not received, the size of the storage space may be stored equally based on the received number, that is, the second received Modules default to the same size for each storage space. According to another example of this embodiment, the user may also customize the size of the divided storage space, and divide the corresponding number and size according to actual data storage requirements.

The division module 13 is configured to divide the storage space of the flash memory in the FPGA correspondingly according to the received number of the storage spaces and the size of each storage space.

The storage module 14 is configured to store the first address of each storage space in the register.

In one embodiment, the above-mentioned flash memory includes parallel flash memory. Parallel flash memory has the characteristics of high data throughput and fast data access speed.

In one of the embodiments, the device 10 for dividing the storage space of the flash memory in the field programmable gate array further includes:

The first address obtaining module is used to obtain the first address of the storage space stored in the register through the address bus interface of the FPGA when the flash memory is selected;

The data access module is used for reading the data stored in the storage space corresponding to the first address, or saving the data in the storage space corresponding to the first address when data is received.

According to an example of this embodiment, the above-mentioned first address acquisition module includes a flash memory selection unit: used to select the flash memory through a transition of high and low levels, and the flash memory selection unit is specifically used for the chip selection output port signal of the FPGA CE_N changes from high level 1 to low level 0, and the parallel FLASH is selected. On the contrary, when the FPGA chip select output port signal CE_N changes from low level 0 to high level 1, it indicates that the data access in the parallel flash memory is accessed. End, release the selection of parallel FLASH.

According to an example of this embodiment, after reading the data in the storage space corresponding to the first address, the data access module can send the data to other electronic devices, such as computer devices, which is not limited here .

In one of the embodiments, the device 10 for dividing the storage space of the flash memory in the field programmable gate array further includes:

The flash memory selection module is used to select the flash memory according to the high-level signal of the chip selection output port of the FPGA on the falling edge of the first clock;

The first address obtaining module is specifically used to obtain the first address of the storage space stored in the register through the address bus output port of the FPGA at the falling edge of the next clock of the first clock;

The data access module includes:

A data storage unit, used for sending the data stored in the storage space corresponding to the first address through the data bus output port of the FPGA on the falling edge of each clock within the clock cycle after the next clock;

The data sending unit is used for storing the received data in the storage space corresponding to the first address through the data bus input port of the FPGA on the rising edge of each clock within the clock cycle after the next clock.

In one of the embodiments, the device 10 for dividing the storage space of the flash memory in the field programmable gate array further includes:

The first level jumping module is used for jumping the address valid output port of the FPGA to a high level after obtaining the first address of the storage space stored in the register.

In one of the embodiments, the device 10 for dividing the storage space of the flash memory in the field programmable gate array further includes:

The second level jumping module is used for jumping the chip select output port of the FPGA to a low level after the flash memory is selected.

Among them, the meanings of "first" and "second" in the above-mentioned first level jumping module and second level jumping module are only to distinguish the two level jumping modules, and are not used to define which one The level transition module has a higher priority or other limited meaning.

Wherein, each module included in the device for dividing the storage space of the flash memory in the field programmable gate array can be implemented in whole or in part by software, hardware or a combination thereof. Further, each module in the device for dividing the storage space of the flash memory in the field programmable gate array may be a program segment for implementing corresponding functions.

The method and device for dividing the storage space of the flash memory in the field programmable gate array provided by this embodiment divide the storage space of the flash memory according to the number of input storage spaces and the capacity of each divided storage space. , so that users can divide the storage space of flash memory in any number and size according to actual data storage requirements. Compared with the traditional FPGA storage space division method based on parallel FLASH, it solves the problem of limited storage space size and quantity. The technical problem significantly improves the convenience and flexibility of FPGA data storage, so that in practical applications, users can divide the storage space of parallel FLASH according to the size and quantity of data to be stored, completely avoiding the traditional FPGA storage space based on parallel FLASH. The waste of space in the partitioning method significantly reduces the cost of the FPGA system.

The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity, all possible combinations of the technical features in the above-described embodiments are not described. However, as long as there is no contradiction between the combinations of these technical features, All should be regarded as the scope described in this specification.

The above-mentioned embodiments only represent several embodiments of the present invention, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can also be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims (2)

1. A method for dividing the storage space of flash memory in a field programmable gate array, wherein the method comprises: The number of divisions of the storage space of the flash memory in the FPGA receiving the input, and the number is a natural number greater than 0; receiving the input size of each of said storage spaces; According to the received number of the storage spaces and the size of each of the storage spaces, correspondingly divide the storage space of the flash memory in the FPGA; storing the first address of each of the storage spaces in a register; When the flash memory is selected, the first address of the storage space stored in the register is obtained through the address bus interface of the FPGA, and the flash memory is a parallel flash memory; reading the data stored in the storage space corresponding to the first address, and saving the data in the storage space corresponding to the first address when data is received; On the falling edge of the first clock, the flash memory is selected according to the high-level signal of the chip select output port of the FPGA, and after the flash memory is selected, the chip select output port of the FPGA jumps to a low power flat; At the falling edge of the next clock of the first clock, the first address of the storage space stored in the register is obtained through the address bus output port of the FPGA; when all the addresses stored in the register are obtained After the first address of the storage space, the effective output port of the address of the FPGA jumps to a high level; the falling edge of each clock within the clock cycle after the next clock, through the data bus of the FPGA The output port sends the data stored in the storage space corresponding to the first address; on the rising edge of each clock within the clock cycle after the next clock, the data bus input port of the FPGA will receive the data. Data is stored in the storage space corresponding to the first address. 2. A device for dividing the storage space of flash memory in a field programmable gate array, wherein the device comprises: The first receiving module is used to receive the number of divided storage spaces of the flash memory in the input FPGA, and the number is a natural number greater than 0; A second receiving module, configured to receive the input size of each of the storage spaces; A division module, configured to divide the storage space of the flash memory in the FPGA according to the received number of the storage spaces and the size of each of the storage spaces; a storage module for storing the first address of each of the storage spaces in a register; a first address obtaining module, configured to obtain the first address of the storage space stored in the register through the address bus interface of the FPGA when the flash memory is selected, and the flash memory is a parallel flash memory; A data access module, configured to read the data stored in the storage space corresponding to the first address, and save the data in the storage space corresponding to the first address when data is received; The flash memory selection module is used to select the flash memory according to the high level signal of the chip select output port of the FPGA on the falling edge of the first clock, and when the flash memory is selected, the chip select of the FPGA The output port jumps to a low level; The first address obtaining module is specifically configured to obtain the first address of the storage space stored in the register through the address bus output port of the FPGA at the falling edge of the next clock of the first clock; a first level jumping module, configured to jump the address valid output port of the FPGA to a high level after obtaining the first address of the storage space stored in the register; The data access module includes: A data storage unit, used for sending the data stored in the storage space corresponding to the first address through the data bus output port of the FPGA on the falling edge of each clock within the clock cycle after the next clock ; A data sending unit, configured to store the received data in the storage space corresponding to the first address through the data bus input port of the FPGA on the rising edge of each clock within the clock cycle after the next clock middle.

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