CN107564985A - Cell piece component, cell piece matrix and solar cell module - Google Patents

Abstract

The invention discloses a battery slice assembly, a battery slice matrix and a solar battery assembly. The battery slice assembly includes: a plurality of battery slices and conductive strips arranged in sequence along the longitudinal direction, each battery slice includes a silicon chip, and is arranged on a silicon chip. The front conductive part on the light-receiving surface, the two electrodes arranged on the backlight surface of the silicon chip, and the side conductive part arranged on the side surface of the silicon chip and electrically connected between the front conductive part and an electrode, wherein the two electrodes Both extend in the transverse direction and are spaced apart in the longitudinal direction. The conductive strips extend in the same direction as the electrodes, and are electrically connected to the two electrodes that are close to each other and respectively located on two adjacent battery sheets so that the two adjacent battery sheets are connected in series. or in parallel. According to the cell assembly of the present invention, the use length of the conductive tape can be effectively reduced, the usage amount of the conductive tape can be reduced, the thermal effect caused by the conductive tape can be reduced, and the overall power of the cell assembly can be improved.

Description

Cell Modules, Cell Matrix and Solar Cell Modules

technical field

The invention relates to the technical field of solar cells, in particular to a cell assembly, a cell matrix and a solar cell assembly.

Background technique

In the crystalline silicon solar cell in the related art, there are 2-3 silver busbars on the light-receiving side and the backlight side respectively as the positive and negative electrodes of the cell. These silver busbars not only consume a large amount of silver paste, but also block the incident light. As a result, the efficiency of the battery sheet is reduced. In addition, since the positive and negative electrodes are respectively distributed on the light-receiving surface and the backlight surface of the cell, when the cells are connected in series, it is necessary to use a conductive tape to weld the negative electrode on the light-receiving surface of the cell to the positive electrode on the backlight surface of the adjacent cell. As a result, the welding process is cumbersome and the use of more welding materials is problematic. Moreover, the battery sheet and the conductive strip are easily damaged during welding and subsequent lamination processes.

In addition, the cell matrix in the related art is usually composed of 72 or 60 cells connected in series to form three loops consisting of six strings of cells. At this time, at least three diodes are generally required to make each loop A diode is added for bypass protection. Since the diode is usually placed in the junction box of the battery, the cost of the integrated junction box is increased, which increases the structural complexity of the battery. When connecting in series again, the amount of connecting cables is very large, and a lot of materials are wasted, which increases the cost of the power station.

Contents of the invention

The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the invention consists in proposing a solar cell assembly which has a high power output.

The present invention also proposes a cell matrix having the above-mentioned cell assembly.

The present invention also proposes a solar cell module having the above cell matrix.

The battery sheet assembly according to the first aspect of the present invention includes: a plurality of battery sheets arranged in sequence along the longitudinal direction, each of the battery sheets includes a silicon chip, a front conductive member arranged on the light-receiving surface of the silicon chip, a device Two electrodes on the backlight surface of the silicon wafer, and a side conductive member arranged on the side surface of the silicon wafer and electrically connected between the front conductive member and one of the electrodes, wherein the two The electrodes extend laterally and are spaced apart in the longitudinal direction; the conductive strips extend in the same direction as the electrodes and are adjacent to each other and are located on two adjacent battery sheets respectively. The electrodes are electrically connected so that two adjacent battery sheets are connected in series or in parallel.

According to the cell assembly of the present invention, the use length of the conductive tape can be effectively reduced, the usage amount of the conductive tape can be reduced, the thermal effect caused by the conductive tape can be reduced, and the overall power of the cell assembly can be increased.

In some embodiments, in the extending direction of the conductive strip, the extension length of the conductive strip is greater than or equal to the extension length of each of the electrodes connected by the conductive strip, and the two ends of the conductive strip respectively protruding from or level with the corresponding end of each of said electrodes conducted by said conductive strips.

In some embodiments, in a direction perpendicular to the extending direction of the conductive strip, the span of the conductive strip is greater than or equal to the sum of the spans of the two electrodes connected by the conductive strip, and the conductive strip The two sides of the electrode respectively exceed or are parallel to the two sides of the two electrodes connected by the conductive strip that are far away from each other.

In some embodiments, the conductive strip includes two halves that have the same structure and are sequentially arranged in a direction perpendicular to the extending direction of the conductive strip, and each half just covers two the electrodes.

In some embodiments, in a direction perpendicular to the extending direction of the conductive strip, the gap between every two adjacent battery pieces is less than or equal to 0.1 mm.

In some embodiments, the silicon chip has a span of 20mm-60mm in a direction perpendicular to the side surface where the side conductive member is located.

In some embodiments, the silicon wafer is a rectangular wafer and is divided into regular square silicon wafer bodies according to the rule of constant length.

In some embodiments, the silicon chip is a rectangular piece, and the two electrodes are respectively arranged adjacent to the two long sides of the silicon chip and both extend along the length direction of the silicon chip. It is provided on one long side surface of the silicon chip.

In some embodiments, the two electrodes on each battery sheet are respectively a first electrode electrically connected to the side conductive member and a second electrode not electrically connected to the side conductive member, and the silicon The sheet includes: a silicon substrate, a front first-type diffusion layer and a back spacer, wherein the backlight surface of the silicon substrate includes a first area and a second area, and the front first-type diffusion layer is arranged on the silicon On the light-receiving surface of the substrate, the front conductive member is arranged on the front first-type diffusion layer, the back spacer is only arranged on and covers the first area, and the first electrode is arranged on the On the back spacer, the second electrode is arranged on the second region and is not in contact with the first electrode, wherein at least part of the back spacer is an insulating layer or is first connected to the front side. A diffusion layer of the same type as a diffusion layer.

In some embodiments, the silicon chip further includes: a side spacer, the side spacer is disposed on the side surface of the silicon substrate, the side conductive member is disposed on the side spacer, the At least part of the side spacer is an insulating layer or a diffusion layer of the same type as the first type of diffusion layer on the front side.

In some embodiments, each battery sheet further includes: a back electric layer, the back electric layer is arranged on the second region, the second electrode is arranged on the back electric layer and is connected to the The back electric layer is electrically connected.

In some embodiments, each battery sheet further includes: a second grid line layer on the back side, the second grid line layer on the back side and the second electrode are both arranged on the second region, and the first grid line layer is arranged on the second region. The two electrodes are electrically connected to the second gate line layer on the back side and do not overlap with each other.

In some embodiments, the silicon wafer further includes a second-type diffusion layer on the back that is different in type from the first-type diffusion layer on the front, and the second-type diffusion layer on the back is only provided on and covers In the area, the second grid line layer on the back side and the second electrode are both arranged on the second type diffusion layer on the back side.

In some embodiments, each battery sheet further includes: a first grid line layer on the back side, the first grid line layer on the back side and the first electrode are both arranged on the back spacer, and the first grid line layer on the back side An electrode is electrically connected to the first gate line layer on the back side and does not overlap with each other.

In some embodiments, the back spacer is a rear first-type diffusion layer of the same type as the front first-type diffusion layer, and the back first-type diffusion layer is only provided and covered on the first In the region, the first grid line layer on the back side and the first electrode are both arranged on the first type diffusion layer on the back side.

In some embodiments, both the first area and the second area are non-discrete areas.

In some embodiments, the first area and the second area are interdigitated, wherein the first area includes a first connected area and a plurality of first dispersed areas, and a plurality of first dispersed areas Areas are spaced apart in the length direction of the first communication area and all communicate with the first communication area, the second area includes a second communication area and a plurality of second dispersed areas, and a plurality of the second dispersed areas The areas are spaced apart in the length direction of the second communication area and all communicate with the second communication area, wherein the first communication area and the second communication area are arranged in parallel, and a plurality of the first communication areas are distributed A region and a plurality of said second dispersed regions alternate one by one between said first connected region and said second connected region.

The battery slice matrix according to the second aspect of the present invention is formed by connecting multiple battery slice parallel components in series, wherein each of the battery slice parallel components is formed by connecting multiple battery slice series components in parallel, wherein each of the battery slices The battery slice assemblies are all battery slice assemblies according to the first aspect of the present invention, and a plurality of the battery slices in each battery slice assembly are serially connected in series by the conductive strips.

According to the battery slice matrix of the present invention, the overall power of the battery slice matrix is improved by arranging the battery slice assembly of the first aspect.

In some embodiments, there are two parallel assemblies of battery slices, and each parallel assembly of battery slices includes three series assemblies of battery slices.

The solar cell assembly according to the third aspect of the present invention includes a first panel, a first adhesive layer, a battery, a second adhesive layer and a second panel arranged in sequence from the light-receiving side to the backlight side, wherein the battery is according to The cell assembly according to the first aspect of the present invention or the cell matrix according to the second aspect of the present invention.

According to the solar cell assembly of the present invention, the overall performance of the solar cell assembly is improved by arranging the cell matrix of the second aspect or the cell assembly of the first aspect.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

FIG. 1 is a schematic diagram of a cell assembly according to an embodiment of the present invention;

Fig. 2 is a schematic diagram of removing the conductive band in Fig. 1;

Fig. 3 is a schematic diagram of a cell matrix according to an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of the cell matrix shown in FIG. 3 .

Fig. 5 is a schematic diagram of the photometry of the cell according to Embodiment 1 of the present invention;

Fig. 6 is a schematic diagram of the backlight side of the battery sheet shown in Fig. 5;

Fig. 7 is a schematic diagram of one side of the battery sheet shown in Fig. 5;

Fig. 8 is a schematic diagram showing that two battery sheets shown in Fig. 6 are connected by conductive strips;

Fig. 9 is a schematic diagram of removing the conductive band in Fig. 8;

Fig. 10 is a schematic diagram of light-receiving measurement of a battery sheet according to Embodiment 2 of the present invention;

Fig. 11 is a schematic diagram of the backlight side of the battery sheet shown in Fig. 10;

Fig. 12 is a schematic diagram of one side of the battery sheet shown in Fig. 10;

Fig. 13 is a schematic diagram of connecting the two battery sheets shown in Fig. 11 with conductive strips;

Fig. 14 is a schematic diagram of removing the conductive band in Fig. 13;

Fig. 15 is a schematic diagram of the photometry of the cell according to Embodiment 3 of the present invention;

Fig. 16 is a schematic diagram of the backlight side of the battery sheet shown in Fig. 15;

Fig. 17 is a schematic diagram of one side of the battery sheet shown in Fig. 15;

Fig. 18 is a schematic diagram of two battery sheets shown in Fig. 16 being connected by conductive strips;

Fig. 19 is a schematic diagram of removing the conductive band in Fig. 18;

Fig. 20 is a schematic diagram of light-receiving measurement of a cell according to Embodiment 4 of the present invention;

Fig. 21 is a schematic diagram of the backlight side of the battery sheet shown in Fig. 20;

Fig. 22 is a schematic diagram of one side of the battery sheet shown in Fig. 20;

Fig. 23 is a schematic diagram of the two cells shown in Fig. 21 being connected by conductive strips;

Figure 24 is a schematic diagram of removing the conductive band in Figure 23;

Fig. 25 is a schematic diagram of the photometry of the cell according to Embodiment 5 of the present invention;

Fig. 26 is a schematic diagram of the backlight side of the battery sheet shown in Fig. 25;

Fig. 27 is a schematic view of one side of the battery sheet shown in Fig. 25;

Fig. 28 is a schematic diagram of another side of the battery sheet shown in Fig. 25;

Fig. 29 is a diagram of the preparation process of the backlight side of the battery sheet shown in Fig. 26;

Fig. 30 is a schematic diagram of connecting the two battery sheets shown in Fig. 26 with conductive strips;

Figure 31 is a schematic diagram of removing the conductive band in Figure 30;

Fig. 32 is a schematic diagram of light-receiving measurement of a cell according to Embodiment 6 of the present invention;

Fig. 33 is a schematic diagram of the backlight side of the battery sheet shown in Fig. 32;

Fig. 34 is a schematic diagram of one side of the battery sheet shown in Fig. 32;

Fig. 35 is a schematic diagram of another side of the battery sheet shown in Fig. 32;

Fig. 36 is a diagram of the preparation process of the backlight side of the battery sheet shown in Fig. 33;

Fig. 37 is a schematic diagram of connecting the two cells shown in Fig. 33 with conductive strips;

Figure 38 is a schematic diagram of removing the conductive band in Figure 37;

Fig. 39 is a schematic diagram of a battery sheet receiving light according to Embodiment 7 of the present invention;

Fig. 40 is a schematic diagram of the backlight side of the battery sheet shown in Fig. 39;

Figure 41 is a schematic view of one side of the battery sheet shown in Figure 39;

Fig. 42 is a schematic diagram of another side of the battery sheet shown in Fig. 39;

Fig. 43 is a diagram of the preparation process of the backlight side of the battery sheet shown in Fig. 40;

Fig. 44 is a schematic diagram of connecting the two battery sheets shown in Fig. 40 with conductive strips;

FIG. 45 is a schematic diagram of removing the conductive band in FIG. 44 .

Reference signs:

Cell series assembly 1000; cell parallel assembly 2000; cell matrix 10000;

Conductive strip 1001; bus bar 1002; cell assembly 100A;

Cell 100; Cell A; Cell B; Electrode A1; Electrode A2; Electrode B1; Electrode B2;

Silicon wafer 1; silicon substrate 11; antireflection layer 101; passivation layer 102;

The first type of diffusion layer 12 on the front side; the side spacer 13; the back side spacer 14; the second type of diffusion layer 15 on the back side;

Front grid line layer 2; Front sub grid line 21;

Side conductive member 3; first electrode 4; second electrode 5;

The second gate line layer 6 on the back; the second sub-gate line 61 on the back; the back electric layer 60;

The first gate line layer 7 on the back side; the first sub-gate line 71 on the back side.

detailed description

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.

The battery sheet assembly 100A according to the embodiment of the first aspect of the present invention will be described below with reference to the accompanying drawings 1 to 45 .

The battery sheet assembly 100A according to the embodiment of the first aspect of the present invention includes: at least two battery sheets 100 and at least one conductive strip 1001 . Wherein, the battery sheet 100 is a back-contact solar battery sheet.

Specifically, each solar cell 100 includes a silicon wafer 1, a front conductive member (such as the front grid line layer 2 described below) provided on the light-receiving surface of the silicon wafer 1, and two conductive elements provided on the backlight surface of the silicon wafer 1. Electrodes (such as the first electrode 4 and the second electrode 5 described below), and the side conductive member 3 that is arranged on the side surface of the silicon wafer 1 and is electrically connected between the front conductive member and an electrode, wherein the two electrodes Positive and negative electrodes with opposite polarities and not in contact with each other. In this way, when the light-receiving surface of the silicon wafer 1 is irradiated with light, the front conductive member can collect a kind of charge from the light-receiving surface of the silicon wafer 1 and transfer it to an electrode electrically connected to it through the side conductive member 3, and the other electrode is on the silicon wafer. The backlight side of 1 gets another kind of charge, so that the two electrodes can output electric energy.

Specifically, a plurality of battery sheets 100 are arranged longitudinally in sequence in such a way that the light-receiving surfaces face the same side, for example, facing the sun, and the backlight surfaces face the same side, for example, facing away from the sun. Both electrodes extend laterally and are spaced apart vertically to ensure that the two electrodes are not in contact with each other to avoid short circuits. Here, it should be noted that the "extending direction of the electrodes" mentioned herein refers to the length of the electrodes Direction, the “extending direction of the conductive strip 1001 ” mentioned below refers to the length direction of the conductive strip 1001 . Here, it should be noted that the "transverse" mentioned herein refers to the extending direction of the transverse lines, such as the horizontal direction shown in Figures 1 and 2, and the "longitudinal" refers to the extending direction of the longitudinal lines, such as In the vertical direction shown in Figure 1 and Figure 2, the transverse line and the longitudinal line are straight lines perpendicular to each other; in addition, "extend along the transverse direction" is taken as a broad understanding, that is, it should include "extend in a direction parallel to the transverse line" and "Extending in a direction at an angle of less than 45° to a transverse line".

Specifically, the extension direction of the conductive strip 1001 is the same as that of the electrodes so as to be fully electrically connected to the electrodes and improve the conduction efficiency. Two adjacent battery slices 100 are connected in series or in parallel. Here, for the sake of clarity, for example, referring to FIG. 1 and FIG. 2 , it is assumed that two adjacent battery sheets 100 are battery sheet A and battery sheet B respectively, and battery sheet A has electrodes A1 and electrodes A2 spaced apart in the longitudinal direction. There are electrodes B1 and B2 spaced apart in the longitudinal direction on the battery sheet B. When the battery sheet A and the battery sheet B are arranged in sequence along the longitudinal direction, the electrode A1, the electrode A2, the electrode B1 and the electrode B2 are arranged in sequence along the longitudinal direction. At this time, The electrode A2 and the electrode B1 are close to each other, and the electrode A1 and the electrode B2 are far away from each other. At this time, the conductive strip 1001 is electrically connected to the electrode A2 and the electrode B1 respectively to conduct the electrode A2 and the electrode B1. At this time, when the electrode A2 and the electrode B1 When the polarities of the electrodes are the same (that is, both are positive electrodes or both are negative electrodes), battery sheet A and battery sheet B can be connected in parallel, and when the polarities of electrode A2 and electrode B1 are different (that is, one is a positive electrode and the other is a negative electrode) electrode), cell A and cell B can be connected in series.

Below, only take the vertical direction shown in Figure 1 and Figure 2 as "longitudinal", and the horizontal direction shown in Figure 1 and Figure 2 as "horizontal" as an example for illustration. Of course, those skilled in the art will read the After the following technical solutions, it is obvious that other directions can be understood as "vertical" technical solutions. In addition, it should be noted that the orientations or positional relationships shown in the drawings of the present application are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred devices or elements must have specific orientations and configuration and operation, and therefore should not be construed as limiting the invention.

As shown in Figures 1 and 2, a plurality of battery sheets 100 are arranged in sequence in the up-down direction, wherein the two electrodes on each battery sheet 100 extend along the left-right direction and are spaced apart in the up-down direction, so that each Each of the upper and lower parts of each battery slice 100 has an electrode respectively, so that the upper electrodes (eg, electrode B1) of the remaining battery slices 100 (eg, battery slice B) except the uppermost battery slice 100 (eg, battery slice A) ) and the lower electrode (such as electrode A2) of the battery sheet 100 above it (such as battery sheet A) are close to each other and can be conducted through the conductive strip 1001, that is, except for the lowermost battery sheet 100 (such as battery sheet B) The lower electrodes (such as electrode A2) of the remaining battery slices 100 (such as battery slices A) and the upper electrodes (such as electrode B1) of the battery slices 100 below (such as battery slices B) are close to each other and can be conducted through the conductive strip 1001 .

Therefore, according to the battery sheet assembly 100A of the embodiment of the present invention, the total area of the conductive strip 1001 can be effectively reduced, the thermal effect caused by the conductive strip 1001 can be reduced, the usage of the conductive strip 1001 can be reduced, and the overall power of the battery sheet assembly 100A can be increased. . Wherein, the conductive strip 1001 may be a solder strip.

Next, a cell matrix 10000 according to an embodiment of the second aspect of the present invention will be described with reference to FIGS. 3 and 4 .

Specifically, when a plurality of battery slices 100 in the battery slice assembly 100A are serially connected in series by the conductive strip 1001 , the battery slice assembly 100A is a battery slice series assembly 1000 . The battery slice matrix 10000 is composed of a plurality of battery slice parallel assemblies 2000 connected in series, wherein each battery slice parallel assembly 2000 is formed by a plurality of battery slice series assemblies 1000 connected in parallel. That is to say, multiple battery slice series assemblies 1000 are first connected in parallel to form multiple battery slice parallel assembly assemblies 2000 , and then multiple battery slice parallel assembly assemblies 2000 are connected in series to form a battery slice matrix 10000 . Thus, the power of the cell matrix 10000 is effectively increased, and there is no need to add diodes for bypass protection, which reduces the cost of the battery. In addition, the positive and negative junction boxes can be distributed on both sides of the cell matrix 10000, thereby reducing The amount of connecting cables between adjacent components is reduced, and the cost of the power station is reduced.

For example, in a preferred embodiment of the present invention, there are two battery slice parallel assemblies 2000 , and each battery slice parallel assembly 2000 is composed of three battery slice series assemblies 1000 connected in parallel. That is to say, the method of "first three parallel and then two strings" is used to form six cell series assemblies 1000 into a cell matrix 10000, that is, to first connect six cell series assemblies 1000 in threes and threes in parallel to form two cell parallel assemblies 2000 , and then connect two battery slice parallel assemblies 2000 in series to form a battery slice matrix 10000.

Here, it should be noted that the cell matrix in the related art usually includes 60 sequentially connected cells, wherein every 10 cells are first connected in series to form a cell string, and then 6 cell strings are connected in sequence, so that 60 The cells can all be connected in series in sequence. When the voltage of each cell is 0.5V, the voltage of 60 cells connected in series is 30V. At this time, if there is a problem with one cell string, the entire cell matrix will not work properly, so It is necessary to connect three diodes in parallel, so that even if there is a problem with one battery string, the circuit will still form a loop through the parallel diodes, and the battery matrix can continue to work normally without being scrapped, but the power is lower. However, on the one hand, the production cost of the diode is relatively high; Cassettes also increase production costs. In addition, since the junction box is located in the center of the modules, when the modules are connected in series, a large amount of connecting cables is used, which wastes materials and increases the cost of the power station.

In comparison, the battery slice 100 in this paper can be 1/4 of the conventional battery slice. At this time, the total voltage of the battery slice series assembly 1000 composed of 10 battery slices 100 in series is 20V (that is, 40×0.5V= 20V), then the voltage of 40V can be achieved by connecting two such battery slice series assemblies 1000 in series, so that the working voltage can be effectively reached. In addition, when adopting the above-mentioned method of "first paralleling three and then two strings" to form the cell matrix 10000, since the parallel structure itself can protect the parallel bypass, there is no need to add additional diodes for bypass. Road protection, reducing production costs. In addition, since the positive and negative junction boxes can be distributed on both sides of the cell matrix 10000, the amount of cables used for connecting components to components is reduced, further reducing the cost of the power station.

Solar cell modules according to embodiments of the third aspect of the present invention are described below.

Specifically, the solar cell module includes: a first panel, a first bonding layer, a battery, a second bonding layer and a second panel arranged in sequence from the light-receiving side to the backlight side. Wherein, the battery may be the battery chip assembly 100A of the above-mentioned embodiment of the first aspect, or the battery chip matrix 10000 of the above-mentioned embodiment of the second aspect. Therefore, the power of the solar cell module is better, the energy efficiency is better, the processing is easier, and the cost is lower.

The preparation method of the solar cell module according to the embodiment of the fourth aspect of the present invention will be described below.

First, a battery is prepared.

Specifically, when the battery is a battery sheet assembly 100A, two adjacent battery sheets 100 can be connected in series or in parallel with the conductive tape 1001 first to obtain the battery sheet assembly 100A, and then the bus bar 1002 is used to connect the battery sheet assembly 100A The positive and negative electrodes are connected separately.

Specifically, when the battery is a matrix of battery slices 10000, two adjacent battery slices 100 can be connected in series first by using a conductive strip 1001 to obtain a plurality of battery slice series assemblies 1000, and then a plurality of battery slices can be connected in series by using a bus bar 1002 The components 1000 are connected in parallel to obtain a plurality of battery slice parallel components 2000, and then the bus bars 1002 are used to connect the multiple battery slice parallel components 2000 in series to obtain a battery slice matrix 10000, and finally the bus bars 1002 are used to connect the positive and negative electrodes of the battery slice matrix 10000 Pick up separately.

Next, lay the first panel, the first adhesive layer, the battery, the second adhesive layer and the second panel sequentially in the up and down direction to obtain a laminated structure, and then laminate and package the laminated structure. For example, the first panel (such as glass), the first bonding layer (such as EVA), the battery, the second bonding layer (such as EVA), and the second panel (such as EVA) can be laid in sequence from bottom to top. Battery backsheet or glass) to obtain a laminated structure, and then, put the laminated structure in the previous step into a laminator for lamination, and install the junction box and frame to realize the packaging and production of solar cell modules.

The battery sheet 100 according to multiple embodiments of the present invention will be described below with reference to FIG. 1 and FIG. 2 and in conjunction with FIG. 5-FIG. 45 .

In one embodiment of the present invention, in the extending direction of the conductive strip 1001, the extension length of the conductive strip 1001 is greater than or equal to the extension length of each electrode connected by the conductive strip 1001, and the two ends of the conductive strip 1001 respectively exceed Or flush with the corresponding end of each electrode conducted by the conductive strip 1001. However, it should be noted that when the two ends of the conductive strip 1001 respectively exceed the corresponding ends of each electrode conducted by the conductive strip 1001, the conductive strip 1001 needs to be connected with each silicon chip 1 and is conducted by the conductive strip 1001. The conductive medium with the opposite charge carried by the connected electrode keeps a certain safety distance, so as to avoid the short circuit of the two electrodes on the same silicon wafer 1 .

For example, in the example shown in Fig. 1 and Fig. 2, the electrode A2 and the electrode B1 both extend along the horizontal direction, and the conductive strip 1001 also extends along the horizontal direction, and the length of the conductive strip 1001 in the horizontal direction is greater than or equal to that of the electrode A2 in the horizontal direction At the same time, it is also greater than or equal to the length of the electrode B1 in the horizontal direction. The two ends of the conductive strip 1001 in the horizontal direction are the left and right ends respectively, and the left end of the conductive strip 1001 exceeds or is equal to the left end of the electrode A2 to the left. , At the same time, the left end of the conductive strip 1001 also exceeds or is equal to the left end of the electrode B1 to the left, and the right end of the conductive strip 1001 exceeds or is equal to the right end of the electrode A2 to the right. At the same time, the right end of the conductive strip 1001 is also to the right Beyond or flush with the right end of the electrode B1, at the same time, the left and right ends of the conductive strip 1001 should also be kept in constant contact with the electrode A1, the conductive medium electrically connected with the electrode A1, the electrode B2, and the conductive medium electrically connected with the electrode B2. Safe distance to avoid short-circuit connection between electrode A1 and electrode A2, while avoiding short-circuit connection between electrode B1 and electrode B2. Thus, it can ensure that the conductive strip 1001 is fully connected to the electrodes, reduce the total area of the conductive strip 1001, reduce the thermal effect caused by the conductive strip 1001, reduce the usage of the conductive strip 1001, and increase the overall power of the cell assembly 100A.

In one embodiment of the present invention, in the direction perpendicular to the extending direction of the conductive strip 1001, the span of the conductive strip 1001 is greater than or equal to the sum of the spans of the two electrodes connected by the conductive strip 1001, and the two sides of the conductive strip 1001 The sides respectively exceed or are parallel to the two sides where the two electrodes connected by the conductive strip 1001 are far away from each other. However, it should be noted that when the two sides of the conductive strip 1001 respectively exceed the two sides where the two electrodes connected by the conductive strip 1001 are far away from each other, the conductive strip 1001 needs to be connected with each silicon chip 1 and is The conductive medium with the opposite charge carried by the conductive electrode of the conductive strip 1001 is kept at a certain safe distance, so as to avoid short-circuiting of two electrodes on the same silicon chip 1 .

For example, in the example shown in Fig. 1 and Fig. 2, electrode A2 and electrode B1 both extend along the horizontal direction, and the conductive strip 1001 also extends along the horizontal direction, and the width of the conductive strip 1001 in the vertical direction is greater than or equal to that of the electrode A2 in the vertical direction. The sum of the width in the direction and the width of the electrode B1 in the vertical direction, the two sides of the conductive strip 1001 in the vertical direction are the upper and lower sides respectively, and the upper side of the conductive strip 1001 exceeds or is equal to The upper side of the electrode A2 and the lower side of the conductive strip 1001 are lower than or flush with the lower side of the electrode B1, and the upper and lower sides of the conductive strip 1001 are also electrically connected to the electrode A1 and the electrode A1 respectively. The conductive medium, the electrode B2, and the conductive medium electrically connected to the electrode B2 all keep a certain safe distance to avoid short-circuit connection between the electrode A1 and the electrode A2, and avoid short-circuit connection between the electrode B1 and the electrode B2. Thus, it can ensure that the conductive strip 1001 is fully connected to the electrodes, reduce the total area of the conductive strip 1001, reduce the thermal effect caused by the conductive strip 1001, reduce the usage of the conductive strip 1001, and increase the overall power of the cell assembly 100A.

In an optional embodiment of the present invention, the conductive strip 1001 includes two halves with the same structure and arranged in sequence perpendicular to the extending direction of the conductive strip 1001, and each half just covers the two electrodes. For example, in the examples shown in FIGS. 1 and 2 , the conductive strip 1001 extends horizontally and includes an upper half and a lower half arranged in sequence in the vertical direction, wherein the upper half just covers the electrode A2, that is, That is, the outer contour of the upper half coincides with the outer contour of the electrode A2, and the lower half just covers the electrode B1, that is, the outer contour of the lower half coincides with the outer contour of the electrode B1. Thus, it can ensure that the conductive strip 1001 is fully connected to the electrodes, reduce the total area of the conductive strip 1001, reduce the thermal effect caused by the conductive strip 1001, reduce the usage of the conductive strip 1001, and increase the overall power of the cell assembly 100A.

Preferably, in a direction perpendicular to the extending direction of the conductive strip 1001 , the gap between every two adjacent battery pieces 100 is less than or equal to 0.1 mm. That is to say, the gap between every two adjacent battery pieces 100 is 0 mm˜0.1 mm. For example, in the example shown in FIG. 1 and FIG. 2, the conductive strip 1001 extends in the horizontal direction, and the cell A and the cell B are arranged in sequence in the vertical direction. At this time, the lower edge of the cell A and the cell B The distance between the upper edges is the gap between cell A and cell B. Therefore, when the gap between two adjacent battery sheets 100 perpendicular to the extending direction of the conductive strip 1001 is limited to be less than or equal to 0.1 mm, the total area of the conductive strip 1001 can be further reduced, and the thermal effect caused by the conductive strip 1001 can be reduced. Reduce the use of conductive tape 1001, improve the overall power of the cell assembly 100A, in addition, when there is a certain small gap between the two cells 100, it can avoid the irregular shape of the cells 100 or the error caused by operation. The problem of stacking adjacent cells 100 .

In some embodiments of the present invention, the span of the silicon wafer 1 in the direction perpendicular to the side surface where the side conductive member 3 is located is 20mm-60mm. That is to say, the silicon wafer 1 includes a set (two) of opposite side surfaces, one of which is provided with a side conductive member 3 , and the distance between the sets of side surfaces is 20 mm to 60 mm. For example, in the example shown in Fig. 1 and Fig. 2, when the silicon chip 1 is a rectangular sheet, such as a rectangular sheet, and the side conductive member 3 is arranged on a long side surface of the silicon chip 1, the silicon chip 1 The width is 20mm ~ 60mm. For example, in another example of the present invention (the figure does not show this example), when the silicon chip 1 is a rectangular body and the side conductive member 3 is arranged on a wide side surface of the silicon chip 1, the silicon chip 1 The length is 20mm ~ 60mm.

In this way, the path of charge transmission from the light-receiving surface of the silicon wafer 1 to the backlight surface can be shortened, thereby increasing the charge transfer rate, and further increasing the power of the solar cell 100 . Here, it should be noted that "rectangular sheet" is understood in a broad sense, that is, it is not limited to a rectangular sheet in the strict sense, such as a substantially rectangular sheet, such as a rectangular sheet with rounded or chamfered corners. etc. also fall within the protection scope of the present invention. Thus, the processing of the battery sheet 100 is facilitated, and the connection between the battery and the battery sheet 100 is facilitated.

Preferably, the silicon wafer 1 is a rectangular wafer, and is formed by dividing a square conventional silicon wafer body according to the rule of constant length (only refers to "separation" rather than "cutting process"). That is to say, the silicon wafer body of square specification can be divided into a plurality of rectangular sheet-shaped silicon wafers 1 according to the constant length mode. At this time, the length of each silicon wafer 1 is equal to the length of the square specification silicon wafer body. , and the sum of the widths of the plurality of silicon wafers 1 is equal to the width of the square silicon wafer body.

The silicon chip 1 is a rectangular piece, and the two electrodes are respectively arranged adjacent to the two long sides of the silicon chip 1 to be spaced apart in the width direction of the silicon chip 1, and both extend along the length direction of the silicon chip 1, and the side conductive parts 3 is provided on one long side surface of the silicon wafer 1, that is, on one side surface of the silicon wafer 1 in the width direction. Therefore, the transmission path of the charge is shorter, the power of the battery sheet 100 is higher, and the processing of the battery sheet 100 is easier, and the connection between the battery sheets 100 is more convenient.

Preferably, both electrodes can be rectangular sheets and have a length equal to the length of the silicon wafer 1, so that the two broad sides and one long side of the two electrodes can be connected to the two wide sides and one long side of the silicon wafer 1 respectively. Alignment can make full use of the space, increase the power of the battery slice 100 , and facilitate the connection of the subsequent battery slice 100 and the battery slice 100 . In addition, the side conductive member 3 can also be configured in a sheet shape and occupy one side surface of the silicon wafer 1 in the width direction, so as to increase the power of the battery sheet 100 . Of course, the specific structures of the side conductors 3 and the electrodes are not limited thereto. For example, the side conductors 3 and the electrodes can also be discrete electrodes composed of a plurality of sub-electrodes distributed at intervals.

Referring to Embodiment 1-Embodiment 7 below, the two electrodes on each cell 100 are the first electrode 4 electrically connected to the side conductive member 3 and the second electrode 5 not electrically connected to the side conductive member 3, silicon Sheet 1 includes: a silicon substrate 11, a front first-type diffusion layer 12 and a back spacer 14, wherein the backlight surface of the silicon substrate 11 includes a first region and a second region, and the front first-type diffusion layer 12 is arranged on the silicon substrate. On the light-receiving surface of the substrate 11, the front conductive member is arranged on the front first-type diffusion layer 12, the back spacer 14 is only arranged on and covers the first area, and the first electrode 4 is arranged on the back side spacer 14. The second electrode 5 is disposed on the second region and does not contact the first electrode 4 , wherein at least part of the back spacer 14 is an insulating layer or the same type of diffusion layer as the front first type diffusion layer 12 . Therefore, the battery sheet 100 has a simple structure, and is convenient for processing and realization.

With reference to the following embodiments 1-embodiment 7, the silicon chip 1 also includes: a side spacer 13, the side spacer 13 is arranged on the side surface of the silicon substrate 11, and the side conductive member 3 is arranged on the side spacer 13, and the side spacer 13 is arranged on the side spacer 13. At least part of the layer 13 is an insulating layer or a diffusion layer of the same type as the front first type diffusion layer 12 . Referring to Embodiment 1 below, each battery sheet 100 also includes: a back electric layer 60, the back electric layer 60 is disposed on the second region, and the second electrode 5 is disposed on the back electric layer 60 and is electrically connected to the back electric layer 60 .

Referring to Embodiment 2-Embodiment 7 below, each solar cell 100 further includes: a second grid line layer 6 on the back side, and the second grid line layer 6 and the second electrode 5 on the back side are both arranged on the second region, and the second The electrodes 5 are electrically connected to the second gate line layer 6 on the back side and do not overlap with each other. Further, with reference to Embodiment 2-Embodiment 6 below, the silicon wafer 1 also includes a second-type diffusion layer 15 on the back that is different in type from the first-type diffusion layer 12 on the front, and the second-type diffusion layer 15 on the back is only arranged on and is covered with In the second area, the second grid line layer 6 and the second electrode 5 are both arranged on the second type diffusion layer 15 at the back.

Referring to Embodiment 5-Embodiment 7 below, each solar cell 100 also includes: the first grid line layer 7 on the back, the first grid line layer 7 and the first electrode 4 on the back are arranged on the spacer layer 14 on the back, and the second An electrode 4 is electrically connected to the first gate line layer 7 on the back side and does not overlap with each other. Further, with reference to the following examples 5-embodiment 7, the back spacer 14 is the same type of back first-type diffusion layer as the front first-type diffusion layer 12, and the back first-type diffusion layer is only arranged on and covered with the first-type diffusion layer. In one area, the back first grid line layer 7 and the first electrode 4 are both arranged on the back first type diffusion layer.

Referring to Embodiment 1 to Embodiment 7 below, both the first area and the second area are non-discrete areas. That is to say, when the first area is arbitrarily divided into multiple sub-areas, the multiple sub-areas can be connected to form a continuous first area. When any layer is only set and covered on the first area, the arbitrary layer is also a non-discrete layer, that is, a continuous layer; when the second area is arbitrarily divided into multiple sub-areas, the multiple sub-areas can be connected into one Contiguous second area. When any layer is provided only on and covers the second region, the arbitrary layer is also a non-discrete layer, that is, a continuous layer.

Referring to the following embodiment 1-embodiment 4, the first area and the second area are both rectangular areas to facilitate processing. Referring to Embodiment 5-Embodiment 7 below, the first area and the second area are distributed in an intersecting shape. At this time, the first area includes a first connected area and a plurality of first dispersed areas. A connecting area is spaced apart in the length direction and communicates with the first connecting area, the second area includes a second connecting area and a plurality of second dispersed areas, and the plurality of second dispersed areas are spaced apart in the length direction of the second communicating area open and all communicate with the second communication area, wherein the first communication area and the second communication area are arranged in parallel, and a plurality of first dispersed areas and a plurality of second dispersed areas are separated between the first communication area and the second communication area. One alternate.

Example 1,

5-9, the battery sheet 100 includes: a silicon wafer 1, a front conductive member, a side conductive member 3, a first electrode 4, a back electric layer 60 and a second electrode 5, wherein the front conductive member is a front grid line layer 2. The silicon wafer 1 may include a silicon substrate 11 , a front first type diffusion layer 12 , a side spacer 13 , and a back side spacer 14 .

The silicon substrate 11 is sheet-shaped, and the two surfaces in the thickness direction of the silicon substrate 11 are respectively a light-receiving surface and a backlight surface, and the light-receiving surface and the backlight surface are connected through side surfaces. Wherein, the front first-type diffusion layer 12 is arranged on the light-receiving surface of the silicon substrate 11, for example, in a preferred embodiment of the present invention, the front-side first-type diffusion layer 12 is covered with the light-receiving surface of the silicon substrate 11, Therefore, the processing difficulty of the front first type diffusion layer 12 is reduced, the processing efficiency is improved, and the processing cost is reduced.

The side spacer 13 is provided on the side surface of the silicon substrate 11 , for example, the side spacer 13 may be provided only on one side surface of the silicon substrate 11 , or may be provided on multiple side surfaces at the same time. Preferably, the side spacer 13 is only provided on one side surface of the silicon substrate 11 and covers the side surface. As a result, the processing and manufacture of the side partition 13 is facilitated.

The side conductors 3 are arranged on the side interlayer 13, that is to say, the side conductors 3 can be directly or indirectly arranged on the side interlayers 13. At this time, the side conductors 3 are arranged on the side surface of the silicon chip 1 and are connected to the side surface of the silicon wafer 1. The side spacer 13 is opposite, that is to say, projected along a direction perpendicular to the side surface where the side spacer 13 is located, the side conductive member 3 does not exceed the outline of the side spacer 13 .

Since the side conductive member 3 is provided on the side surface of the silicon wafer 1 instead of being embedded in the interior of the silicon wafer 1, the overall processing difficulty of the battery sheet 100 can be reduced, the processing process can be simplified, the processing efficiency can be improved, and the processing cost can be reduced. .

The backlight surface of the silicon substrate 11 includes a first area and a second area, and the first area and the second area have no intersection. Wherein, the first area and the second area may be in contact with each other or may not be in contact with each other, that is, the outline of the first area and the outline of the second area may or may not be in contact with each other. For example, when the part of the back spacer 14 that is in contact with the back electric layer 60 is an insulating layer, the first region and the second region can be in contact with each other, and when the part of the back spacer 14 that is in contact with the back electric layer 60 is When the diffusion layer is of the same type as the first type diffusion layer 12 on the front side, the first region and the second region may not be in contact with each other. Wherein, both the first area and the second area are non-discrete areas.

The back spacer 14 is only arranged on the first area, that is, the backlight surface of the silicon substrate 11 does not have a back spacer 14 on the remaining surface except the first area, and further, the back spacer 14 is covered with the first area. In one area, in this way, when the first area is a non-discrete continuous area, the back spacer 14 can be non-discrete, that is, continuously arranged on the silicon substrate 11 . Thus, since the back spacer 14 is continuously, that is, non-discretely arranged on the silicon substrate 11, rather than discretely, that is, discontinuously, for example, it is scattered on the silicon substrate in discrete forms such as scattered dots or zebra stripes. 11, thereby greatly reducing the processing difficulty of the back spacer 14, improving the processing efficiency, reducing the processing cost, and can effectively increase the power of the battery sheet 100.

The front grid line layer 2 is disposed on the front first type diffusion layer 12, that is to say, the front grid line layer 2 can be directly or indirectly disposed on the front first type diffusion layer 12, at this time, the front grid line layer 2 is disposed on the front first type diffusion layer 12. The light-receiving surface of the silicon wafer 1 is opposite to the front first-type diffusion layer 12 , in other words, projected along the thickness direction of the silicon wafer 1 , the front-side gate line layer 2 does not exceed the contour line of the front-side first-type diffusion layer 12 .

For example, in some embodiments of the present invention, the silicon wafer 1 may further include an anti-reflection layer 101 , and the anti-reflection layer 101 may be disposed on the front-side first-type diffusion layer 12 . In this way, when the silicon chip 1 includes the antireflection layer 101 , the front gate line layer 2 can be directly disposed on the antireflection layer 101 . And when the silicon wafer 1 does not include the antireflection layer 101 , the front gate line layer 2 can be directly disposed on the front first type diffusion layer 12 .

The first electrode 4 is arranged on the back interlayer 14, that is to say, the first electrode 4 can be directly or indirectly arranged on the back interlayer 14. At this time, the first electrode 4 is arranged on the backlight surface of the silicon chip 1 and is connected with The first area is opposite, in other words, projected along the thickness direction of the silicon wafer 1 , the first electrode 4 does not exceed the first area. For example, the first electrode 4 may be indirectly disposed on the back spacer 14 through the passivation layer 102 .

Both the back electric layer 60 and the second electrode 5 are arranged on the second region, that is to say, the back electric layer 60 and the second electrode 5 can be directly or indirectly arranged on the second region on the backlight surface of the silicon substrate 11, At this time, the back electric layer 60 and the second electrode 5 are arranged on the backlight surface of the silicon wafer 1 and are opposite to the second region, that is, projected along the thickness direction of the silicon wafer 1, the back electric layer 60 and the second electrode 5 Not beyond the second zone. For example, the back electric layer 60 and the second electrode 5 can be indirectly provided on the back light surface of the silicon substrate 11 through the passivation layer 102 . Wherein, the first electrode 4 is neither in contact with the back electric layer 60 nor in contact with the second electrode 5 .

In addition, it should be noted that, in some embodiments of the present invention, the back electric layer 60 and the second electrode 5 may not overlap each other and be in contact with each other. At this time, the back electric layer 60 and the second electrode 5 are completely arranged on The backlight surface of the silicon wafer 1 is in direct contact with the electrical connection, so that the space can be fully utilized and the power of the battery sheet 100 can be improved; in some other embodiments of the present invention, the back electric layer 60 and the second electrode 5 can also be stacked At this time, the backlight layer 60 and the second electrode 5 are arranged on the backlight surface of the silicon wafer 1 with their combined surface after the two are stacked.

Here, it should be noted that when the conductive medium (directly or indirectly through the antireflection layer 101, passivation layer 102) is arranged on the front first type diffusion layer 12, or (directly or through the antireflection layer 101, passivation layer 102 indirectly) on the same type of diffusion layer as the front first type diffusion layer 12 (such as the side first type diffusion layer and the back side first type diffusion layer 14 as described below), can collect one type of charge; and when A conductive medium (directly or indirectly through the passivation layer 102) is provided on the surface of the silicon substrate 11 that does not have the front first-type diffusion layer 12, or (directly or indirectly through the passivation layer 102) on the surface opposite to the front first-type diffusion layer 12. When one type of diffusion layer 12 with the opposite type of diffusion (such as the second type of diffusion layer 15 on the back side described below), charges of another type can be collected. Here, it should be noted that the principle of the conductive medium collecting charges on the silicon chip should be well known to those skilled in the art, and will not be described in detail here.

In addition, it should be noted that the entire light-receiving surface of the silicon wafer 1 in Examples 1-7 herein and the outermost surface of one side surface may all have an anti-reflection layer 101, and the silicon wafer 1 in Examples 2-7 herein 1 may also have a passivation layer 102 on the outermost surface of the entire backlight surface, so as to facilitate processing and manufacturing. In addition, it should be noted that the concepts of the anti-reflection layer 101 and the passivation layer 102 described herein should be well known to those skilled in the art, and they mainly function to reduce reflection and enhance charge collection. For example, the materials of the antireflection layer 101 and the passivation layer 102 may include but not limited to TiO ₂ , Al ₂ O ₃ , SiNxOy, SiNxCy.

For example, when the silicon substrate 11 is P-type silicon, the first type of diffusion layer 12 on the front side can be a phosphorus diffusion layer. At this time, the conductive medium disposed on the phosphorus diffusion layer can collect negative charges, and the conductive medium disposed on the non-phosphorus diffusion layer A conductive medium can collect positive charges. In this way, since the front grid line layer 2 is disposed on (for example, directly or indirectly through the antireflection layer 101) the front first type diffusion layer 12, the front grid line layer 2 can collect the first type of charge (eg negative charge). The back charge layer 60 is disposed on (for example, directly or indirectly through the passivation layer 102 ) the backlight surface of the silicon substrate 11 , so that the positive and back charge layer 60 can collect the second type of charges (for example, positive charges).

Specifically, the first electrode 4 is electrically connected to the front grid line layer 2 through the side conductive member 3, so that the first type of charges (such as negative charges) collected by the front grid line layer 2 can be transferred to the first electrode 4 (such as a negative electrode) The second electrode 5 is electrically connected to the back electric layer 60, so that the second type of charge (eg positive charge) collected by the back electric layer 60 can be transferred to the second electrode 5 (eg positive electrode). Thus, the first electrode 4 and the second electrode 5 can serve as positive and negative poles of the battery sheet 100 to output electric energy. In addition, since the side conductors 3 are arranged on the side of the silicon chip 1, the front grid line layer 2 and the first electrode 4 can be effectively and electrically connected together simply and conveniently through the side conductors 3, ensuring the reliable operation of the battery sheet 100. sex.

Those skilled in the art can understand that the first electrode 4 and the second electrode 5 need to be electrodes with opposite polarities, and they need to be insulated, that is, they are not conductive to each other, and do not form an electrical connection with each other. At this time, the first electrode 4 , and all components electrically connected to the first electrode 4 and the second electrode 5, and all components electrically connected to the second electrode 5 cannot be directly conducted, nor can they be indirectly conducted through any external conductive medium, for example, they may not be in contact with each other. Or separated by an insulating material, etc., so as to avoid short-circuit connection between the first electrode 4 and the second electrode 5 .

Wherein, the back spacer 14 is configured to prevent the first electrode 4 from being connected to the second electrode 5 through a short circuit through the silicon substrate 11, that is, avoiding the direct contact between the first electrode 4 and the silicon substrate 11 to cause a short circuit, for example, the back spacer 14 can be the same diffusion layer and/or insulating layer as the front diffusion layer, that is, the back spacer 14 can all be the same diffusion layer as the front diffusion layer, or all of them can be insulating layers, or a part can be the same as the front diffusion layer. The diffusion layer is the same as the layer type, and the rest is an insulating layer.

Thus, on the one hand, when the first electrode 4 is arranged on the silicon substrate 11 through the insulating layer, the first electrode 4 can be directly insulated from the silicon substrate 11, preventing the first electrode 4 from collecting and contacting the silicon substrate 11. The electric charge that the second electrode 5 collects is the same electric charge, thereby can avoid the problem that first electrode 4 is connected with second electrode 5 through silicon substrate 11 conduction short-circuit effectively, promptly avoids first electrode 4 and silicon substrate 11 direct contact. Contact causes a short circuit.

On the other hand, when the first electrode 4 is arranged on the silicon substrate 11 through the same diffusion layer as the front diffusion layer type, the first electrode 4 can be collected from the diffused silicon substrate 11 and the front gate line layer 2 The collected charges are of the same type, that is, opposite to the charges collected by the second electrode 5 , thereby avoiding short-circuit connection between the first electrode 4 and the second electrode 5 , and increasing the power of the battery sheet 100 .

Wherein, the side spacer 13 is configured to prevent the side conductor 3 from being short-circuited to the second electrode 5 through the silicon substrate 11, thereby avoiding the short-circuit connection between the first electrode 4 and the second electrode 5, that is, avoiding the side conductor 3 from being connected to the silicon substrate. 11 Direct contact causes a short circuit. For example, the side spacer 13 can be the same diffusion layer and/or insulating layer as the front diffusion layer, that is, the side spacer 13 can all be the same diffusion layer as the front diffusion layer, or all be insulating layers, or A part is a diffusion layer of the same type as the front diffusion layer, and the rest is an insulating layer.

Thus, on the one hand, when the side conductors 3 are arranged on the silicon substrate 11 through the insulating layer, the side conductors 3 can be directly insulated from the silicon substrate 11, so as to prevent the side conductors 3 from being collected and separated from the silicon substrate 11. The electric charge that the second electrode 5 collects is the same electric charge, thus can effectively avoid the problem that side conductive member 3 is connected with second electrode 5 conduction and short circuit by silicon substrate 11, promptly avoids side conductive member 3 and silicon substrate 11 directly. Contact causes a short circuit.

On the other hand, when the side conductive member 3 is arranged on the silicon substrate 11 through the same diffusion layer as the front diffusion layer type, the side conductive member 3 can be collected from the diffused silicon substrate 11 and the front grid line layer 2 The same charge of the collected charge type, that is, the opposite charge of the charge type collected by the second electrode 5, can also avoid the short circuit connection between the side conductive member 3 and the second electrode 5, that is, avoid the side conductive member 3 and the silicon substrate 11. The direct contact causes a short circuit and can increase the power of the cell 100 .

Specifically, in an embodiment of the present invention, at least part of at least one of the side spacer 13 and the back side spacer 14 is the same type of diffusion layer as the front first type diffusion layer 12, that is, either the side spacer 13 is at least partly the same type of diffusion layer as the front first type diffusion layer 12, or at least part of the back spacer 14 is the same type of diffusion layer as the front side first type diffusion layer 12, thereby not only ensuring that the first electrode 4 The insulation effect from the second electrode 5 can also increase the power of the battery sheet 100 .

Preferably, all the back spacers 14 are of the same type as the front first-type diffusion layer 12 , that is, the back spacer 14 is the back first diffusion layer covering the first region. Therefore, processing is facilitated and insulation reliability is good. Preferably, the side spacers 13 are all the same type of diffusion layer as the front first type diffusion layer 12 , that is, the side spacer 13 is a side diffusion layer covering the side surface of the silicon substrate 11 . Therefore, processing is facilitated and insulation reliability is good.

Here, it should be noted that concepts such as the silicon substrate 11, the diffusion layer, the anti-reflection layer 101, and the passivation layer 102, as well as the principle that the conductive medium collects charges from the silicon wafer 1 are well known to those skilled in the art, and will not be described here. More details.

In addition, in a preferred embodiment of the present invention, the front grid line layer 2, the back second grid line layer 6, and the back first grid line layer 7 described later can all be made of a plurality of conductive grid lines arranged at intervals. A conductive medium layer composed of thin grid lines, wherein the thin grid lines can be made of silver material, so that on the one hand, the conduction rate can be improved, and on the other hand, the light-shielding area can be reduced, thereby increasing the power of the battery sheet 100 in disguise. The back electric layer 60 can be an aluminum layer, that is, an aluminum back field, so that on the one hand, the conduction rate can be improved, and on the other hand, the cost can be reduced.

To sum up, according to the battery sheet 100 of the embodiment of the present invention, since at least one of the back spacer 14 and the side spacer 13 is at least partly the same type of diffusion layer as the first type of diffusion layer 12 on the front side, it can not only ensure the first type of diffusion layer The insulation between the first electrode 4 and the second electrode 5 can also effectively increase the power of the battery sheet 100 .

Moreover, by setting the side conductive member 3 on the side of the silicon substrate 11, the first electrode 4 on the light-receiving surface of the existing battery sheet 100 can be transferred from the light-receiving side of the silicon wafer 1 to the backlight side, so as to prevent the first electrode 4 from being opposite to the light-receiving side. The light-receiving side of the silicon wafer 1 is shielded from light, which improves the power of the battery sheet 100, and can ensure that the first electrode 4 and the second electrode 5 are all located on the same side of the silicon wafer 1, thereby facilitating the electrical connection between a plurality of battery sheets 100, reducing Soldering is difficult, reducing the amount of solder used, and at the same time reducing the damage probability of the battery sheet 100 during welding and subsequent lamination processes.

In addition, by arranging the side conductive member 3 on the side surface of the silicon wafer 1, the processing difficulty of the battery sheet 100 is greatly reduced (for example, there is no need to process holes on the silicon wafer 1 and inject conductive medium into the holes, etc. process), thereby increasing the processing rate, reducing the processing failure rate and processing cost. In addition, when the side conductive member 3 is arranged on one side surface in the width direction of the silicon substrate 11, the path for transferring charges from the light-receiving side of the silicon chip 1 to the backlight side can be effectively shortened, and the charge transfer rate can be improved. Therefore, the power of the battery sheet 100 is improved in a disguised form.

Preferably, when both the first area and the second area are non-discrete areas, have no intersection, and do not touch each other. Preferably, when the silicon wafer 1 is a rectangular wafer, the first area and the second area may both be rectangular areas and be spaced sequentially in the width direction of the silicon wafer 1 . The first electrode 4 and the back electric layer 60 with larger areas can be processed, preferably, projected along the thickness direction of the silicon wafer 1, the outer edge of the first electrode 4 falls on the contour line of the first region, and the back electric layer 60 is arranged Covering the second area, the second electrode 5 is disposed on the back electric layer 60 . Therefore, the first area and the second area can be utilized to the maximum extent, and the power of the battery sheet 100 can be increased. Here, it should be noted that, for surface-shaped components (such as the first electrode 4 and the second electrode 5 in the form of a rectangular sheet described herein), "outer edge" refers to its contour line, and for linear components ( For example, the fine grid lines described herein), the "outer edge" refers to its two ends.

In a preferred embodiment of the present invention, the front grid line layer 2 includes a plurality of front sub grid line layers 21 extending perpendicular to the length direction of the side conductive member 3, that is to say, each front sub grid line layer 21 is vertical in the length direction of the side conductor 3 . Thus, the charge transfer path of the front sub-grid layer 21 can be shortened, the charge transfer efficiency can be improved, and the power of the battery sheet 100 can be increased.

Next, the method for preparing the battery sheet 100 of the first embodiment will be briefly introduced.

Step a1, divide the square conventional silicon substrate body (for example, a conventional silicon substrate with a specification of 156mm*156mm) into 3-15 parts (preferably 5-10 parts) of rectangular sheet-like shape with constant length by laser The silicon substrate 11 (for example, the length is 156 mm), and then the subsequent battery sheet 100 manufacturing process is performed. Of course, the present invention is not limited thereto, and other ways or processes can also be used to obtain the silicon substrate 11 in the shape of a rectangular sheet. Here, it should be noted that the square conventional silicon substrate body is preferably evenly divided into three or more parts, so as to shorten the distance for the charge to migrate from the light-receiving surface to the backlight surface, to make the collection of charges efficient and easy, thereby increasing the power of the cell 100. , and, when the square conventional silicon substrate body is divided into fifteen parts or less, it is easy to cut and process, and the subsequent series-parallel battery slices 100 consume less solder, thereby improving the overall power of the battery slices 100 after series-parallel connection ,cut costs.

Step a2, cleaning and making texture: cleaning and removing the dirt on each surface of the silicon substrate 11, and making texture to reduce the reflectivity of each surface of the silicon substrate 11;

Step a3, Diffusion junction: Diffusion is performed on both sides of the silicon substrate 11 through a diffusion furnace to prepare a P-N junction, so that each surface of the silicon substrate 11 has the same type of diffusion layer;

Step a4, mask protection: protect the diffusion layer on the first region (that is, serve as the back diffusion layer 14 ) and the diffusion layer on the side surface adjacent to the first region (that is, serve as the side diffusion layer 13 ) with paraffin.

Step a5, etching: removing the back junction not protected by paraffin wax on the side surface of the silicon substrate 11 and the backlight surface;

Step a6, removing the paraffin protection and removing the phosphosilicate glass, thereby obtaining the back diffusion layer 14 and the side diffusion layer 13 under the protection of paraffin;

Step a7, evaporating the anti-reflection layer 101 on the front diffusion layer 12, the material of the anti-reflection layer 101 includes but not limited to TiO2, Al2O3, SiNxOy, SiNxCy;

Step a8: screen-print the back electric layer 60 along the length direction on the second area, screen-print the second electrode 5 on the back electric layer 60 along the length direction, and screen-print the first electrode on the back diffusion layer 14 along the length direction 4. Drying, wherein the first electrode 4 coincides with the back diffusion layer 14, and there is a certain safety distance between the back electric layer 60 and the first electrode 4, and no short circuit is connected;

Step a9, screen printing the grid line layer 2 along the width direction on the front diffusion layer 12 so that each sub-grid line 21 in the grid line layer 2 is perpendicular to the second electrode 5, and drying;

Step a10, screen-print the side conductive element 3 on the side diffusion layer 13 along the length direction, and dry it.

Example 2,

Referring to Fig. 10-Fig. 14, the structure of this embodiment 2 is substantially the same as that of the embodiment 1, wherein the same components use the same reference numerals, the only difference is that the second area in the embodiment 1 is provided with a back electric layer 60, the second electrode 5 is arranged on the back electric layer 60, and the second type diffusion layer 15 on the back is arranged on the second area in this embodiment 2, and the second gate line on the back is arranged on the second type diffusion layer 15 on the back layer 6 and the second electrode 5.

The battery sheet 100 includes: a silicon wafer 1, a front conductive part, a side conductive part 3, a first electrode 4, a second grid line layer 6 and a second electrode 5 on the back side, wherein the front conductive part is the front grid line layer 2, and the silicon chip 1 may include a silicon substrate 11, a front first-type diffusion layer 12, a back-side second-type diffusion layer 15, a side spacer 13, and a back side spacer 14, wherein the side spacer 13 may be the same as the front-side first-type diffusion layer 12 is the same type of side diffusion layer, and the back spacer 14 can be the same type of back first type diffusion layer 12 as the front side first type diffusion layer. Wherein, the second-type diffusion layer 15 on the back side includes a plurality of second sub-gate line layers 61 extending perpendicular to the length direction of the second electrode 5, that is to say, each second sub-gate line layer 61 on the back side is perpendicular to the second electrode 5. The length direction of the two electrodes 5 . Thus, the charge transfer path of the second sub-gate line layer 61 on the back side can be shortened, the charge transfer efficiency can be improved, and the power of the battery sheet 100 can be increased.

Specifically, the backlight surface of the silicon substrate 11 includes a first area and a second area, and the first area and the second area have no intersection and no contact with each other, that is to say, the outline of the first area and the outline of the second area not in contact.

The first-type diffusion layer on the back is only arranged on the first region, that is, the other surfaces on the backlight surface of the silicon substrate 11 except the first region do not have the first-type diffusion layer on the back, further, the first-type diffusion layer on the back The diffusion layer is all over the first area, so when the first area is a non-discrete continuous area, the first type of diffusion layer on the back can be non-discrete, that is, continuously arranged on the silicon substrate 11 . Thus, since the first type of diffusion layer on the back is arranged continuously, that is, non-discretely, on the silicon substrate 11, instead of discretely, that is, discontinuously, for example, it is scattered on the silicon substrate in discrete forms such as scattered spots or zebra stripes. The substrate 11 greatly reduces the difficulty of processing the first type of diffusion layer on the back, improves the processing efficiency, reduces the processing cost, and can effectively increase the power of the battery sheet 100 .

The second-type diffusion layer 15 on the back is only provided on the second region, that is, there is no second-type diffusion layer 15 on the backlight surface of the silicon substrate 11 except the second region. Further, the second-type diffusion layer 15 on the back is covered with the second region, so that when the second region is a non-discrete continuous region, the second-type diffusion layer 15 on the back can be arranged non-discretely, that is, continuously on the silicon substrate. Sheet 11 on. Thus, since the second-type diffusion layer 15 on the back side is arranged continuously, that is, non-discretely, on the silicon substrate 11, rather than discretely, that is, discontinuously, for example, it is scattered in discrete forms such as scattered dots or zebra stripes. Silicon substrate 11 , thereby greatly reducing the processing difficulty of the second-type diffusion layer 15 on the back, improving processing efficiency, reducing processing cost, and effectively increasing the power of the cell 100 .

The first electrode 4 is arranged on the backside first type diffusion layer, that is to say, the first electrode 4 can be arranged directly or indirectly on the backside first type diffusion layer, at this time, the first electrode 4 is arranged on the backlight of the silicon wafer 1 On the surface and opposite to the first region, that is, projected along the thickness direction of the silicon wafer 1 , the first electrode 4 does not exceed the first region. For example, in some embodiments of the present invention, the silicon wafer 1 may further include a passivation layer 102, and the passivation layer 102 may be disposed on the first-type diffusion layer on the back side. In this way, when the silicon wafer 1 includes the passivation layer 102 , the first electrode 4 can be directly disposed on the passivation layer 102 . And when the silicon wafer 1 does not include the passivation layer 102, the first electrode 4 can be directly disposed on the first type diffusion layer on the back side.

The second type diffusion layer 15 and the second electrode 5 on the back side are all arranged on the second type diffusion layer 15 on the back side, that is to say, the second type diffusion layer 15 and the second electrode 5 on the back side can be directly or indirectly arranged on the second type diffusion layer 15 on the back side. On the diffusion layer 15, at this moment, the backside second type diffusion layer 15 and the second electrode 5 are arranged on the backlight surface of the silicon wafer 1 and are opposite to the second area, that is to say, projected along the thickness direction of the silicon wafer 1, the backside The second type diffusion layer 15 and the second electrode 5 do not protrude beyond the second area. Wherein, the first electrode 4 is not in contact with the second-type diffusion layer 15 on the back surface, nor is it in contact with the second electrode 5 .

For example, in some embodiments of the present invention, the silicon wafer 1 may further include a passivation layer 102 , and the passivation layer 102 may be disposed on the second-type diffusion layer 15 at the back. In this way, when the silicon wafer 1 includes the passivation layer 102 , the second-type diffusion layer 15 and the second electrode 5 on the back side can be directly disposed on the passivation layer 102 . However, when the silicon wafer 1 does not include the passivation layer 102 , the back second type diffusion layer 15 and the second electrode 5 can be directly disposed on the back side second type diffusion layer 15 .

In addition, it should be noted that, in some embodiments of the present invention, the second-type diffusion layer 15 on the back side and the second electrode 5 may not overlap each other and be in contact with each other. At this time, the second-type diffusion layer 15 on the back side and the second The electrodes 5 are respectively completely arranged on the backlight surface of the silicon chip 1 and the edges are directly in contact with the electrical connection, so that the space can be fully utilized and the power of the cell 100 can be improved; in some other embodiments of the present invention, the second type of diffusion layer on the back is 15 and the second electrode 5 can also be stacked on each other. At this time, the back surface of the second type of diffusion layer 15 and the second electrode 5 is set on the backlight surface of the silicon wafer 1 with the combined surface after the two are stacked.

Wherein, since the first region and the second region have no intersection and do not contact each other, the first electrode 4 with a larger area can be processed, and the second type diffusion layer 15 and the second electrode 5 with a larger area can be processed, preferably Specifically, projected along the thickness direction of the silicon wafer 1, the outer edge of the first electrode 4 falls on the contour line of the first region, and the outer edges of the second type diffusion layer 15 and the second electrode 5 on the back all fall on the second region. on the contour line. Thus, the first area and the second area can be utilized to the maximum extent, and the power of the battery sheet 100 can be increased.

Here, it should be noted that the "first type of diffusion layer" and "second type of diffusion layer" described herein are two different types of diffusion layers. When the anti-reflection layer 101 or the passivation layer 102 is indirectly disposed on the first-type diffusion layer and the second-type diffusion layer, different types of charges can be collected. In addition, it should be noted that the concepts of the anti-reflection layer 101 and the passivation layer 102 described herein are well known to those skilled in the art, and they mainly function to reduce reflection and enhance charge collection.

Thus, the front first-type diffusion layer 12, the back-side first-type diffusion layer, and the side first-type diffusion layer described herein in the "first-type diffusion layer" are the same type of diffusion layer. When on the first type of diffusion layer, the charges of the first type can be collected; and the backside second type of diffusion layer 15 in the "second type of diffusion layer" is another type of diffusion layer, when the conductive medium is arranged on the second type of diffusion layer When on the diffusion layer of the second type, the charge of the second type can be collected. Here, it should be noted that the principle of the conductive medium collecting charges on the silicon wafer 1 should be well known to those skilled in the art, and will not be described in detail here.

For example, when the silicon substrate 11 is P-type silicon, the first type of diffusion layer can be a phosphorus diffusion layer. At this time, the conductive medium arranged on the phosphorus diffusion layer can collect negative charges, and the second type of diffusion layer can be a boron diffusion layer. layer, a conductive medium disposed on the boron diffusion layer can collect positive charges. For another example, when the silicon substrate 11 is N-type silicon, the "first type diffusion layer" can be a boron diffusion layer, and the "second type diffusion layer" can be a phosphorus diffusion layer, which will not be repeated here.

In this way, since the front grid line layer 2 is disposed (for example, directly on or indirectly through the antireflection layer 101) on the first type of diffusion layer, the front grid line layer 2 can collect the first type of charges (such as negative charges). . And the second-type diffusion layer 15 on the back side is arranged on (for example, directly arranged on or indirectly arranged on through the passivation layer 102) on the second-type diffusion layer, so that the front and back side second-type diffusion layer 15 can collect the second type of charges (for example, positive charge).

Specifically, the first electrode 4 is electrically connected to the front grid line layer 2 through the side conductive member 3, so that the first type of charges (such as negative charges) collected by the front grid line layer 2 can be transferred to the first electrode 4 (such as a negative electrode) The second electrode 5 is electrically connected to the second type of diffusion layer 15 on the back side, so that the second type of charge (eg positive charge) collected by the second type diffusion layer 15 on the back side can be transferred to the second electrode 5 (eg positive electrode). Thus, the first electrode 4 and the second electrode 5 can serve as positive and negative poles of the battery sheet 100 to output electric energy.

Like this, because the first electrode 4 can collect the first kind of charges through the front grid line layer 2 positioned at the light-receiving side of the silicon wafer 1, the second electrode 5 can collect the second type of charge through the backside second diffusion layer 15 on the backlight side of the silicon wafer 1. different types of charges, thereby effectively improving the space utilization rate and further increasing the power of the battery sheet 100, so that the battery sheet 100 can become a beautiful and efficient double-sided battery.

Specifically, the preparation method of the battery sheet 100 in this embodiment 2 is substantially the same as the preparation method of the battery sheet 1 in the embodiment 1, the difference is that when preparing the silicon wafer 1 in the embodiment 2, the The silicon substrate 11 carries out double-sided diffusion of different types, that is, the light-receiving surface and the backlight surface of the silicon substrate 11 are respectively diffused with different types of diffusion layers, and the diffusion layer on the light-receiving surface is extended from one side surface of the silicon substrate 11 to the backlight surface of the silicon substrate 11 to obtain the first type diffusion layer 12 on the front side, the first type diffusion layer 13 on the side and the first type diffusion layer 14 on the back side, and then the first type diffusion layer 14 on the back side and the second type diffusion layer on the back side A passivation layer 102 of the same material as the anti-reflection layer 101 is vapor-deposited on the diffusion-like layer 15 and the silicon substrate 11 , and then the second grid line layer 6 on the back is screen-printed on the passivation layer 102 .

Example 3,

Referring to Fig. 15-Fig. 19, the structure of this embodiment 3 is substantially the same as that of embodiment 2, wherein the same components use the same reference numerals, the only difference is that the first region and the second region in embodiment 2 have no Intersect and do not touch each other, while the first area and the second area have no intersection and contact each other in Embodiment 3, that is, the outline of the first area is in contact with the outline of the second area.

Specifically, the first region and the second region have no intersection and are in contact with each other, and the first electrode 4 is arranged on the first region, that is to say, the first electrode 4 can be directly or indirectly arranged on the first region, at this time, the second An electrode 4 is provided on the backlight surface of the silicon wafer 1 and is opposite to the first area, that is, projected along the thickness direction of the silicon wafer 1 , the first electrode 4 does not exceed the first area and is located outside the second area. Both the back gate line layer and the second electrode 5 are arranged on the second region and are not in contact with the first electrode 4, that is to say, the back gate line layer and the second electrode 5 can be directly or indirectly arranged on the second region, And the back gate line layer is not in contact with the first electrode 4, and the second electrode 5 is not in contact with the first electrode 4. At this time, the back gate line layer and the second electrode 5 are arranged on the backlight surface of the silicon chip 1 and are in contact with the first electrode 4. The two regions face each other, that is to say, projected along the thickness direction of the silicon wafer 1 , the back grid line layer and the second electrode 5 do not exceed the second region and are located outside the first region. Thus, contact short circuit between the first electrode 4 and the second electrode 5 can be effectively avoided.

Example 4,

Referring to Fig. 20-Fig. 24, the structure of this embodiment 4 is substantially the same as that of embodiment 3, wherein the same components use the same reference numerals, the only difference is that the side spacer 13 in embodiment 3 is the first on the side. The diffusion-like layer and the back spacer 14 are the first type of diffusion layer on the back, while the side spacer 13 and the back spacer 14 in Embodiment 4 are both insulating layers.

Specifically, the method for preparing the cell 100 in Example 4 is substantially the same as the method for preparing the cell 1 in Example 2, except that when preparing the silicon chip 1 in Example 4, the The silicon substrate 11 carries out double-sided different types of diffusion, that is, the light-receiving surface and the backlight surface of the silicon substrate 11 are respectively diffused with different types of diffusion layers, so as to obtain the first-type diffusion layer 12 on the front side and the second-type diffusion layer 15 on the back side. And process an insulating layer on one side of the backlight surface of the silicon substrate 11 and on the side surface adjacent to the rear surface, so as to obtain the back spacer 14 and the side spacer 13 .

Example 5,

Referring to Fig. 25-Fig. 31, the structure of this embodiment 5 is substantially the same as that of embodiment 3, wherein the same components use the same reference numerals, the only difference is: first, the first type of diffusion on the back side in embodiment 3 Only the first electrode 4 is provided on the layer (i.e., the back spacer 14), while the first type of diffusion layer on the back side (ie, the back spacer 14) in Embodiment 5 is also provided with a back side electrically connected to the first electrode 4. The first grid line layer 7 . Second, in Embodiment 5, the first area and the second area are distributed in a contact-type interdigitated manner.

The first grid line layer 7 and the first electrode 4 on the back side are arranged on the first type diffusion layer on the back side, that is to say, the first grid line layer and the first electrode 4 on the back side can be directly or indirectly arranged on the first type diffusion layer on the back side , at this time, the back first grid line layer 7 and the first electrode 4 are arranged on the backlight surface of the silicon wafer 1 and are opposite to the first region, that is to say, projected along the thickness direction of the silicon wafer 1, the back first grid line Layer 7 and first electrode 4 do not protrude beyond the first area and are located outside the second area.

For example, in some embodiments of the present invention, the silicon wafer 1 may further include a passivation layer 102, and the passivation layer 102 may be disposed on the first-type diffusion layer on the back side. In this way, when the silicon wafer 1 includes the passivation layer 102 , the first gate line layer 7 and the first electrode 4 on the back side can be directly disposed on the passivation layer 102 . And when the silicon wafer 1 does not include the passivation layer 102, the first gate line layer 7 and the first electrode 4 on the back side can be directly disposed on the first type diffusion layer on the back side.

In addition, it should be noted that, in some embodiments of the present invention, the first gate line layer 7 on the back side and the first electrode 4 may not overlap each other and be in contact with each other. At this time, the first gate line layer 7 on the back side and the first The electrodes 4 are respectively completely arranged on the backlight surface of the silicon chip 1 and the edges are in direct contact with the electrical connection, so that the space can be fully utilized and the power of the battery sheet 100 can be improved; in some other embodiments of the present invention, the first grid line layer on the back 7 and the first electrode 4 can also overlap each other. At this time, the combined surface of the first grid line layer 7 and the first electrode 4 on the back is set on the backlight surface of the silicon wafer 1 after the two are overlapped.

Thus, according to the cell sheet 100 of this embodiment, the front gate line layer 2 and the back first gate line layer 7 connected to the first electrode 4 are respectively processed on the light-receiving surface and the backlight surface of the silicon wafer 1, and the The backside of the sheet 1 is processed with the second grid line layer 6 connected to the second electrode 5, so that the battery sheet 100 can be a double-sided battery with higher power.

In one embodiment of the present invention, the first area and the second area are distributed in a finger-contact cross shape, that is, the contour line of the first area is in contact with the contour line of the second area, for example, the first area and the second area The two regions can be inserted seamlessly to form a continuous, complete and non-discrete region without holes. For example, preferably, the first region and the second region may cover the backlight surface of the silicon substrate 11 . Thus, the space can be fully utilized and the power of the battery sheet 100 can be increased. Here, it should be noted that the "cross-fingered shape" refers to a shape similar to that of the fingers of the left and right hands intersecting each other without overlapping.

Specifically, the first area includes a first connected area and a plurality of first dispersed areas, and the plurality of first dispersed areas are spaced apart in the length direction of the first connected area and all communicate with the first connected area, and the second area includes the first distributed area. Two communication areas and a plurality of second dispersion areas, the plurality of second dispersion areas are spaced apart in the length direction of the second communication area and all communicate with the second communication area.

Wherein, the number of the first distributed area and the second distributed area is not limited, and the shape of the first connected area, the first distributed area, the second connected area, and the second distributed area is not limited, for example, the first distributed area and the second distributed area Each of the dispersion areas can be formed in a triangle, semicircle, rectangle, etc., and the first dispersion area and the second dispersion area can be formed in a rectangle, a wave shape, etc.

Wherein, the first connected area is arranged opposite to the second connected area, for example, the first connected area and the second connected area are arranged parallel or substantially parallel (with a small included angle), and the plurality of first dispersed areas and the plurality of second dispersed areas The areas alternate between the first connected area and the second connected area one by one, that is to say, along the length direction of the first connected area, that is, along the length direction of the second connected area, a first dispersed area, a second connected area are arranged in sequence. Two dispersive areas, another first dispersive area, another second dispersive area, and so on, a plurality of first dispersive areas and a plurality of second dispersive areas are distributed alternately and alternately.

Wherein, the outline of the first connected area is in contact with the outline of the second connected area and the outline of the second dispersed area respectively, and the outline of the second connected area is in contact with the outline of the first connected area and the outline of the first dispersed area. The lines touch separately. Thus, it can be ensured that the first area and the second area are arranged in a contact interdigitated manner.

Further, the first electrode 4 is arranged on the first connection area, and the first grid line layer 7 on the back is arranged on the plurality of first scattered areas. In other words, the first electrode 4 is arranged opposite to the first connection region, and the first gate line layer 7 on the back is arranged opposite to the plurality of first dispersed regions. That is to say, projected along the thickness direction of the silicon wafer 1, the first electrode 4 does not exceed the outline of the first connected area, and the first gate line layer 7 on the back does not exceed the outline of multiple first dispersed areas and is located in the second area. outside the contour line. Therefore, the layout of the first electrode 4 and the first grid line layer 7 on the back side is reasonable and simple, which is convenient for processing on the first type diffusion layer on the back side.

Preferably, the back first gate line layer 7 includes a plurality of back first sub-gate line layers 71 extending perpendicular to the length direction of the first communication region and spaced apart in the length direction of the first communication region. As a result, the first grid line layer 7 on the back side can transfer the collected charges to the first electrode 4 in a shorter path, thereby improving the charge transfer efficiency and increasing the power of the battery sheet 100 .

Further, the second electrode 5 is arranged on the second connection area, and the second grid line layer 6 on the back is arranged on multiple second scattered areas. In other words, the second electrode 5 is arranged opposite to the second connection region, and the second gate line layer 6 on the back is arranged opposite to the plurality of second dispersed regions. That is to say, projected along the thickness direction of the silicon wafer 1, the second electrode 5 does not exceed the contour line of the second connected region, and the second grid line layer 6 on the back does not exceed the contour line of multiple second dispersed regions and is located in the first region. outside the contour line. Therefore, the layout of the second electrode 5 and the second grid line layer 6 on the back is reasonable and simple, which is convenient for processing on the second type diffusion layer 15 on the back.

Preferably, the back second gate line layer 6 includes a plurality of back second sub-gate line layers 61 extending perpendicular to the length direction of the second connection region and spaced apart in the length direction of the second connection region. As a result, the second grid line layer 6 on the back side can transfer the collected charges to the second electrode 5 in a shorter path, thereby improving the charge transfer efficiency and increasing the power of the battery sheet 100 .

Wherein, the outline of each back first sub-gate line layer 71 is not in contact with the second connected area and the second scattered area, that is to say, each back side first sub-gate line layer 71 is not in contact with the back side second sub-gate line layer. Neither layer 61 nor second electrode 5 are in contact. Wherein, the outline of each rear second sub-gate line layer 61 is not in contact with the first connected region and the first scattered region, that is to say, each rear second sub-gate line layer 61 is not in contact with the rear first sub-gate line layer 61. Neither layer 71 nor first electrode 4 are in contact.

Specifically, the preparation method of the battery sheet 100 in Example 5 is substantially the same as that of the battery sheet 1 in Example 2, the difference is that after the silicon wafer 1 is prepared, the second type of On the diffusion layer 15, the second sub-gate line layer 61 on the back side is processed.

Example 6,

Referring to Fig. 32-Fig. 38, the structure of this embodiment 6 is substantially the same as that of embodiment 5, wherein the same components use the same reference numerals, the only difference is that the first region and the second region in embodiment 5 form The contact interdigitated distribution, while the first area and the second area in the embodiment 6 are non-contact interdigitated distribution.

The outline of the first connected area does not touch the outline of the second connected area and the outline of the second dispersed area, and the outline of the second connected area does not touch the outline of the first connected area and the outline of the first dispersed area. No contact. Thus, it can be ensured that the first area and the second area are non-contact interdigitated. Wherein, the outline of each back first sub-gate line layer 71 is not in contact with the second connected area and the second scattered area, that is to say, each back side first sub-gate line layer 71 is not in contact with the back side second sub-gate line layer. Neither layer 61 nor second electrode 5 are in contact. Wherein, the outline of each rear second sub-gate line layer 61 is not in contact with the first connected region and the first scattered region, that is to say, each rear second sub-gate line layer 61 is not in contact with the rear first sub-gate line layer 61. Neither layer 71 nor first electrode 4 are in contact.

Example 7,

Referring to Fig. 39-Fig. 45, the structure of this embodiment 7 is substantially the same as that of embodiment 5, wherein the same components use the same reference numerals, the difference is only that: the second area in embodiment 5 is covered with the second area on the back. The second type of diffusion layer 15, while the second area in the seventh embodiment is not provided with the second type of diffusion layer.

The second electrode 5 and the second gate line layer 6 on the back side may be directly or indirectly provided on the second region. For example, in an optional example of the present invention, the second region may be covered with a passivation layer 102 , and the second gate line layer 6 and the second electrode 5 on the back side may be directly disposed on the passivation layer 102 . And when the silicon wafer 1 does not include the passivation layer 102, the second gate line layer 6 and the second electrode 5 on the back side can be directly disposed on the second region.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear" etc. is based on the orientation or positional relationship shown in the drawings, and is only for It is convenient to describe the present invention and simplify the description, but does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and thus should not be construed as limiting the present invention.

In the present invention, terms such as "installation", "connection", "connection" and "fixation" should be interpreted in a broad sense unless otherwise clearly specified and limited, for example, they may be directly connected or indirectly through an intermediary To be connected can be the internal communication of two elements or the interaction relationship between two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations. In the present invention, unless otherwise clearly specified and limited, the first feature may be in direct contact with the first feature or the first and second feature may be in direct contact with the second feature through an intermediary. touch.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the invention is defined by the claims and their equivalents.

Claims (20)

1. A kind of 1. cell piece component, it is characterised in that including：

   The multiple cell pieces arranged successively along longitudinal direction, each cell piece include silicon chip, are located on the silicon chip smooth surface Front side conductive part, two electrodes being located on the silicon chip shady face and be located on the silicon chip side surface and electrically connect Lateral conduction part between the front side conductive part and an electrode, wherein, two electrodes extend transversely And distribution is spaced apart on the longitudinal direction；

   Conductive strips, the conductive strips it is identical with the bearing of trend of the electrode and with it is close to each other and respectively positioned at two neighboring Two electrodes on the cell piece electrically connect two cell piece serial or parallel connections so that adjacent.
2. 2. cell piece component according to claim 1, it is characterised in that on the bearing of trend of the conductive strips, institute The development length for stating conductive strips is more than or equal to the development length of each electrode turned on by the conductive strips, and the conduction The both ends of band exceed or flushed in respectively the respective end of each electrode turned on by the conductive strips.
3. 3. cell piece component according to claim 1, it is characterised in that perpendicular to the conductive strips bearing of trend On direction, the span of the conductive strips is more than or equal to the span sum of two electrodes turned on by the conductive strips, and institute Two sides for stating conductive strips exceed or flushed in respectively the both sides of two electrodes turned on by the conductive strips away from each other Side.
4. 4. cell piece component according to claim 1, it is characterised in that the conductive strips are identical including structure and hanging down Directly it is covered each by just by the conduction in the two half-unit being sequentially arranged on the conductive strips bearing of trend, each half portion Two electrodes with conducting.
5. 5. cell piece component according to claim 1, it is characterised in that perpendicular to the conductive strips bearing of trend On direction, the gap between every two adjacent cell pieces is less than or equal to 0.1mm.
6. 6. cell piece component according to claim 1, it is characterised in that the silicon chip is perpendicular to the lateral conduction Span where part in side face directions is 20mm-60mm.
7. 7. cell piece component according to claim 6, it is characterised in that the silicon chip is for rectangle lamellar body and by pros Shape conventional silicon wafers body is split to form according to the constant rule of length.
8. 8. cell piece component according to claim 6, it is characterised in that the silicon chip is rectangle lamellar body, two institutes State electrode recline respectively the silicon chip two long sides set and along the silicon chip length direction extend, the lateral conduction Part is located on a long side side surface of the silicon chip.
9. 9. cell piece component according to claim 1, it is characterised in that two electricity on each cell piece Pole is respectively the first electrode and the non-second electrode electrically connected with the lateral conduction part electrically connected with the lateral conduction part,

   The silicon chip includes：Silicon chip, positive first kind diffusion layer and back side interlayer, wherein, the backlight of the silicon chip Face includes first area and second area, and the positive first kind diffusion layer is located on the smooth surface of the silicon chip, it is described just Face electric-conductor is located on the positive first kind diffusion layer, and the back side interlayer is only defined and is covered with the first area, The first electrode is located on the back side interlayer, the second electrode be located on the second area and with the first electrode Do not contact, wherein, at least partially insulating barrier of the back side interlayer or with the positive first kind diffusion channel type identical Diffusion layer.
10. 10. cell piece component according to claim 9, it is characterised in that the silicon chip also includes：Side interlayer, The side interlayer is located on the side surface of the silicon chip, and the lateral conduction part is located on the side interlayer, the side At least partially insulating barrier of face interlayer spreads channel type identical diffusion layer with the positive first kind.
11. 11. cell piece component according to claim 9, it is characterised in that each cell piece also includes：

    Carry on the back electric layer, it is described the back of the body electric layer be located on the second area, the second electrode be located at it is described the back of the body electric layer on and with it is described Carry on the back electric layer electrical connection.
12. 12. cell piece component according to claim 9, it is characterised in that each cell piece also includes：

    The grid line layer of the back side second, the grid line layer of the back side second and the second electrode are each provided on the second area, and institute Second electrode is stated to electrically connect with the grid line layer of the back side second and be not stacked mutually.
13. 13. cell piece component according to claim 12, it is characterised in that the silicon chip also includes and described positive the A kind of different types of the second class of back side diffusion layer of diffusion layer, the second class of back side diffusion layer are only defined and are covered with described On two regions, the grid line layer of the back side second and the second electrode are each provided on the second class of back side diffusion layer.
14. 14. cell piece component according to claim 9, it is characterised in that each cell piece also includes：

    The grid line layer of the back side first, the grid line layer of the back side first and the first electrode are each provided on the back side interlayer, and institute First electrode is stated to electrically connect with the grid line layer of the back side first and be not stacked mutually.
15. 15. cell piece component according to claim 14, it is characterised in that the back side interlayer is and described positive the One kind diffusion channel type identical back side first kind diffusion layer, the back side first kind diffusion layer are only defined and are covered with described the On one region, the grid line layer of the back side first and the first electrode are each provided on the back side first kind diffusion layer.
16. 16. cell piece component according to claim 9, it is characterised in that the first area and the second area It is non-discrete region.
17. 17. cell piece component according to claim 16, it is characterised in that the first area and the second area It is distributed in X-shape is referred to, wherein, the first area includes the first connected region and multiple first discrete areas, multiple described First discrete areas is spaced apart on the length direction of first connected region and connected with first connected region, institute Stating second area includes the second connected region and multiple second discrete areas, and multiple second discrete areas connect described second It is spaced apart on the length direction in logical region and is connected with second connected region, wherein, first connected region and institute State the second connected region to be arranged in parallel, multiple first discrete areas and multiple second discrete areas connect described first It is logical to replace one by one between region and second connected region.
18. A kind of 18. cell piece matrix, it is characterised in that

    It is in series by multiple cell piece parallel components,

    Wherein, each cell piece parallel component is formed in parallel by multiple cell piece series components,

    Wherein, each cell piece series component is the cell piece component according to any one of claim 1-17, often Multiple cell pieces in the individual cell piece component are sequentially connected in series by the conductive strips.
19. 19. cell piece matrix according to claim 18, it is characterised in that the cell piece parallel component is two, Each cell piece parallel component includes three cell piece series components.
20. A kind of 20. solar cell module, it is characterised in that including：The first face set gradually from sensitive side to backlight side Plate, the first tack coat, battery, the second tack coat and second panel, wherein, the battery is according to claim 1-17 Any one of cell piece component or the cell piece matrix according to any one of claim 18-19.