CN107562648B

CN107562648B - Lock-free FTL (fiber to the Home) access method and device

Info

Publication number: CN107562648B
Application number: CN201610512869.3A
Authority: CN
Inventors: 袁戎
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Shanghai Manbu Information Technology Co ltd; Beijing Memblaze Technology Co Ltd
Priority date: 2016-07-01
Filing date: 2016-07-01
Publication date: 2021-04-06
Anticipated expiration: 2036-07-01
Also published as: CN107562648A

Abstract

An IO command processing method and apparatus are provided. A method of processing IO requests, comprising: responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; in response to receiving the read request, accessing a first FTL table entry corresponding to the read request, and reading data from a physical address of the first table entry even if the first FTL table entry is locked; and allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

Description

Lock-free FTL (fiber to the Home) access method and device

Technical Field

The present invention relates to a solid state storage device, and more particularly, to processing a lock on an FTL (Flash Translation Layer) when the solid state storage device processes an IO request.

Background

Referring to FIG. 1, a block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host and the storage device 102 by, for example, SATA, IDE, USB, PCIE, NVMe (NVM Express), SAS, ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The storage device 102 includes an interface 103, a control unit 104, one or more NVM (Non-Volatile Memory) chips 105 and optionally a firmware Memory 110. The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc. The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the firmware memory 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in a variety of ways including software, hardware, firmware, or a combination thereof. The control unit 104 may be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller. Control unit 104 loads firmware from firmware memory 110 at runtime. Firmware memory 110 may be NOR flash, ROM, EEPROM, or may be part of NVM chip 105.

In the solid-state storage device, mapping information from logical addresses to physical addresses is maintained using FTL (Flash Translation Layer). The logical addresses constitute the storage space of the solid-state storage device as perceived by upper-level software, such as an operating system. The physical address is an address for accessing a physical memory location of the solid-state memory device. Address mapping may also be implemented in the prior art using an intermediate address modality. E.g. mapping the logical address to an intermediate address, which in turn is further mapped to a physical address.

A table structure storing mapping information from logical addresses to physical addresses is called an FTL table. FTL tables are important metadata in solid state storage devices. Usually, the data entry of the FTL table records the address mapping relationship in the unit of data page in the solid-state storage device.

The FTL table includes a plurality of FTL table entries (or table entries). In one embodiment, each FTL table entry records a correspondence relationship between a logical page address and a physical page. In another example, each FTL table entry records the correspondence between consecutive logical page addresses and consecutive physical pages. In another embodiment, each FTL table entry records the corresponding relationship between the logical block address and the physical block address. In still another embodiment, the FTL table records the mapping relationship between logical block addresses and physical block addresses, and/or the mapping relationship between logical page addresses and physical page addresses.

Fig. 2 is a schematic diagram of a prior art control component accessing an FTL table. The control section 204 includes a plurality of CPUs (CPU210, CPU212, and CPU214) and a flash interface through which the CPU of the control section accesses the NVM chip in the solid-state storage device. The FTL table is stored in a memory external to control component 204 and includes a plurality of entries (entry 220, entry 222, and entry 224). Each of the plurality of CPUs can independently access the FTL table. Since FTL entries may be accessed by multiple CPUs simultaneously, to achieve data consistency, a lock is provided for each FTL entry. Referring to fig. 2, to update the FTL entry 224, the CPU210 checks the lock 234 of the FTL entry 224, and in case the lock 234 indicates that the FTL entry 224 is not locked, the CPU210 obtains the lock 234 (e.g., sets the lock 234 to the locked state) and acquires the FTL entry 224 (time t 1). Next, the CPU210 operates on the retrieved FTL entry 224 and updates the FTL entry 224 at time t4 and releases the lock 234 (e.g., sets the lock 234 to an unlocked state). During times t1-t4, the other CPUs (CPU 212 and CPU214) retrieve the presence of lock 234 and temporarily relinquish access to the FTL entry 224. In FIG. 2, at time t2, the CPU212 attempts to access the FTL entry 224, but finds that the lock 234 cannot be obtained, and then relinquishes access to the FTL entry 224. Similarly, the CPU214 may also relinquish access to the FTL entry 224 at time t3 because the lock 234 is not available. After time t4, however, CPU210 releases lock 234 and the CPU212 and the CPU214 that preempted lock 234 will access FTL entry 234. In another example, during the time period t1-t4, one task of the CPU210 acquires the lock 234, while another task in the CPU210 temporarily relinquishes access to the FTL entry 224 because the lock 234 was not acquired.

The lock of the FTL entry may be stored in the same location of the corresponding FTL entry, or the locks of a plurality of FTL entries may be collectively stored in another storage space.

Disclosure of Invention

In the solid-state storage device, a plurality of IO requests are processed simultaneously, and almost every IO request needs to access the FTL table. And the locking mechanism enables the access to the FTL table entry to be serialized, reduces the parallel processing capacity of solid-state storage, and increases the processing delay of the IO request.

In the present invention, there is provided a first method for processing an IO request according to the first aspect of the present invention, including: responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; in response to receiving the read request, accessing a first FTL table entry corresponding to the read request, and reading data from a physical address of the first table entry even if the first FTL table entry is locked; and allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

A first method for processing an IO request according to a first aspect of the present invention is provided, and a second method for processing an IO request according to the first aspect of the present invention is provided, where when a write request is processed, if a first FTL entry is locked, processing of the write request is aborted until the lock of the first FTL entry is released.

A second method for processing an IO request according to the first aspect of the present invention is provided, and a third method for processing an IO request according to the first aspect of the present invention is provided, where after the lock of the first FTL entry is released, the first FTL entry is obtained and locked.

A first method for processing an IO request according to a first aspect of the present invention is provided, and a fourth method for processing an IO request according to the first aspect of the present invention is provided, where when a write request is processed, if a first FTL entry is locked, processing of the write request is ended.

According to a second aspect of the present invention, there is provided a first method for processing an IO request, including: responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; responding to a received read request, accessing a first FTL table entry corresponding to the read request, and if the first FTL table entry is locked, taking data to be written in the write request as a response to the read request; and allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

According to a third aspect of the present invention, there is provided a method for processing an IO request according to the first aspect of the present invention, including: responding to a received write request, accessing a first FTL table entry and a second FTL table entry corresponding to the write request, and locking the first FTL table entry and the second FTL table entry; in response to receiving the read request, accessing a first FTL table entry corresponding to the read request, and reading data from a physical address of the first table entry even if the first FTL table entry is locked; the method includes allocating a first physical address and a second physical address for a write request, updating a first FTL table entry with the first physical address, unlocking the first FTL table entry, updating a second FTL table entry with the second physical address, and writing data to the first physical address and the second physical address.

According to a first method for processing an IO request in a third aspect of the present invention, there is provided a second method for processing an IO request in the third aspect of the present invention, wherein when a write request is processed, if a first FTL entry is locked, it is waited for the lock of the first FTL entry to be released.

According to a second method for processing an IO request of a third aspect of the present invention, there is provided the third method for processing an IO request of the third aspect of the present invention, wherein when a write request is processed, after a lock of a first FTL entry is released, the first FTL entry is obtained and locked.

According to a fourth aspect of the present invention, there is provided an apparatus for processing an IO request according to the fourth aspect of the present invention, including: the write request processing module is used for responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; the read request processing module is used for responding to the received read request, accessing a first FTL table entry corresponding to the read request, and reading data from a physical address of the first table entry even if the first FTL table entry is locked; and the write request execution module is used for allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry and writing data into the first physical address.

According to a fifth aspect of the present invention, there is provided an apparatus for processing an IO request according to the fifth aspect of the present invention, including: the write request processing module is used for responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; a read request processing module, configured to respond to a received read request, access a first FTL entry corresponding to the read request, and if the first FTL entry is locked, use data to be written in by the write request as a response to the read request; and the write request execution module is used for allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry and writing data into the first physical address.

According to a sixth aspect of the present invention, there is provided an apparatus for processing an IO request according to the sixth aspect of the present invention, including: the write request processing module is used for responding to a received write request, accessing a first FTL table entry and a second FTL table entry corresponding to the write request, and locking the first FTL table entry and the second FTL table entry; the read request processing module is used for responding to the received read request, accessing a first FTL table entry corresponding to the read request, and reading data from a physical address of the first table entry even if the first FTL table entry is locked; the write request execution module is configured to allocate a first physical address and a second physical address to the write request, update the first FTL entry with the first physical address, unlock the first FTL entry, update the second FTL entry with the second physical address, and write data to the first physical address and the second physical address.

According to a seventh aspect of the present invention, there is provided a method for processing an IO request according to the seventh aspect of the present invention, including: responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; responding to the received read request, accessing a first FTL table entry corresponding to the read request, and reading data from a physical address of the first table entry if the first FTL table entry is locked or the first FTL table entry is not locked; and allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

According to an eighth aspect of the present invention, there is provided a method for processing an IO request according to the eighth aspect of the present invention, including: responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked; responding to the received read request, accessing a first FTL table entry corresponding to the read request, and reading data from a physical address of the first table entry no matter whether the first FTL table entry is locked or not; and allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

According to a ninth aspect of the present invention there is provided a computer program comprising computer program code to, when loaded into a computer system and executed thereon, cause said computer system to perform a method of handling IO requests as provided in accordance with the first to third, seventh and eighth aspects of the present invention.

According to a first aspect of the present invention, there is provided a program comprising program code which, when loaded into a storage device and executed thereon, causes the storage device to perform the method of handling IO requests as provided in the first to third, seventh and eighth aspects of the present invention.

Drawings

The invention, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of a prior art storage device;

FIG. 2 is a schematic diagram of a control component of a prior art storage device accessing an FTL table;

fig. 3A is a schematic diagram of a control component of a storage device accessing an FTL table according to an embodiment of the present invention;

fig. 3B is a schematic diagram of a control component of a storage device accessing an FTL table according to another embodiment of the present invention;

fig. 3C is a schematic diagram of a control component of a storage device accessing an FTL table according to still another embodiment of the present invention; and

FIG. 4A is a flow diagram of accessing an FTL table for handling write commands according to an embodiment of the present invention; and

fig. 4B is a flow diagram of accessing an FTL table for processing a read IO command according to an embodiment of the present invention.

Detailed Description

In the NVMe (Non-Volatile Memory express) protocol, different IO command types are defined. For some IO commands, no requirements are made on the sequentiality between the IO commands. For example, if a read command for logical address x is submitted and a write command for logical address x is also submitted, although the execution result of the write command may affect the execution result of the read command, if the sequentiality between the two IO commands is not required, the NVMe protocol allows the solid-state storage device to execute the two IO commands in any order.

Aiming at the characteristic of the NVMe protocol, in the embodiment of the invention, the processing mode of the IO request is improved, so that the IO command processing capacity of the solid-state storage device is improved, and the processing delay of the IO command is reduced. Those skilled in the art will appreciate that while embodiments in accordance with the present invention are described in the context of the NVMe protocol, embodiments in accordance with the present invention may be implemented in other protocols that do not require an execution order between IO commands.

Referring to fig. 3A, a schematic diagram illustrating a control component of a storage device accessing an FTL table according to an embodiment of the present invention is shown. The control unit 304 of the solid state disk includes a plurality of CPUs (CPU 310, CPU 312, and CPU 314), each of which is capable of accessing the FTL table external to the control unit 304. The FTL table is stored in, for example, a DRAM (Dynamic Random Access Memory). The CPU of the control unit also accesses the NVM chip through a flash interface (not shown). By way of example, the CPU310 processes a write command from the host, accesses the FTL entry 324 (indicated by W-t1 of FIG. 3A) at time t1 in accordance with the logical address indicated by the write command to assign a physical address to the write command. To avoid multiple write commands writing the same logical address at the same time, a lock corresponding to an entry is also requested when accessing the FTL entry. In the example of FIG. 3A, the CPU310 accesses the lock 334 corresponding to the FTL entry 324. In the example of FIG. 3, the lock 334 indicates that the FTL entry 324 is not locked, and the CPU310 modifies the lock 334 to indicate a lock on the FTL entry 324. In an embodiment according to the present invention, when a write command is processed, a lock of an FTL entry to be modified by the write command is acquired. When the lock cannot be acquired, processing of the write command is temporarily suspended and release of the lock is awaited. In the example of FIG. 3A, after time t1, the CPU310 obtains a lock for the FTL entry 324. At this time, when other CPUs access the FTL entry 324 for processing the write command, since the lock 334 is found to indicate that the FTL entry 324 is locked, the processing of the write command accessing the FTL entry 324 is terminated.

Still referring to fig. 3A, the CPU 314 processes a read command from the host and accesses the FTL entry 324 at time t2 according to the logical address of the read command. Although FTL entry 324 is already locked, in the embodiment according to the present invention, CPU 314 ignores the lock of FTL entry 324, still obtains FTL entry 324, and obtains the physical address to be accessed according to FTL entry 324. Further, the CPU 314 or other CPUs read data by the physical address and provide the read data to the host as a response to the read command. Because the read command is processed without checking whether the FTL entry 324 is locked, the write command accessing the FTL entry 324 and one or more read commands accessing the FTL entry 324 can be executed simultaneously, thereby improving the parallel processing capability of the IO command. And reduces read command processing time since there is no need to wait for the lock of FTL entry 324 to be released when processing read commands.

In the example of FIG. 3A, to process a write command, the CPU310 assigns a new physical address to the write command and updates the FTL entry 324 with the new physical address, and at time t3, the CPU310 completes the update of the FTL entry 324 (indicated in FIG. 3 by W-t 3). And also writes data to the new physical address in response to the write command. The data may be written to the new physical address by CPU310 or other CPU. Thus, at time t2, which is before time t3, the CPU 314 obtains the old physical address from the FTL entry 324, and after time t3, the new physical address (updated by the CPU310 in processing write commands) is obtained from the FTL entry 324 in response to a read command. Therefore, when processing the read command, if the CPU 314 accesses the FTL entry 324 before the time t3, a different physical address is obtained by accessing the FTL entry 324 after the time t3, and different data is read. Such results conform to protocols such as NVMe protocol that do not require the order of processing of IO commands.

In one example, the lock 334 and the FTL entry 324 are stored separately from each other. To process a read command, the CPU 314 accesses the FTL entry 324 without accessing the lock 334. In another example, the lock 334 is stored in the same storage location as the FTL entry 324. While processing read commands, the CPU 314 will obtain the contents of the lock 334 while accessing the FTL entry 324, but the CPU 314 need not process the contents of the lock 334, but instead only care about the physical address provided by the FTL entry 324.

With continued reference to fig. 3A, the granularity of the lock is for each FTL entry. In response to the IO command, CPU 312 accesses FTL entry 328. For read commands, the CPU 312 ignores the lock 338 corresponding to the FTL entry 328; for write commands, CPU 312 checks lock 338 corresponding to FTL entry 328, and continues processing write commands only if lock 338 indicates that FTL entry 328 is not locked, and suspends processing write commands or defers updating FTL entry 328 if lock 338 indicates that FTL entry 328 is locked.

Fig. 3B is a schematic diagram of a control component of a storage device accessing an FTL table according to another embodiment of the present invention. Read or write commands from the host access different lengths of data and different numbers of FTL entries. In an embodiment consistent with the invention, the granularity of locking is per FTL entry. By way of example, the CPU310 processes a write command from the host, the write command accessing 3 logical addresses, and the CPU310 accesses the FTL entry 320, the FTL entry 322, and the FTL entry 324 (indicated by W1-t1, W2-t1, and W3-t1 of FIG. 3B) at time t1 to allocate a physical address for the write command. CPU310 also requests locks corresponding to the entries when accessing FTL entries, by accessing lock 330, lock 332, and lock 334 to request locks corresponding to FTL entries 320, FTL entries 322, and FTL entries 324. When the corresponding lock is acquired, the CPU310 performs subsequent operations, allocates a new physical address and updates the corresponding FTL entry with the new physical address, and when the corresponding lock cannot be acquired, the CPU310 stops the operation on the corresponding FTL entry and waits for the corresponding lock to be released. For example, the CPU310 obtains the lock of the FTL entry 320 and the FTL entry 322, but does not obtain the lock of the FTL entry 324, the CPU310 continues to update the FTL entry 320 and the FTL entry 322 by subsequent processing, and suspends the operation on the FTL entry 324 until the lock 334 of the FTL entry 324 is released and obtained by the CPU310, and the CPU310 continues to update the FTL entry 324. In response to the FTL entry being updated, data is also written to the new physical address in response to the write command. And when the new physical addresses of the three FTL table entries corresponding to the write command are all written with data, completing the write command processing.

Still referring to FIG. 3B, the CPU 314 processes the read command from the host, and accesses the FTL entry 324 (denoted as R-t2 in FIG. 3B) at time t2 according to the logical address of the read command. Although the FTL entry 324 has been locked by the CPU310 when processing the write command, in an embodiment according to the present invention, the CPU 314 ignores the lock of the FTL entry 324, still acquires the FTL entry 324, and acquires the physical address to be accessed according to the FTL entry 324. Further, the CPU 314 or other CPUs read data by the physical address and provide the read data to the host as a response to the read command. Because the read command is processed without checking whether the FTL entry 324 is locked, the write command accessing the FTL entry 324 and one or more read commands accessing the FTL entry 324 can be executed simultaneously, thereby improving the parallel processing capability of the IO command. And reduces read command processing time since there is no need to wait for the lock of FTL entry 324 to be released when processing read commands.

Fig. 3C is a schematic diagram of a control component of a storage device accessing an FTL table according to still another embodiment of the present invention. In the illustrated embodiment, FIG. 3C is an illustration of how multiple IO commands may be processed in parallel on the same CPU. By way of example, the CPU310 processes a write command from the host, and the CPU310 accesses the FTL entry 324 (indicated by W1-t2 of FIG. 3C) at time t1 to assign a physical address for the write command based on the logical address indicated by the write command. The CPU310 also requests a lock corresponding to the entry when accessing the FTL entry, and requests a lock corresponding to the FTL entry 324 by accessing the lock 334. Upon acquiring the corresponding lock, the CPU310 performs subsequent operations, allocates a new physical address and updates the corresponding FTL entry 324 with the new physical address at time t3 (the updating of the FTL entry 324 is indicated by W3-t3 of fig. 3C). Between times t1 and t3, the CPU310 also accesses the FTL entry 324 at time t2 in response to a host read command. Although at time t2, the lock 334 indicates that the FTL entry 324 is locked, for a read command, the CPU310 still accesses and uses the FTL entry 324 to read data using the physical address provided by the FTL entry 324 even though there is a lock on the FTL entry 324. In further embodiments, the CPU310 caches the FTL entry 324 retrieved at time t1, and retrieves the contents of the FTL entry 324 from the CPU310 cache at time t 2. And for processing read commands, whether or not the FTL entry 324 cached by the CPU310 is updated, reading data using the physical address provided by the cached FTL entry 324. At time t2, the CPU 314 accesses the FTL entry 324 (shown in FIG. 3C as R3-t 2) in response to the logical address of another read command. Because of the read command, although the lock 334 indicates that the FTL entry 324 is locked, the CPU 314 still accesses and uses the FTL entry 324 and reads data with the physical address provided by the FTL entry 324.

Fig. 4A is a flow diagram of accessing an FTL table for processing a write command according to an embodiment of the present invention. In an embodiment consistent with the invention, in response to receiving a write command (410) to access a logical address of a first FTL entry, it is checked (420) whether the first FTL entry is locked. If the first FTL table entry is locked, stopping the subsequent processing of the first FTL table entry and waiting for the lock of the first FTL table entry to be released. Subsequent processing of the first FTL entry is part of the processing of the write command. If the first FTL entry is not locked or the lock of the first FTL entry is released, to process the write command, the first FTL entry is locked (430) so that other write commands accessing the first FTL entry are temporarily suspended. To process the write command, a first physical address is assigned to the write command, the first FTL entry is updated with the first physical address, the updated FTL entry is written into the FTL table, and the first FTL entry is unlocked (440). Assigning a new physical address for a write command may utilize a variety of means known in the art. And writing data corresponding to the write command to the first physical address (450).

In another example, when the first FTL entry corresponding to the logical address of the write command is accessed in response to receiving the second write command, and the first FTL entry is found to be locked, the processing of the second write command is completed without allocating a physical address for the second write command and without writing data corresponding to the second write command to the nonvolatile memory.

Fig. 4B is a flow diagram of accessing an FTL table for processing a write command according to an embodiment of the present invention. In response to receiving the read command, the logical address of the read command corresponds to the first FTL entry (432). For read commands, it is not checked whether the first FTL entry is locked. Even if the first FTL entry has been locked due to processing the write command (see step 430 of fig. 4A), the locked first FTL entry is obtained from the FTL table and used when processing the read command (434). And reading the data (436) in response to the read command based on the first physical address.

In another example, when a first FTL entry is obtained for processing a read command, if the first FTL entry is locked, it indicates that there is a write command in execution accessing the first FTL table, and the data to be written by the write command is in the cache. And searching data to be written by the write command accessing the first FTL table from the cache as read data of the read command. The speed of obtaining data from the cache is far faster than the speed of obtaining data from the nonvolatile memory chip, so that the processing time of the read command is further reduced by using the cached data to be written as a response to the read command.

Embodiments of the present invention also provide a program comprising program code which, when loaded into and executed on a CPU, causes the CPU to perform one of the methods according to embodiments of the present invention provided above.

Embodiments of the present invention also provide a program comprising program code, which, when loaded into and executed on a storage device, causes the processor of the storage device to perform one of the methods according to embodiments of the present invention provided above.

It will be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by various means including computer program instructions. These computer program instructions may be loaded onto a general purpose computer, special purpose computer, or other programmable data control apparatus to produce a machine, such that the instructions which execute on the computer or other programmable data control apparatus create means for implementing the functions specified in the flowchart block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data control apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including computer-readable instructions for implementing the function specified in the flowchart block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data control apparatus to cause a series of operational operations to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide operations for implementing the functions specified in the flowchart block or blocks.

Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of operations for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Although the present invention has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the invention, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the invention.

Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A method of processing an IO request, comprising:

responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked;

in response to receiving a read request, accessing a first FTL table entry corresponding to the read request, and reading data from a physical address recorded by the first table entry even if the first FTL table entry is locked;

and allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry, and writing data into the first physical address.

2. The method of claim 1, wherein

When a write request is processed, if the first FTL table entry is locked, the processing of the write request is stopped until the lock of the first FTL table entry is released.

3. The method of claim 2, wherein

And after the lock of the first FTL table entry is released, acquiring the first FTL table entry and locking the first FTL table entry.

4. The method of claim 1, wherein

When a write request is processed, if the first FTL table entry is locked, the processing of the write request is finished.

5. A method of processing an IO request, comprising:

responding to the received read request, accessing a first FTL table entry corresponding to the read request, and if the first FTL table entry is locked, taking data to be written in the write request as a response to the read request;

6. A method of processing an IO request, comprising:

responding to a received write request, accessing a first FTL table entry and a second FTL table entry corresponding to the write request, and locking the first FTL table entry and the second FTL table entry;

in response to receiving the read request, accessing a first FTL table entry corresponding to the read request, and reading data from a physical address of the first table entry even if the first FTL table entry is locked;

the method includes allocating a first physical address and a second physical address for a write request, updating a first FTL table entry with the first physical address, unlocking the first FTL table entry, updating a second FTL table entry with the second physical address, and writing data to the first physical address and the second physical address.

7. The method of claim 6, wherein

When a write request is processed, if the first FTL table entry is locked, waiting for the lock of the first FTL table entry to be released.

8. The method of claim 7, wherein

When the write request is processed, after the lock of the first FTL table entry is released, the first FTL table entry is obtained, and the first FTL table entry is locked.

9. An apparatus to process IO requests, comprising:

the write request processing module is used for responding to the received write request, accessing a first FTL table entry corresponding to the write request, and locking the first FTL table entry if the first FTL table entry is not locked;

the read request processing module is used for responding to the received read request, accessing a first FTL table entry corresponding to the read request, and reading data from the physical address of the first table entry even if the first FTL table entry is locked;

and the write request execution module is used for allocating a first physical address for the write request, updating the first FTL table entry by using the first physical address, unlocking the first FTL table entry and writing data into the first physical address.

10. An apparatus to process IO requests, comprising:

a read request processing module, configured to respond to a received read request, access a first FTL entry corresponding to the read request, and if the first FTL entry is locked, use data to be written in by the write request as a response to the read request;