CN107544618A - Pointer synchronous circuit and method, message switching apparatus and method - Google Patents
Pointer synchronous circuit and method, message switching apparatus and method Download PDFInfo
- Publication number
- CN107544618A CN107544618A CN201610473495.9A CN201610473495A CN107544618A CN 107544618 A CN107544618 A CN 107544618A CN 201610473495 A CN201610473495 A CN 201610473495A CN 107544618 A CN107544618 A CN 107544618A
- Authority
- CN
- China
- Prior art keywords
- pointer
- synchronous circuit
- sub
- circuit
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 294
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000004044 response Effects 0.000 claims abstract description 55
- 230000005611 electricity Effects 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 16
- 230000005540 biological transmission Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000976 ink Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Multi Processors (AREA)
Abstract
The invention discloses a kind of pointer synchronous circuit and method, message switching apparatus and method, it is related to technical field of integrated circuits, the execution time length for solving processor, the occupancy of processor is high, and occupancy bus bar is roomy, and the technical problem of delay.The pointer synchronous circuit includes belonging to the first pointer register of the first clock zone with first processor, second pointer register and the first synchronous circuit in second clock domain is belonged to second processor；Wherein, the pointer value in the first pointer register may be in response to first processor and be updated, and the first synchronous circuit writes the pointer value in the first pointer register in the second pointer register, and the pointer value in the second pointer register can be read by second processor.The present invention is applied to the write-in and reading of the message between different processors.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of pointer synchronous circuit and method, message exchange dress
Put and method.
Background technology
Integrated circuit generally includes multiple processors, in order to realize the function of integrated circuit, between multiple processors often
Need to exchange information, wherein, message queue is the usual way for exchanging information among multiple processors.Usual above-mentioned message team
Row are stored in main storage (such as DRAM, Dynamic RandomAccess Memory, dynamic random access memory), or
Person, which is stored in, to be closed in the memory unit of a certain processor.
To exchange information, it is necessary to safeguard the head pointer and tail pointer of message queue using message queue, specifically, message is sent out
Message is inserted into the tail of the queue of message queue based on tail pointer by the side of going out (producer), and message receiver (consumer) is based on head pointer
The message in message queue is taken out from team's head of message queue, after message sends direction queue insertion message, modification rear of queue refers to
Pin, it is allowed to point to new tail of the queue.Message receiver changes queue head pointer, is allowed to point to new team after message is taken out in queue
Head.In above process, message sender need to identify message queue whether be it is full, message queue less than when, could be to disappearing
Queue insertion message is ceased, message receiver needs to identify whether message queue is sky, could be from message in message queue non-NULL
Message is taken out in queue.
From described above, the processor of message is exchanged using message queue can all access head pointer and tail pointer, lead to
Carry out the synchronization of head pointer/tail pointer frequently with the mode of inquiry, and if then cause when message queue is stored in into main storage,
The execution time of processor can be not only consumed, takes bus bandwidth, when the processor is coupled to main storage by bus,
The access delay of bus turns into performance bottleneck；If message queue is stored in when closing in the memory unit of a certain processor, no
The problem of it is inconsistent that the delay of the memory unit is accessed with processor, and then introduces synchronous, performance etc..
The content of the invention
It is an object of the invention to provide a kind of pointer synchronous circuit and method, message switching apparatus and method, for dropping
The execution time of low processor, the occupancy of processor is reduced, reduce and take bus bandwidth, and solve the technical problems such as delay.
The first aspect of the present invention provides a kind of pointer synchronous circuit, and the pointer synchronous circuit includes same with first processor
Belong to the first clock zone the first pointer register, with second processor belong to second clock domain the second pointer register and
First synchronous circuit；Wherein, the pointer value in the first pointer register may be in response to first processor and be updated, and first is synchronous
Circuit writes the pointer value in the first pointer register in the second pointer register, and the pointer value in the second pointer register can
Read by second processor.
With reference to the first aspect of the present invention, in the first possible implementation, the first synchronous circuit includes the first son
Synchronous circuit and the second sub- synchronous circuit；Wherein, the first pointer register, the synchronous electricity of the first son are updated in response to first processor
The second sub- synchronous circuit of road direction sends the instruction of synchronization request；The synchronization request sent in response to the first sub- synchronous circuit received
Instruction, the second sub- synchronous circuit sends the instruction for receiving synchronization request to the first sub- synchronous circuit, and by the first pointer register
Pointer value in device is write in the second pointer register.
With reference to the first aspect of the present invention, and its first possible implementation, in second of possible implementation
In, the pointer value in the first pointer register is write the second pointer register by first state indicating circuit in the first synchronous circuit
Period is in busy condition, and remaining is in idle condition；Wherein, when first state indicating circuit is in idle condition, subsequently
The operation that first processor updates the first pointer register is performed；When first state indicating circuit is in busy condition, after
The operation that continuous first processor updates the first pointer register is blocked.
With reference to the first or second of possible implementation of the first aspect of the present invention, in the third possible realization
In mode, the instruction for receiving synchronization request that is sent in response to the second sub- synchronous circuit received, the first sub- synchronous circuit is to
Two sub- synchronous circuits send the instruction synchronously completed；The finger synchronously completed sent in response to the first sub- synchronous circuit received
Show, the second sub- synchronous circuit receives the instruction synchronously completed to the first sub- synchronous circuit instruction；It is same in response to the second son for receiving
First state indicating circuit is arranged to idle shape by the instruction for receiving synchronization request of step circuit instruction, the first sub- synchronous circuit
State.
With reference to the first or second of possible implementation of the first aspect of the present invention, in the 4th kind of possible realization
In mode, the instruction for receiving synchronization request that is sent in response to the second sub- synchronous circuit received, the first sub- synchronous circuit is to
Two sub- synchronous circuits send the instruction synchronously completed；The finger synchronously completed sent in response to the first sub- synchronous circuit received
Show, the second sub- synchronous circuit receives the instruction synchronously completed to the first sub- synchronous circuit instruction；It is same in response to the second son for receiving
Step circuit instruction receives the instruction synchronously completed, and first state indicating circuit is arranged to idle shape by the first sub- synchronous circuit
State.
With reference to the first aspect of the present invention, the first to the 4th kind of possible implementation, in the 5th kind of possible realization
In mode, pointer synchronous circuit also includes the 3rd pointer register and second that the first clock zone is belonged to first processor
Processor belongs to the 4th pointer register and the second synchronous circuit in second clock domain；Wherein, in the 4th pointer register
Pointer value may be in response to second processor and be updated, and the second synchronous circuit is by the pointer value write-in the in the 4th pointer register
In three pointer registers, the pointer value in the 3rd pointer register can be read by first processor.
With reference to the 5th kind of possible implementation of the first aspect of the present invention, in the 6th kind of possible implementation,
Second synchronous circuit includes the 3rd sub- synchronous circuit and the 4th sub- synchronous circuit；Wherein, in response to second processor renewal the 4th
Pointer register, the 3rd sub- synchronous circuit send the instruction of synchronization request to the 4th sub- synchronous circuit；In response to receive the 3rd
The instruction for the synchronization request that sub- synchronous circuit is sent, the 4th sub- synchronous circuit is sent to the 3rd sub- synchronous circuit receives synchronization request
Instruction, and by the 4th pointer register pointer value write the 3rd pointer register in.
With reference to the 5th kind of the first aspect of the present invention or the 6th kind of possible implementation, in the 7th kind of possible realization
In mode, pointer synchronous circuit also includes the second condition indication circuit, and the second condition indication circuit is in the second synchronous circuit by
Pointer value in four pointer registers is in busy condition during writing the 3rd pointer register, and remaining is in idle condition；Its
In, when the second condition indication circuit is in idle condition, follow-up second processor updates the operation quilt of the 4th pointer register
Perform；When the second condition indication circuit is in busy condition, follow-up second processor updates the operation of the 4th pointer register
It is blocked.
With reference to the 6th kind of the first aspect of the present invention or the 7th kind of possible implementation, in the 8th kind of possible realization
In mode, the instruction for receiving synchronization request that is sent in response to the 4th sub- synchronous circuit received, the 3rd sub- synchronous circuit is to
Four sub- synchronous circuits send the instruction synchronously completed；The finger synchronously completed sent in response to the 3rd sub- synchronous circuit received
Show, the 4th sub- synchronous circuit receives the instruction synchronously completed to the 3rd sub- synchronous circuit instruction；It is same in response to the 4th son that receives
What step circuit was sent receives the instruction of synchronization request, and the second condition indication circuit is arranged to idle shape by the 3rd sub- synchronous circuit
State.
With reference to the 6th kind of the first aspect of the present invention or the 7th kind of possible implementation, in the 9th kind of possible realization
In mode, the instruction for receiving synchronization request that is sent in response to the 4th sub- synchronous circuit received, the 3rd sub- synchronous circuit is to
Four sub- synchronous circuits send the instruction synchronously completed；The finger synchronously completed sent in response to the 3rd sub- synchronous circuit received
Show, the 4th sub- synchronous circuit receives the instruction synchronously completed to the 3rd sub- synchronous circuit instruction；It is same in response to the 4th son that receives
Step circuit instruction receives the instruction synchronously completed, and the second condition indication circuit is arranged to idle shape by the 3rd sub- synchronous circuit
State.
With reference to the 5th kind of possible implementation of the first aspect of the present invention, in the tenth kind of possible implementation,
Pointer synchronous circuit also includes belonging to the first queue condition indication circuit of the first clock zone, and belongs to the of second clock domain
Two quene state indicating circuits；Wherein, first queue condition indication circuit is by comparing the first pointer register and the 3rd pointer
The value of register determines whether quene state is normal, and in quene state exception, interrupt signal is sent to first processor；The
Two quene state indicating circuits determine whether quene state is normal by the second pointer register and the 4th pointer register, and
During quene state exception, interrupt signal is sent to second processor.
With reference to the 5th kind of possible implementation of the first aspect of the present invention, in a kind of the tenth possible implementation
In, pointer synchronous circuit also includes two quene state indicating circuits, a quene state indicating circuit include the first register,
First XOR circuit and first comparator, another quene state indicating circuit include the second register, the second XOR circuit and
Second comparator；First XOR circuit is by the first register and the first pointer register be different or, first comparator is by XOR knot
Fruit compared with the 3rd pointer register, wherein, if XOR result is equal with the 3rd pointer register, quene state is different
Often, corresponding quene state indicating circuit sends interrupt signal to first processor；Second XOR circuit by the second register with
4th pointer register is different or, the second comparator by XOR result compared with the second pointer register, wherein, if XOR
As a result equal with the second pointer register, then quene state is abnormal, and corresponding quene state indicating circuit is sent out to second processor
Go out interrupt signal.
With reference to a kind of the tenth possible implementation of the first aspect of the present invention, in the 12nd kind of possible implementation
In, the first register can be accessible by the first processor, and the second register can be accessed by second processor.
With reference to the 5th kind of possible implementation of the first aspect of the present invention, in the 13rd kind of possible implementation,
First pointer register and the 3rd pointer register are provided by the first public register, wherein, the low level of the first public register
The first pointer register is provided, the high-order of the first public register provides the 3rd pointer register；Second pointer register and
Four pointer registers are provided by the second public register, wherein, the low level of the second public register provides the 4th pointer register,
The high-order of second public register provides the second pointer register.
Because the pointer synchronous circuit in the first aspect of the present invention has structure as described above, so that at first
Reason device is updated to the pointer value in the first pointer register, and the first synchronous circuit is by the pointer value in the first pointer register
Write in the second pointer register, second processor read pointer values from the second pointer register, you can in first processor
The write-in and reading of message are realized between second processor, therefore, can be reduced the execution time of each processor, is reduced everywhere
The occupancy of device is managed, reduces and takes bus bandwidth；And because first processor and the first pointer register belong to the first clock
Domain, second processor and the second pointer register belong to second clock domain, so as to solve the problems, such as delay.
The second aspect of the present invention provides a kind of pointer synchronous method, and the pointer synchronous method includes：At first
The pointer value in device the first pointer register of renewal is managed, busy shape is indicated to first processor by first state indicating circuit
State；Pointer value in first pointer register is write in the second pointer register；And by first state indicating circuit to
First processor indicates idle condition；Wherein, the first pointer register and first processor belong to the first clock zone, and second refers to
Pin register and second processor belong to the second clock domain different from the first clock zone.
With reference to the second aspect of the present invention, in the first possible implementation, pointer synchronous method also includes：First
When processor request updates the pointer value in the first pointer register, according to the state of first state indicating circuit, at first
The operation that reason device updates the first pointer register is controlled；Wherein, if first state indicating circuit is in busy condition, subsequently
The operation that first processor updates the first pointer register is blocked；If first state indicating circuit is in idle condition, subsequently
The operation that first processor updates the first pointer register is performed.
With reference to the second aspect of the present invention, in second of possible implementation, by the finger in the first pointer register
Pin value, which writes the second pointer register, to be included：First sub- synchronous circuit sends the finger of synchronization request to the second sub- synchronous circuit
Show；The instruction of the synchronization request sent in response to the first sub- synchronous circuit received, the second sub- synchronous circuit are synchronous to the first son
Circuit sends the instruction for receiving synchronization request, and the pointer value in the first pointer register is write in the second pointer register.
With reference to second of possible implementation of the second aspect of the present invention, in the third possible implementation,
Indicate that idle condition includes to first processor by first state indicating circuit：In response to the second sub- synchronous circuit hair received
What is gone out receives the instruction of synchronization request, and the first sub- synchronous circuit sends the instruction synchronously completed to the second sub- synchronous circuit；Response
In the instruction synchronously completed that the first sub- synchronous circuit received is sent, the second sub- synchronous circuit indicates to the first sub- synchronous circuit
Receive the instruction synchronously completed；In response to the instruction for receiving synchronization request of the second sub- synchronous circuit instruction received, the first son
First state indicating circuit is arranged to idle condition by synchronous circuit.
With reference to second of possible implementation of the second aspect of the present invention, in the 4th kind of possible implementation,
Indicate that idle condition includes to first processor by first state indicating circuit：In response to the second sub- synchronous circuit hair received
What is gone out receives the instruction of synchronization request, and the first sub- synchronous circuit sends the instruction synchronously completed to the second sub- synchronous circuit；Response
In the instruction synchronously completed that the first sub- synchronous circuit received is sent, the second sub- synchronous circuit indicates to the first sub- synchronous circuit
Receive the instruction synchronously completed；The instruction synchronously completed, the first son are received in response to what the second sub- synchronous circuit received indicated
First state indicating circuit is arranged to idle condition by synchronous circuit.
With reference to the second aspect of the present invention, the first possible implementation to the 4th kind of possible implementation,
In five kinds of possible implementations, pointer synchronous method also includes：Updated in response to second processor in the 4th pointer register
Pointer value, by the second condition indication circuit to second processor indicate busy condition；By the finger in the 4th pointer register
Pin value is write in the 3rd pointer register；And idle condition is indicated to second processor by the second condition indication circuit；Its
In, the 3rd pointer register and first processor belong to the first clock zone, and the 4th pointer register and second processor belong to the
Two clock zones.
With reference to the 5th kind of possible implementation of the second aspect of the present invention, in the 6th kind of possible implementation,
Pointer synchronous method also includes：When second processor request updates the pointer value in the 4th pointer register, according to the second state
The state of indicating circuit, the operation that the 4th pointer register is updated to second processor are controlled；Wherein, if the second state refers to
Show that circuit is in busy condition, the operation that follow-up second processor updates the 4th pointer register is blocked；If the second state refers to
Show that circuit is in idle condition, the operation that follow-up second processor updates the 4th pointer register is performed.
With reference to the 6th kind of possible implementation of the second aspect of the present invention, in the 7th kind of possible implementation,
Pointer value in 4th pointer register is write into the 3rd pointer register includes：3rd sub- synchronous circuit is synchronous to the 4th son
Circuit sends the instruction of synchronization request；The instruction of the synchronization request sent in response to the 3rd sub- synchronous circuit received, the 4th son
Synchronous circuit sends the instruction for receiving synchronization request to the 3rd sub- synchronous circuit, and the pointer value in the 4th pointer register is write
Enter in the 3rd pointer register.
With reference to the 7th kind of possible implementation of the second aspect of the present invention, in the 8th kind of possible implementation,
Indicate that idle condition includes to second processor by the second condition indication circuit：In response to the 4th sub- synchronous circuit hair received
What is gone out receives the instruction of synchronization request, and the 3rd sub- synchronous circuit sends the instruction synchronously completed to the 4th sub- synchronous circuit；Response
In the instruction synchronously completed that the 3rd sub- synchronous circuit received is sent, the 4th sub- synchronous circuit indicates to the 3rd sub- synchronous circuit
Receive the instruction synchronously completed；The instruction for receiving synchronization request sent in response to the 4th sub- synchronous circuit received, the 3rd son
Second condition indication circuit is arranged to idle condition by synchronous circuit.
With reference to the 7th kind of possible implementation of the second aspect of the present invention, in the 9th kind of possible implementation,
Indicate that idle condition includes to second processor by the second condition indication circuit：In response to the 4th sub- synchronous circuit hair received
What is gone out receives the instruction of synchronization request, and the 3rd sub- synchronous circuit sends the instruction synchronously completed to the 4th sub- synchronous circuit；Response
In the instruction synchronously completed that the 3rd sub- synchronous circuit received is sent, the 4th sub- synchronous circuit indicates to the 3rd sub- synchronous circuit
Receive the instruction synchronously completed；The instruction synchronously completed, the 3rd son are received in response to what the 4th sub- synchronous circuit received indicated
Second condition indication circuit is arranged to idle condition by synchronous circuit.
With reference to the 5th kind of possible implementation of the second aspect of the present invention, in the tenth kind of possible implementation,
Pointer synchronous method also includes comparing the first pointer register and the value of the 3rd pointer register determines whether quene state is normal,
And in quene state exception, interrupt signal is sent to first processor；And compare the second pointer register and the 4th pointer
The value of register determines whether quene state is normal, and in quene state exception, interrupt signal is sent to second processor.
With reference to the 5th kind of possible implementation of the second aspect of the present invention, in a kind of the tenth possible implementation
In, pointer synchronous method also includes：Make the first register and the first pointer register different or, wherein, if XOR result and the
Three pointer registers are equal, then send interrupt signal to first processor；Make the second register and the 4th pointer register different
Or, wherein, if XOR result is equal with the second pointer register, interrupt signal is sent to second processor.
Pointer synchronous method in the second aspect of the present invention has synchronous with the pointer in above-described first aspect
Circuit identical beneficial effect, is no longer repeated herein.
The third aspect of the present invention provides a kind of pointer synchronous circuit, and the pointer synchronous circuit includes belonging to same clock zone
The 5th pointer register and the 6th pointer register；Wherein, the pointer value in the 5th pointer register may be in response at first
Reason device is updated, and can be read by second processor；Pointer value in 6th pointer register may be in response to second processor
It is updated, and can be read by first processor.
With reference to the third aspect of the present invention, in possible implementation, pointer synchronous circuit also refers to including the third state
Show circuit and the 4th condition indication circuit, third state indicating circuit is in when first processor updates five pointer registers
Busy condition, remaining is in idle condition, the 4th condition indication circuit when second processor updates six pointer registers at
In busy condition, remaining is in idle condition；Wherein, when third state indicating circuit is in idle condition, first processor
The operation for updating the 5th pointer register is performed；When third state indicating circuit is in busy condition, follow-up first processing
The operation that device updates the 5th pointer register is blocked；When the 4th condition indication circuit is in idle condition, at follow-up second
The operation that reason device updates the 6th pointer register is performed；When the 4th condition indication circuit is in busy condition, second processing
The operation that device updates the 6th pointer register is blocked.
Because the pointer synchronous circuit in the third aspect of the present invention has structure as described above, so that at first
Reason device is updated to the pointer value in the 5th pointer register, is read by second processor, second processor is to the 6th pointer
Pointer value in register is updated, and first processor reads the pointer value in the 6th pointer register, and second processor is read
Take the pointer value in the 5th pointer register, you can the write-in and reading of message are realized between first processor and second processor
Take, therefore, the execution time of each processor can be reduced, reduce the occupancy of each processor, reduce and take bus bandwidth；And by
Same clock zone is belonged in first processor, second processor, the 5th pointer register and the 6th pointer register, so as to also
The problem of can solve the problem that delay.
The fourth aspect of the present invention provides a kind of message switching method, and the message switching method includes：Generation one or more
Individual message, the queue tail of the queue that one or more message are write in memory；By the synchronous electricity of address write-in pointer of queue tail of the queue
First pointer register on road.
It is same the address of queue tail of the queue is write into pointer in possible implementation with reference to the fourth aspect of the present invention
Before first pointer register of step circuit, the message switching method also includes：The first state of inquiry pointer synchronous circuit refers to
Show circuit；If first state indicating circuit is in idle condition, the address of queue tail of the queue is write the of pointer synchronous circuit
One pointer register.
The pointer synchronous circuit that the message switching method that the fourth aspect of the present invention provides is provided based on first aspect, because
This, the pointer synchronous circuit identical that the message switching method that the fourth aspect of the present invention provides has and first aspect provides has
Beneficial effect, is no longer repeated herein.
The fifth aspect of the present invention provides a kind of message switching apparatus, the message switching apparatus include message generating module and
Pointer update module, wherein, message generating module is used to generate one or more message, and the write-in of one or more message is deposited
Queue tail of the queue in reservoir；The first pointer that pointer update module is used to write the address of queue tail of the queue pointer synchronous circuit is posted
Storage.
With reference to the fifth aspect of the present invention, in possible implementation, it is same that pointer update module is additionally operable to inquiry pointer
The first state indicating circuit of step circuit, wherein, if first state indicating circuit is in idle condition, pointer update module is by team
Line up the first pointer register of the address write-in pointer synchronous circuit of tail.
The message switching method phase that the message switching apparatus that the fifth aspect of the present invention provides has and fourth aspect provides
Same beneficial effect, is no longer repeated herein.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, embodiment will be described below
In the required accompanying drawing used be briefly described, it should be apparent that, drawings in the following description be only the present invention some
Embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, can also be attached according to these
Figure obtains other accompanying drawings.
Fig. 1 is the schematic diagram of the first pointer synchronous circuit in the embodiment of the present invention；
Fig. 2 is the schematic diagram of second of pointer synchronous circuit in the embodiment of the present invention；
Fig. 3 is the schematic diagram of the pointer synchronizing process in the embodiment of the present invention；
Fig. 4 is the schematic diagram of the third pointer synchronous circuit in the embodiment of the present invention；
Fig. 5 is the schematic diagram of the 4th kind of pointer synchronous circuit in the embodiment of the present invention；
Fig. 6 is the schematic diagram of the 5th kind of pointer synchronous circuit in the embodiment of the present invention；
Fig. 7 is the schematic diagram of the 6th kind of pointer synchronous circuit in the embodiment of the present invention；
Fig. 8 is the schematic diagram of the 7th kind of pointer synchronous circuit in the embodiment of the present invention；
Fig. 9 is the schematic diagram of the 8th kind of pointer synchronous circuit in the embodiment of the present invention；
Figure 10 is the schematic diagram of the 9th kind of pointer synchronous circuit in the embodiment of the present invention；
Figure 11 is the schematic diagram of the head registers of the flag bit that includes unrolling in the embodiment of the present invention；
Figure 12 is the first partial schematic diagram of the quene state indicating circuit in the embodiment of the present invention；
Figure 13 is second of partial schematic diagram of the quene state indicating circuit in the embodiment of the present invention；
Figure 14 is the schematic diagram of the tenth kind of pointer synchronous circuit in the embodiment of the present invention；
Figure 15 is the tenth a kind of schematic diagram of pointer synchronous circuit in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is part of the embodiment of the present invention, rather than whole embodiments.Based on this hair
Embodiment in bright, the every other implementation that those of ordinary skill in the art are obtained under the premise of creative work is not made
Example, belongs to the scope of protection of the invention.
It should be noted that passed through in following embodiment with first processor (CPU1) and second processor (CPU2)
Message queue exchanges information, and first processor reads message from message queue, and second processor is to message queue write-in message
Example, is described in detail, wherein, CPU1 and CPU2 safeguards head registers with tail registers to indicate message queue shape jointly
State simultaneously operates to message queue, tail registers storage tail pointer value, the tail of the queue position of the value instruction message queue of tail pointer
Put, when CPU2 is to message queue tail of the queue write-in message, the pointer value of the new tail of the queue of message queue is also write into tail registers, head
Team's head position of the value instruction message queue of pointer, CPU1 from message queue team head read message when, also by the new of message queue
The pointer value write-in heal registers of team's head.
Certainly, those skilled in the art are based on following description, can necessarily learn that CPU1 reads message from message queue,
CPU2 is no longer repeated to detailed embodiment during message queue write-in message, the application.
Embodiment one
As shown in figure 1, pointer synchronous circuit includes the head registers that the first clock zone is belonged to CPU1, it is same with CPU2
Belong to the head_sync registers in second clock domain, and synchronous circuit 10, CPU1 can high speed access head registers (for example,
One bus cycles), CPU2 can high speed access head_sync registers (for example, a bus cycles).In head register quilts
When CPU1 updates, synchronous circuit 10 sends the new value of head registers to head_sync registers.Wherein, synchronous circuit 10
Can in several ways by the new value of head registers send to head_sync registers (such as bus transfer, network transmission with
And hardwire transmission).
For the pointer synchronous circuit in embodiment one, because head registers are close in CPU1, CPU1 renewals head is posted
The operation of storage can be rapidly completed, and then CPU1 can continue with other tasks.Although synchronous circuit 10 is by head registers
New value write-in head_sync registers, after the completion of the operation, CPU2 could know from head_sync registers CPU1 write
The value of head registers, the operation may need the long period, but in this period, CPU1 and CPU2 can perform other
Business, so as to improve CPU1 and CPU2 utilization rate.
Embodiment two
Based on embodiment one, as shown in Fig. 2 synchronous circuit 10 includes sub- synchronous circuit 101 and sub- synchronous circuit 102,
After CPU1 renewal head registers, sub- synchronous circuit 101 and sub- synchronous circuit 102 exchange handshake signals each other, to identify head
Whether the value of register is reliably written head_sync registers.Because signal is in head registers and head_sync deposits
Being transmitted between device has delay, after time delay, represent head registers each bit status from head registers
The signal of extraction is just reliably transmitted to head_sync registers.For identification signal transmission delay, sub- synchronous circuit 101 with
Sub- synchronous circuit 102 exchange handshake signals each other.Handshake is transmitted between sub- synchronous circuit 101 and sub- synchronous circuit 102,
The time delay of handshake is close to from head registers to the signal delay of head_sync registers.Thus handshake
After reliably being exchanged between a_Sync1 and b_Sync1, the signal that can be speculated from the output of head registers is also reliably transmitted
To Head_sync registers.
Fig. 3 is the schematic diagram of the pointer synchronizing process in the embodiment of the present invention, illustrates CPU1 renewal head registers, son
The value renewal of head registers is arrived head_sync registers by synchronous circuit 101 with sub- synchronous circuit 102, and CPU2 reads head_
The process of sync registers.
At the 1. moment, the write operation (by effective a_wr signal designations) to head registers occurs for CPU1.It is because sub
(effective) the instruction synchronous regime of a_idle signals of synchronous circuit 101 is idle condition, it is allowed to which CPU1 updates head deposits immediately
Device, head registers can be immediately subjected to the value of write-in.Then, in response to a_wr signals, effectively (and a_idle signal designations are same
Step state is idle condition), sub- synchronous circuit 101 sends synchronization request (i.e. setting a_sync_to_b_in signals are effective), and
Synchronous regime is arranged to be carrying out synchronous (setting a_idle invalidating signals).After a period of time, sub- synchronous circuit 101 is sent out
The synchronization request (effective a_sync_to_b_in signals) gone out is sent to sub- synchronous circuit 102 and (received in sub- synchronous circuit 102
Effective a_sync_to_b_out signals).
At the 2. moment, sub- synchronous circuit 102 receives synchronization request (i.e. a_sync_to_b_out signals are effective), now
The new value of head registers has been stably transmitted to sub- synchronous circuit 102.Then, sub- synchronous circuit 102 deposits head
Device value write-in head_sync registers, and send receive synchronization request instruction (i.e. set b_sync_to_a_in signals have
Effect), notify sub- synchronous circuit 101 to complete subsynchronous.After a period of time, what sub- synchronous circuit 102 was sent receives synchronization
Request instruction (i.e. b_sync_to_a_out signals are effective) is sent to sub- synchronous circuit 101.
At the 3. moment, sub- synchronous circuit 101 receives the synchronization request that receives that sub- synchronous circuit 102 is sent and indicates (i.e. b_
Sync_to_a_out signals are effective).
The synchronization request that receives sent in response to receiving sub- synchronous circuit 102 indicates that (i.e. b_sync_to_a_out signals have
Effect), at the 4. moment, sub- synchronous circuit 101, which is sent, synchronously completes instruction (i.e. a_sync_to_b_in signals are changed into invalid).
At the 5. moment, what sub- synchronous circuit 102 received that sub- synchronous circuit 101 sends synchronously completes instruction (i.e. a_sync_
To_b_out signals are changed into invalid), and send to receive to sub- synchronous circuit 101 and synchronously complete instruction (b_sync_to_ is set
A_in signals are changed into invalid).After a period of time, what sub- synchronous circuit 102 was sent receive synchronously complete instruction be sent to it is sub same
Step circuit 101 (i.e. b_sync_to_a_out invalidating signals).
At the 6. moment, sub- synchronous circuit 101 receives sub- receiving for the transmission of synchronous circuit 102 and synchronously completes instruction (i.e. b_
Sync_to_a_out signals are changed into invalid).
At the 7. moment, receive sub- receiving for the transmission of synchronous circuit 102 in response to sub- synchronous circuit 101 and synchronously complete instruction
(i.e. b_sync_to_a_out signals are changed into invalid), sub- synchronous circuit 101 know that this synchronizing process is completed, can allowed
CPU1 update next time the operation of head registers, then indicates that synchronous regime (is set a_idle signals for the free time
It is effective).
In another example, at the 3. moment, what sub- synchronous circuit 101 received that sub- synchronous circuit 102 sends receives synchronization
After request instruction (i.e. b_sync_to_a_out signals are effective), sub- synchronous circuit 101 knows to have had time enough by head
The value of register is synchronized to head_Sync registers, and CPU1 can be allowed update next time the operation of head registers, in
It is that instruction synchronous regime is idle (a_idle signals are arranged into effective).
Embodiment three
Based on embodiment one or embodiment two, the value write-in head_sync of head registers is posted in synchronous circuit 10
During storage, for reliably synchrodata, avoid introducing wrong data, identify and indicate synchronous regime, as shown in figure 4, pointer
Synchronous circuit also includes condition indication circuit 20, when indicating CPU1 renewal head registers (for example, passing through execute instruction), shape
Whether state indicating circuit 20 is completed to the CPU1 operations for indicating to write the value of head registers into head_sync registers.It is if same
The operation that step circuit 10 writes the value of head registers in head_sync registers is not yet completed, then at condition indication circuit 20
In busy condition, block CPU1 execution, until the value of head registers is write head_sync registers by synchronous circuit 10
Afterwards, condition indication circuit 20 is in idle condition, and CPU1 just performs the renewal to head registers, and causes synchronous circuit 10 again
It is secondary synchronous with head_sync registers to head registers.When indicating CPU1 renewal head registers, if in the absence of
Carry out from head registers to the simultaneously operating of head_sync registers, then condition indication circuit 20 is in idle condition,
CPU1 is immediately performed the renewal to head registers.
Example IV
Based on the embodiment three based on embodiment two, sub- synchronous circuit 101 sends synchronous ask to sub- synchronous circuit 102
After asking instruction, sub- synchronous circuit 102 to receive synchronization request instruction, the instruction for receiving synchronization request is sent to sub- synchronous circuit 101,
The instruction of synchronization request is received in response to this, sub- synchronous circuit 101 sends the instruction synchronously completed, and sub- synchronous circuit 102 receives
After the instruction synchronously completed, instruction is sent to sub- synchronous circuit 101, to show to have received what sub- synchronous circuit 101 was sent
The instruction synchronously completed.In one example, sub- synchronous circuit 101 receive that sub- synchronous circuit 102 sends this receive synchronization
After the instruction of request, i.e., condition indication circuit 20 is arranged to idle condition, so as to which CPU1 can update head registers again.
In another example, after what sub- synchronous circuit 102 received that sub- synchronous circuit 101 indicates receives the instruction that this is synchronously completed, i.e.,
Condition indication circuit 20 is arranged to idle condition, so as to which CPU1 can update head registers again.
Embodiment five
Based on any one in embodiment one to four, as shown in figure 5, pointer synchronous circuit also includes belonging to CPU1
The tail_sync registers of first clock zone, the tail registers in second clock domain, and synchronous circuit are belonged to CPU2
30, CPU2 can high speed access tail registers (for example, a bus cycles), CPU1 can high speed access tail_sync registers
(for example, a bus cycles), when tail registers are updated by CPU2, synchronous circuit 30 transmits the new value of tail registers
Give tail_sync registers.Wherein, synchronous circuit 30 can send the new value of tail registers to tail_ in several ways
Sync registers (such as bus transfer, network transmission and hardwire transmission).
For above-mentioned pointer synchronous circuit, because tail registers are close in CPU2, CPU2 updates the behaviour of tail registers
Work can be rapidly completed, and then CPU2 can continue with other tasks.Although synchronous circuit 30 writes the new value of tail registers
Enter tail_sync registers, after the completion of the operation, CPU1 could know CPU2 write-in tail deposits from tail_sync registers
The value of device, the operation may need the long period, but in this period, CPU1 and CPU2 can perform other tasks, so as to carry
High CPU1 and CPU2 utilization rate.
Embodiment six
Based on embodiment five, as shown in fig. 6, synchronous circuit 30 includes sub- synchronous circuit 301 and sub- synchronous circuit 302,
After CPU2 renewal tail registers, sub- synchronous circuit 301 sends synchronization request instruction, sub- synchronous circuit to sub- synchronous circuit 302
After 302 receive synchronization request instruction, the instruction for receiving synchronization request is sent to sub- synchronous circuit 301, and by tail registers
New value write-in tail_sync registers.
CPU2 updates tail registers, and sub- synchronous circuit 301 arrives the value renewal of tail registers with sub- synchronous circuit 302
The sub- synchronous circuit 101 that is shown in the process and figure 3 above of tail_sync registers and sub- synchronous circuit 102 are by head registers
Value renewal to head_sync registers procedure it is similar, here is omitted.
Embodiment seven
Based on embodiment five or embodiment six, the value write-in tail_sync of tail registers is posted in synchronous circuit 30
During storage, for reliably synchrodata, avoid introducing wrong data, identify and indicate synchronous regime.As shown in fig. 7, pointer
Synchronous circuit also includes condition indication circuit 40, when indicating CPU2 renewal tail registers (for example, passing through execute instruction), shape
Whether state indicating circuit 40 is completed to the CPU2 operations for indicating to write the value of tail registers into tail_sync registers.It is if same
The operation that step circuit 30 writes the value of tail registers in tail_sync registers is not yet completed, then at condition indication circuit 40
In busy condition, block CPU2 execution, until the value of tail registers is write tail_sync registers by synchronous circuit 30
Afterwards, condition indication circuit 40 is in idle condition, and CPU2 just performs the renewal to tail registers, and causes synchronous circuit 30 again
It is secondary synchronous with tail_sync registers to tail registers.When indicating CPU2 renewal tail registers, if in the absence of
Carry out from tail registers to the simultaneously operating of tail_sync registers, then condition indication circuit 40 is in idle condition,
CPU2 is immediately performed the renewal to tail registers.
Embodiment eight
Based on the embodiment seven based on embodiment six, sub- synchronous circuit 301 sends synchronous ask to sub- synchronous circuit 302
After asking instruction, sub- synchronous circuit 302 to receive synchronization request instruction, the instruction of synchronization request is received to the instruction of sub- synchronous circuit 301,
The instruction of synchronization request is received in response to this, sub- synchronous circuit 301 sends the instruction synchronously completed, and sub- synchronous circuit 302 receives
After the instruction synchronously completed, instruction is sent to sub- synchronous circuit 301, to show to have received what sub- synchronous circuit 301 was sent
The instruction synchronously completed.In one example, sub- synchronous circuit 301 receive that sub- synchronous circuit 302 sends this receive synchronization
After the instruction of request, i.e., condition indication circuit 40 is arranged to idle condition, so as to which CPU2 can update tail registers again.
, will after what sub- synchronous circuit 302 received that sub- synchronous circuit 301 indicates receives the instruction synchronously completed in another example
Condition indication circuit 40 is arranged to idle condition, so as to which CPU2 can update tail registers again.
Embodiment nine
Based on embodiment five, as shown in figure 8, pointer synchronous circuit also includes the quene state instruction for belonging to the first clock zone
Circuit 50, and belong to the quene state indicating circuit 60 in second clock domain, so that the value according to head pointer and tail pointer,
It can determine the state of queue.Queue less than when, CPU2 can write data to tail of the queue, queue completely when, CPU2 can not be to
Tail of the queue writes data, and in queue not empty, CPU1 can take out data from team's head, and be space-time in queue, and CPU1 can not be from team's head
Take out data.Wherein, quene state indicating circuit 60 compares the value of head_sync registers and tail registers, and according to than
Compared with result to CPU2 instruction quene states to be full or non-full, quene state indicating circuit 50 compare tail_sync registers with
The value of head registers, and indicate quene state for empty or non-NULL to CPU1 according to comparative result.
In one example, when head registers are identical with the value of tail_sync registers, quene state is sky, its
In the case of him, quene state is non-NULL.And when the highest order of head_sync registers and tail registers is on the contrary, and remove highest
Position outside other it is identical when, quene state is full；In the case of other, quene state is non-full.It is pointed out that queue
The specific judgment mode of state is relevant with queue depth and queue address, and those skilled in the art are based on being actually needed and can entering
Row reasonable selection.
Quene state indicating circuit 50 can send interruption when it is determined that quene state is non-NULL to CPU1, with instruction
Pending message in CPU1 queues be present.Quene state indicating circuit 60, can be to CPU2 when it is determined that quene state is full
Interruption is sent, to indicate that CPU2 queues are full, message should not be write into queue again.Now CPU2 can inquire about the shape for determining queue
State, when queue is non-full, then message is write into queue.
Certainly, CPU1 and/or CPU2 can also query request condition indication circuit 50 and/or quene state indicating circuit
60, to know the state of queue.
Embodiment ten
Based on embodiment five, deposited as shown in figure 9, providing head registers by a 32 bit register A with tail_sync
High 16 of device, wherein register A are used as tail_sync registers, and low 16 of register A are used as head registers.With
And head_sync registers and tail registers are provided by a 32 bit register B, high 16 of wherein register B are used as
Head_sync registers, and low 16 of register B are used as tail registers.And register A low 16 (head deposits
Device) it is coupled to by synchronous circuit 101 register B high 16 (head_sync registers), and low 16 of register B
(tail registers) is coupled to register A high 16 (tail_sync registers) by synchronous circuit 102, so as to synchronous electricity
Road 101 is used for the content synchronization of head registers to head_sync registers, and synchronous circuit 102 is used to deposit tail
The content synchronization of device is to tail_sync registers.
In this way, CPU1 is when updating head registers, low 16 of renewal register A, and CPU2 is in renewal tail
During register, low 16 of CPU2 are updated.So as in CPU1 with being updated respectively using identical program segment in CPU2
Head registers and tail registers.And CPU1 reads the high 16 of register A when reading tail_sync registers, and
CPU2 reads the high 16 of register B when reading head_sync registers.So as in CPU1 with using phase in CPU2
With program segment read tail_sync registers and head_sync registers respectively.
Embodiment 11
Based on embodiment five or embodiment ten, as shown in Figure 10, pointer synchronous circuit also includes quene state indicating circuit
70 and quene state indicating circuit 80, quene state indicating circuit 70 includes negating register (reg_A_inverse) 701, different
Or circuit 702 and comparator 703, quene state indicating circuit 80 include negating register (reg_B_inverse) 801, XOR
Circuit 802 and comparator 803；XOR circuit 702 will negate that register 701 and head registers are different or, comparator 703 will be different
Or result is compared with tail_sync registers, wherein, if XOR result is equal with tail_sync registers, queue shape
State is sky, and quene state indicating circuit 70 sends interrupt signal to CPU1.XOR circuit 802 will negate register 801 and tail
Register is different or, comparator 803 by XOR result compared with head_sync registers, wherein, if XOR result with
Head_sync registers are equal, then quene state is full, and quene state indicating circuit 80 sends interrupt signal to CPU2.Although
In CPU1 sides and CPU2 sides, the abnormal condition of quene state is different, but still can detect queue shape using same circuit
Whether state is abnormal, and corresponding interrupt signal is sent in exception.
Negate general of register and be arranged to non-zero value at message producer end, to detect whether queue is full, disappear in message
Fei Zheduan is arranged to 0, to detect whether queue is empty.Full 0 is arranged in CPU1 sides, the value for negating register 701, head is posted
Storage is with negating the XOR result of the phase XOR of register 701 or the value of head registers；In CPU2 sides, register 801 is negated
Value be arranged to up to 1, other full 0s, tail registers are that tail is posted with the XOR result for negating the phase XOR of register 801
The highest order of storage negates, other invariant positions.
As shown in figure 11, above-described head registers, tail registers, head_sync registers and tail_sync
Register may each comprise the flag bit that unrolls, and the flag bit that unrolls is a register bit.For example, queue includes 4 units,
Head registers need to indicate each unit with 2 bits, and in order to provide the flag bit that unrolls, head registers also need to a volume
Outer bit.The implication of flag bit of unrolling can be embodied by following two examples.For example, the head with the flag bit that unrolls is posted
When storage currency is 0 ' b011 (highest order is the flag bit that unrolls), head registers add the value of 1, head registers to be changed into 0 '
B100 (highest bit reversal, low 2 of instruction are unrolled).In another example queue includes 16 units, head registers need 4
Individual bit indicates each unit, and in order to provide the flag bit that unrolls, head registers also need to an extra bit, for example,
Head registers currency with the flag bit that unrolls is 0 ' b01111 (highest order is the flag bit that unrolls), and head registers add 1
When, the value of head registers is changed into 0 ' b10000 (highest bit reversal, low 4 of instruction are unrolled).
In one example, as shown in figure 12, head registers are 3 bits (including 1 bit unroll flag bit), negate and post
Storage 701 is 1 bit, and the flag bit that unrolls for negating register 701 and head registers is coupled to XOR circuit 702, its XOR
XOR result and the head registers that circuit 702 exports except after the flag bit that unrolls remaining 2 bit splice, splicing result with
Tail_sync registers (including the flag bit that unrolls) are compared (such as by comparison circuit 703).
In another example, as shown in figure 13, head registers are 5 bits (including 1 bit unroll flag bit), are negated
Register 701 is 5 bits, and it is significant to negate the only highest order of register 701, and low 4 all (do not change corresponding head for 0 after XOR
The value of register).Negate register 701 and be coupled to the input of XOR circuit 702 with head registers, negate register 701
XOR result with head registers is 5 bits, and the XOR result that XOR circuit 702 exports and the tail_sync of 5 bits are deposited
Device (including the flag bit that unrolls) is compared.
The associated exemplary of register 801 is negated referring to above-mentioned, is no longer repeated.
Embodiment 12
As shown in figure 14, when CPU1 is located at identical clock zone with CPU2, pointer synchronous circuit include head registers and
Tail registers, CPU1 and CPU2 can high speed access head registers (for example, CPU1 by local bus a bus week
Head registers are accessed in phase), CPU1 and CPU2 can high speed access tail registers (for example, CPU1 is existed by local bus
Head registers are accessed in one bus cycles).
CPU1 is renewable or reads head registers, and head registers only can be read in CPU2.Pass through head registers, CPU1
Queue head pointers are transmitted to CPU2.CPU2 is renewable or reads tail registers, and CPU1 only can be read tail registers, pass through
Tail registers, CPU2 transmit queue tail pointers to CPU1.
Alternatively, as shown in figure 15, pointer synchronous circuit also includes Status3 and Status4, wherein, Status3 passes through
The value for comparing head registers and tail registers determines whether quene state is empty, and when quene state is non-NULL, to
CPU1 sends interrupt signal, to indicate to have pending message in CPU1 queues.Status4 by compare head registers with
Tail registers determine whether quene state is full, and when quene state is full, interrupt signal are sent to CPU2, with instruction
CPU2 queues are full, should not write message into queue again.CPU1 and CPU2 can inquire about corresponding quene state instruction electricity at any time
Road, confirm quene state, and make corresponding operation.
Embodiment 13
In an embodiment according to the present invention, CPU1 and CPU2 carries out message exchange.CPU2 according to the present invention by implementing
The pointer synchronous circuit of example obtains message pointer to CPU1 new information pointers, CPU1 from pointer synchronous circuit, and according to message
Pointer obtains message from main storage.
Exemplarily, CPU2 generations will be sent to CPU1 one or more message.CPU2 writes one or more message
Enter message caching, and immediately return to, memory (for example, main storage) is written into without waiting for the arrival of news.Message caching record
The message content and core address of write-in, and message is write into memory on backstage.Now CPU2 can perform other operations.CPU2
Message is write with a brush dipped in Chinese ink memory by instruction message caching.If the message in message caching is all write memory, this behaviour
Make directly to return, CPU2 can continue other processing；If the message in message caching is not yet written into memory, CPU2 is hindered
Plug, until the message in message caching is all write memory.Message is organized as queue in memory.
In another example, memory that CPU2 writes direct message where message queue.And CPU1 is directly from depositing
Message is obtained in reservoir.
After message is write the message queue in memory by CPU2, the tail pointer of CPU2 also new information queues.In basis
In embodiments of the invention, CPU2 is write the queue tail pointer of renewal by pointer synchronous circuit according to embodiments of the present invention
Enter tail registers.CPU1 indicates message queue non-NULL in response to tail_sync registers and head registers, from message queue
Middle acquisition message, team's head pointer of new information queue, and team's head pointer of renewal is write into head registers.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
- A kind of 1. pointer synchronous circuit, it is characterised in that the first pointer including belonging to the first clock zone with first processor Register and second processor belong to second pointer register and the first synchronous circuit in second clock domain；Wherein, first refers to Pointer value in pin register may be in response to first processor and be updated, and the first synchronous circuit is by the first pointer register Pointer value is write in the second pointer register, and the pointer value in the second pointer register can be read by second processor.
- 2. pointer synchronous circuit according to claim 1, it is characterised in that the first synchronous circuit includes the synchronous electricity of the first son Road and the second sub- synchronous circuit；Wherein, the first pointer register is updated in response to first processor, the first sub- synchronous circuit is to the Two sub- synchronous circuits send the instruction of synchronization request；The finger of the synchronization request sent in response to the first sub- synchronous circuit received Showing, the second sub- synchronous circuit sends the instruction for receiving synchronization request to the first sub- synchronous circuit, and by the first pointer register Pointer value write the second pointer register in.
- 3. the pointer synchronous circuit according to one of claim 1-2, it is characterised in that also indicate electricity including first state Pointer value in first pointer register is write the second pointer register by road, first state indicating circuit in the first synchronous circuit Period is in busy condition, and remaining is in idle condition；Wherein, when first state indicating circuit is in idle condition, subsequently The operation that first processor updates the first pointer register is performed；When first state indicating circuit is in busy condition, after The operation that continuous first processor updates the first pointer register is blocked.
- 4. the pointer synchronous circuit according to Claims 2 or 3, it is characterised in that in response to the synchronous electricity of the second son received What road was sent receives the instruction of synchronization request, and the first sub- synchronous circuit sends the instruction synchronously completed to the second sub- synchronous circuit； The instruction synchronously completed sent in response to the first sub- synchronous circuit received, the second sub- synchronous circuit is to the first sub- synchronous circuit Indicate to receive the instruction synchronously completed；The instruction for receiving synchronization request indicated in response to the second sub- synchronous circuit received, the First state indicating circuit is arranged to idle condition by one sub- synchronous circuit.
- 5. the pointer synchronous circuit according to Claims 2 or 3, it is characterised in that in response to the synchronous electricity of the second son received What road was sent receives the instruction of synchronization request, and the first sub- synchronous circuit sends the instruction synchronously completed to the second sub- synchronous circuit； The instruction synchronously completed sent in response to the first sub- synchronous circuit received, the second sub- synchronous circuit is to the first sub- synchronous circuit Indicate to receive the instruction synchronously completed；In response to the instruction synchronously completed that receives of the second sub- synchronous circuit instruction for receiving, the First state indicating circuit is arranged to idle condition by one sub- synchronous circuit.
- 6. the pointer synchronous circuit according to any one of Claims 1 to 5, it is characterised in that also include and first processor Belong to the 3rd pointer register of the first clock zone, the 4th pointer register in second clock domain is belonged to second processor With the second synchronous circuit；Wherein, the pointer value in the 4th pointer register may be in response to second processor and be updated, and second is same Step circuit writes the pointer value in the 4th pointer register in the 3rd pointer register, the pointer value in the 3rd pointer register It can be read by first processor.
- 7. pointer synchronous circuit according to claim 6, it is characterised in that also include the first team for belonging to the first clock zone Row condition indication circuit, and belong to the second queue condition indication circuit in second clock domain；Wherein, first queue state instruction Circuit determines whether quene state is normal by comparing the value of the first pointer register and the 3rd pointer register, and in queue shape During state exception, interrupt signal is sent to first processor；Second queue condition indication circuit passes through the second pointer register and Four pointer registers determine whether quene state is normal, and in quene state exception, interrupt signal is sent to second processor.
- A kind of 8. pointer synchronous method, it is characterised in that including：The pointer value in the first pointer register is updated in response to first processor, by first state indicating circuit at first Manage device instruction busy condition；Pointer value in first pointer register is write in the second pointer register；AndIdle condition is indicated to first processor by first state indicating circuit；Wherein, the first pointer register and first processor belong to the first clock zone, the second pointer register and second processing Device belongs to the second clock domain different from the first clock zone.
- 9. a kind of pointer synchronous circuit, it is characterised in that including belonging to same clock with first processor and second processor 5th pointer register in domain and the 6th pointer register；Wherein, the pointer value in the 5th pointer register may be in response to first Processor is updated, and can be read by second processor；Pointer value in 6th pointer register may be in response to second processing Device is updated, and can be read by first processor.
- A kind of 10. message switching method, it is characterised in that including：One or more message are generated, the queue tail of the queue that one or more message are write in memory；The address of queue tail of the queue is write to the first pointer register of pointer synchronous circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610473495.9A CN107544618B (en) | 2016-06-24 | 2016-06-24 | Pointer synchronization circuit and method, message exchange device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610473495.9A CN107544618B (en) | 2016-06-24 | 2016-06-24 | Pointer synchronization circuit and method, message exchange device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107544618A true CN107544618A (en) | 2018-01-05 |
| CN107544618B CN107544618B (en) | 2021-12-28 |
Family
ID=60960991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610473495.9A Active CN107544618B (en) | 2016-06-24 | 2016-06-24 | Pointer synchronization circuit and method, message exchange device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107544618B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4926414A (en) * | 1987-06-12 | 1990-05-15 | International Business Machines Corporation | Control point session synchronization in a network |
| CN102065569A (en) * | 2009-11-17 | 2011-05-18 | 中国科学院微电子研究所 | An Ethernet MAC Sublayer Controller Suitable for WLAN |
-
2016
- 2016-06-24 CN CN201610473495.9A patent/CN107544618B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4926414A (en) * | 1987-06-12 | 1990-05-15 | International Business Machines Corporation | Control point session synchronization in a network |
| CN102065569A (en) * | 2009-11-17 | 2011-05-18 | 中国科学院微电子研究所 | An Ethernet MAC Sublayer Controller Suitable for WLAN |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107544618B (en) | 2021-12-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102197384B (en) | Method and system for improving serial port memory communication latency and reliability | |
| CN101477504B (en) | System and method for transmission of data | |
| US8762616B2 (en) | Bus system and bridge circuit connecting bus system and connection apparatus | |
| CN102567255B (en) | Have and monitor the invalid data handling system of request selecting and be used for its method | |
| US20090187681A1 (en) | Buffer controller and management method thereof | |
| US6154796A (en) | Apparatus and method in a network interface device for storing receiving frame status in a holding register | |
| CN101206614B (en) | Simulator for simulating register with specific function | |
| CN104778025B (en) | Circuit structure of first-in first-out memory based on random access memory | |
| US4174537A (en) | Time-shared, multi-phase memory accessing system having automatically updatable error logging means | |
| CN108401467A (en) | The control method of storage device, chip and storage device | |
| US6061768A (en) | Apparatus and method in a network interface device for storing tracking information indicating stored data status between contending memory controllers | |
| CN102331922B (en) | Data comparison apparatus, cache apparatus comprising it, and control method thereof | |
| CN101825997A (en) | Asynchronous first-in first-out storage | |
| CN109388344A (en) | A kind of dual-port SRAM access control system and method for intersecting addressing based on bandwidth expansion | |
| CN101493759B (en) | Address control method of random capacity asynchronous first-in/first-out memory | |
| CN100471175C (en) | Method for message storage and forwarding and message storage and forwarding circuit | |
| CN107544618A (en) | Pointer synchronous circuit and method, message switching apparatus and method | |
| CN109285580A (en) | Data prediction device, method and asynchronous double-end randon access memory system | |
| EP1016966A2 (en) | Method and protocol for inter-process communication | |
| CN116051279A (en) | Information updating device, method, equipment and medium of wind control system | |
| CN109426562A (en) | Priority weighted robin scheduling device | |
| CN111126584A (en) | Data write-back system | |
| US12093124B2 (en) | Multi-level signal reception | |
| CN104679667A (en) | Efficient sampling port buffer management method | |
| CN109800200A (en) | A kind of data communications method, originating end, responder and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20180426 Address after: 361000 Xiamen, Fujian, China (Fujian) free trade trial area Xiamen area (bonded port area), South Sea Road two Road 45, 4 Building 03 unit F0100 Applicant after: Xiamen Xin Yi news Technology Co., Ltd. Address before: 100089 building 32, Chuang Zhong Road, Haidian District, Beijing 32-1-1-167 Applicant before: Beijing core technology Co., Ltd. |
|
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 361000 Xiamen, Fujian, China (Fujian) free trade trial area Xiamen area (bonded port area), South Sea Road two Road 45, 4 Building 03 unit F0100 Applicant after: Xiamen Jingcun Semiconductor Technology Co., Ltd Address before: 361000 Xiamen, Fujian, China (Fujian) free trade trial area Xiamen area (bonded port area), South Sea Road two Road 45, 4 Building 03 unit F0100 Applicant before: XIAMEN KINGBLAZE TECHNOLOGY Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |