CN107526894A - A kind of more/many-core framework TriBA CMPs placement-and-routing scheme tMesh - Google Patents

Abstract

The invention relates to a layout and wiring scheme tMesh of multi/many-core architecture TriBA-CMPs, belonging to the technical fields of computer architecture, high-performance computing, and multi-/many-core processor architecture. Based on the three-level recursive scalability of the TriBA-CMPs base, the present invention proposes a tMesh layout and wiring scheme: the f-layer tMesh consists of three f-1-layer tMesh located in the upper left, lower left, and lower right, and one L _f in the upper right area ₊₁ -level Cache unit layout implementation; when interconnecting 3 f‑1 layer tMesh to implement f layer tMesh wiring, the upper left and lower left, lower left and lower right, upper left and lower right are respectively vertically, horizontally, vertically and then horizontally or Connect horizontally and then vertically; when the L _f+1 level Cache unit is interconnected with three L _f level Cache units located in the upper left, lower right, and lower left f-1 layers of tMesh, respectively, use horizontal, vertical, first vertical and then Connected horizontally or horizontally and then vertically. Compared with the traditional 2D-mesh-Tile, the present invention not only has the advantages of simple layout and wiring and is easy to implement in the final process, but also has good hierarchical scalability.

Description

A layout and routing scheme tMesh for TriBA-CMPs with multi-core/many-core architecture

technical field

The present invention relates to a layout and wiring scheme of multi/many-core architecture TriBA-CMPs, in particular to adopting the tMesh scheme to realize the layout and wiring of TriBA-CMPs, belonging to the technical field of computer architecture, high-performance computing, and multi-/many-core processor architecture .

Background technique

Multi-core processors have become the research and development direction of high-performance processor architecture, and the on-chip communication architecture has an extremely important impact on the performance of multi-core processors. At present, 2D mesh is widely used as the mainstream network-on-chip (hereinafter referred to as NoC) architecture. The topology of 2D mesh network is shown in Figure 1. This structure is the simplest and most intuitive topology, and it has the same intuitive, simple and efficient Tile Layout and routing scheme (hereinafter referred to as 2D-mesh-Tile).

Tile is the basic layout and routing unit, and the shape (square or rectangle), size, and internal structure of all Tile are exactly the same. There is a router R inside the Tile for interconnection and communication with the other four adjacent Tiles and the local Core (core), and the Core generally includes a processing core (processor in a general sense) and a local private L1Cache. However, the 2Dmesh topology is non-recursive, so the sharing method of the on-chip distributed shared storage system using this topology can only be shared globally. Therefore, as the number of cores increases, the delay in accessing remote shared storage nodes will increase sharply. Therefore, as a storage network, 2D mesh has poor scalability.

Although 2D mesh has many insurmountable shortcomings, the tile layout itself in its hardware implementation is efficient and concise, and no previous structure has been able to provide a layout with comparable performance and efficiency. Therefore, 2D mesh has been applied in the industry, and 2D-mesh-Tile has become the actual standard to measure whether a NoC is available.

TriBA-CMPs is a multi/many-core processor architecture, which consists of its unique on-chip network TriBA-NoC and some important peripheral interface protocols. TriBA-NoC contains two independent heterogeneous on-chip networks (NoC): TriBA-cNoC and TriBA-mNoC, which form between cores, on-chip Cache units (or storage units), and between cores and Cache units The basic communication infrastructure (infrastructure). Although in principle, the communication between various nodes may be completed using the above two NoCs or their combination, but TriBA-cNoC is used for inter-core communication, and TriBA-mNoC is used to construct hierarchical distributed on-chip Cache/storage network.

The TriBA-CMPs architecture can solve the problems of the aforementioned 2D mesh topology to a considerable extent, and the present invention provides a layout and wiring scheme tMesh with performance and efficiency equivalent to 2D-mesh-Tile, thereby ensuring the TriBA-CMP feasibility.

1. Introduction to TriBA-cNoC

This NoC tends to be used for inter-core communication, and adopts a basic three-layer recursive topology, such as the 1-layer, 2-layer, and 3-layer TriBA-cNoC topology shown in Figure 2. The F-layer TriBA-cNoC includes 3 ^F nodes in total, and its network diameter (the distance between the tips of the triangular regions in Figure 2, that is, the side length) is 2 ^F -1; the topology of the network is marked by TC ^{F. TCF} can be constructed recursively as follows.

According to the construction method of ^TCF in Algorithm 1, the precise graph theory definition of ^TCF can be obtained as Definition 1.

Definition 1: TC ^F = {V(TC ^F ), E(TC ^F )}, where the set of vertices (nodes) and the set of edges are respectively defined as follows

where the set of literals 1, 3, and 2 is labeled as means x _F ... x _f+1 ,

a ^f-1 represents a text string composed of (f-1) words a, N is a set of natural numbers, For example: when F=2, V(TC ² )={11, 12, 13, 21, 22, 23, 31, 32, 33}, and

2. Introduction to TriBA-mNoC

The on-chip network is used to share the on-chip memory (or Cache) with hierarchical grouping, and adopts a common trident tree topology, as shown in Figure 3 with 4 layers of TriBA-mNoC. F-layer TriBA-CMPs can theoretically have up to F+1 layers of on-chip storage structures, but in practice, the significance of about five or more levels is not obvious (see the special statement in the introduction to TriBA-NoC later), so higher levels are usually There is no more on-chip storage, and the corresponding place-and-route area can be used for any other purpose. For example, other functional components often found in processors, and even coprocessors and computing accelerators. The topology of this network is marked with ^TMF . ^TMF can be constructed as follows.

According to the above construction of ^TMF , the precise graph theory definition of ^TMF can be obtained as Definition 2.

Definition 2: TM ^F = {V(TM ^F ), E(TM ^F )}, where the set of vertices (nodes) and the set of edges are respectively defined as follows

Among them, 0 just represents a placeholder, although not necessary, but meaningful for simplifying hardware implementation;

Other description methods are the same as those used in the definition of ^TCF .

For example, when F=4, under the above definition, the entire network and its node codes are shown in Figure 3 . Each node is drawn in the form of a three-dimensional diagram, just for the convenience of understanding the hierarchical relationship. In the specific implementation of TriBA-mNoC (that is, in tMesh), they are located on the same plane.

It is specifically stated here that the storage scale (corresponding to its module area) of the nodes at the same layer of TriBA-mNoC is the same, and the storage scales of nodes at different levels are different. The area occupied by these nodes in tMesh is called Cache Unit (Cache Unit), hereinafter referred to as CU. The node of the fth layer is called L _f CU, and L _f Cache is the collective name of all nodes of the f level.

3. Introduction to TriBA-NoC

TriBA-NoC is the fusion of the above-mentioned TriBA-cNoC and TriBA-mNoC in the multi-core architecture TriBA-CMPs, or a general term for both of them appearing in a TriBA-CMPs at the same time. The non-dashed line in Figure 3 shows the topology of TriBA-mNoC. Since the first-layer nodes are located in the kernel, these nodes also represent the kernel (the coding rules are also compatible), so they and the dotted line in the figure just constitute the TriBA-mNoC cNoC, so Figure 3 can also be regarded as a schematic diagram of the topology after the fusion of TriBA-cNoC and TriBA-mNoC (i.e. TriBA-NoC). Of course, this figure is a 3-layer TriBA-CMPs, but any Topology of the on-chip fusion network TriBA-NoC with layers of TriBA-CMPs.

Special statement here: the network topology given in the present invention is a complete graph, that is, the TriBA-mNoC of the F-layer many-core TriBA-CMPs is from the first layer to the highest layer F+1. This is a technical practice, mainly for mathematics The rigor of the problem described above, the edge is only a logical relationship (link). When actually using the multi-core architecture TriBA-CMPs, the complete graph may not be used. For example, a 5-layer TriBA-CMPs architecture many-core memory may only have 4 layers of Cache instead of 6 layers of the complete graph; in addition, the edge of TriBA-CMPs (or link) may also be implemented using one physical channel, or multiple physical or logical channels, or multiple virtual channels, and each physical channel may also have a different number of signal lines.

4. Placement and routing of TriBA-CMPs

TriBA-CMPs is a distributed computing-oriented software and hardware architecture proposed by our research group with obvious original features. At present, although there are reports on the related research of non-members of the research group at home and abroad, almost all of them are about the routing and topology of TriBA-cNoC. Far from reaching the level of physical realization, there is no related research on TriBA-CMPs layout and routing.

This research group has given a "Y" layout and routing scheme before (Licheng Xue, Weixing Ji, QiZuo and Yang Zhang. Floorplanning Exploration and Performance Evaluation of a New Network-on-Chip[C]. Design Automation&Test in Europe(DATE) . Grenoble, France, IEEE Computer Society, 2011:625-630.), the layout and wiring method is a non-Manhattan method, which is contrary to the existing technology and is not conducive to wiring. Based on this, the present invention adopts the Manhattan wiring method, and proposes a layout and wiring scheme tMesh of TriBA-CMPs with multiple/many-core architectures.

Contents of the invention

The purpose of the present invention is to solve the problem that adopting "Y" type layout and wiring in TriBA-CMPs is not conducive to process realization, and proposes a layout and wiring scheme tMesh of TriBA-CMPs with multi/many-core architecture.

The object of the present invention is achieved through the following technical solutions.

A placement and routing scheme tMesh of TriBA-CMPs with many/many-core architectures, including an F-layer tMesh layout method and a tMesh routing method, wherein F is a natural number;

The tMesh layout method includes the following steps:

Step 1: Layout 1 layer tMesh: This layer includes 3 coreTiles and 1 Cache unit, where coreTile means Tile for kernel layout, Cache means cache memory, and 1 Cache unit in this layer includes 1 cacheTile, cacheTile means Tile for Cache unit; and:

The three coreTiles are respectively located at the upper left, lower left and lower right positions, and each coreTile corresponds to the node x ₁ ∈ {3,1,2} of the original TC ¹ , that is, the numbers are 3, 1, and 2 respectively; mark the Tile type as C;

1 cacheTile is located in the upper right area, constituting the L2 level Cache unit, and the cacheTile of this level is marked as L ₂ ;

If F=1, exit; otherwise, let f=2;

Step 2: Layout f layer tMesh: This layer includes 3 f-1 layer tMesh and 1 Cache unit, and the Cache unit in this layer includes 4 ^f-1 cacheTile; and:

The three f-1 layer tMesh are located in the upper left, lower left and lower right respectively, and the numbers in TC ^f are respectively with Each f-1 layer tMesh corresponds to the node of the original TC ^f-1 where x _i ∈ {3,1,2}, 1≤i≤f-1;

One Cache unit is located in the upper right area, forming L _f+1 level Cache unit, marking all cacheTiles of this level as L _f+1 ;

let f=f+1;

If f=F+1, exit; otherwise, return to step 2 to lay out the next layer of tMesh;

The tMesh wiring method includes TriBA-cNoC wiring and TriBA-mNoC wiring. The specific method steps are as follows:

Step 1: Routing 1 Layer tMesh:

1-layer TriBA-cNoC wiring: routers corresponding to coreTile numbers 3 and 1 (ie, upper left and lower left cores) are directly connected through vertical wiring; routers corresponding to coreTiles numbered 1 and 2 (ie, lower left and lower right cores) are connected through horizontal The wiring is directly connected; the routers corresponding to the coreTile numbered 2 and 3 (that is, the lower right and upper left cores) are connected through the first horizontal and then vertical or the first vertical and then horizontal (choose one of the two methods, and it is recommended that the corresponding selection remains unchanged in subsequent wiring) .

Layer 1 TriBA-mNoC wiring: Horizontal wiring, directly connecting the interface provided by the upper left core router and L2-level Cache unit; vertical wiring, directly connecting the interface provided by the lower right core router and L2-level Cache unit; first horizontal and then vertical or first vertical and then Choose one of the two horizontal methods (it is recommended that the corresponding choice remains unchanged in the subsequent wiring) to connect the lower left kernel router to the interface provided by the L2-level Cache unit.

If F=1, exit; otherwise, let f=2;

Step 2: Routing the f-layer tMesh:

Layer f TriBA-cNoC wiring: routers corresponding to coreTile numbers 31 ^f-1 and 13 ^f-1 are directly connected through vertical wiring; routers corresponding to coreTile numbers 12 ^f-1 and 21 ^f-1 are directly connected through horizontal wiring ; The routers corresponding to the coreTiles numbered 32 ^f-1 and 23 ^f-1 are connected through horizontal first and then vertical or first vertical and then horizontal (choose one of the two methods, and it is recommended that the corresponding selection remains unchanged in the subsequent wiring).

F-layer TriBA-mNoC wiring: the interface between the L _f level Cache unit of the f-1 layer tMesh on the upper left and the L _f+1 level Cache unit of the f-layer tMesh is connected through horizontal wiring; the L _f level of the lower right f-1 layer tMesh The interface between the Cache unit and the L _{f +1 level} Cache unit of the current f layer tMesh is connected through vertical wiring; Choose one of the two ways of first horizontal and then vertical or first vertical and then horizontal (it is recommended that the corresponding selection in the subsequent wiring remains unchanged) wiring connection.

let f=f+1;

If f=F+1, exit; otherwise, return to step 2 to wire the next layer tMesh.

Beneficial effect

The tMesh layout and wiring scheme proposed by the present invention adopts the Manhattan wiring method, which basically conforms to the characteristics of the factual industrial standard of 2D-mesh-Tile, and realizes the docking of TriBA-CMPs with the existing technology in the specific implementation, which is beneficial to the final process realization ; That is, in the field of multi/many-core processors, each Tile in 2D mesh is isomorphic, and the non-recursive nature of its topology makes storage generally shared globally. As the network scale grows, access to remote shared The storage delay will be significantly increased. Therefore, the problem of poor scalability is simple and easy to implement like 2D mesh. Specifically, the present invention has the following different characteristics compared with 2D-mesh:

The topology of the on-chip network implemented by 1 ^st is different. The coreTile class Tile and the cacheTile class Tile in tMesh are used to implement TriBA-cNoC and TriBA-mNoC respectively, and are respectively oriented to the layout of the base three-topology TC ^F and the tri-tree topology TM ^F , which realizes the fusion of two heterogeneous networks Layout and routing can better reflect the characteristics of different application requirements; while the layout between tiles of 2D mesh realizes the 2D mesh topology network, and it is always the fusion layout and routing of isomorphic networks when used in multi-layer networks. tMesh uses two heterogeneous networks to independently implement inter-core communication and storage system data transfer, which is conducive to improving inter-core communication bandwidth and reducing memory access latency.

2 ^st Tile types are different. Both use Tile as the basic unit of layout, but the difference is that the Tile in 2D mesh is identical (identical), and both are composed of the same processing core, L1Cache and router in the same way, that is, there is only one In the present invention, Tile is divided into several types. Although different types of Tile have the same shape and size, their functions, uses and structures are completely different. Among them, the type of Tile used for kernel layout is called coreTile in this paper. The F-layer TriBA-CMPs have a total of 3 ^F coreTiles; and the Tile used for Cache, which is collectively referred to as cacheTile in this paper, has a total of F types (excluding L1 Cache), and the f-th layer TriBA-CMPs (including 3 ^f coreTiles) correspond to the base three groups The number of tiles included in the shared cache unit is 4 ^f-1 , which means that the larger the number of layers, the larger the number of cores contained, and the larger the capacity of the corresponding shared cache unit, which can effectively allocate cache space between different layers , improve storage space utilization efficiency. However, the invention in this paper only focuses on the occupancy (layout, in units of Tile) of different levels of Cache, and the routing rules (wiring) between them;

3 ^rd In principle, there are many different layout and routing schemes for TriBA-NoC in physical implementation, and tMesh gives a specific layout scheme for TriBA-NoC. This scheme uses various cacheTile and coreTile for layout according to specific rules. The wiring area is filled to provide a layout efficiency and convenience comparable to 2D-mesh-Tile; that is, it contains multiple types of Tile, and the arrangement of different types of Tile meets specific rules, which is different from 2D -mesh-Tile is essentially different;

4th In principle, even if the layout scheme is determined during the physical implementation of ^TriBA -NoC, there are also many different wiring schemes. tMesh provides a specific layout scheme for its specific layout scheme. Due to the different topologies implemented, the wiring of tMesh is naturally impossible to be the same as that of 2D-mesh-Tile;

Description of drawings

Figure 1 is a schematic diagram of 2D mesh and its Tile layout scheme (ie 2D-mesh-Tile);

Figure 2 is a schematic diagram of the topology TC ^F of the F-layer TriBA-cNoC (taking the 1, 2, and 3-layer network as an example);

Figure 3 is the topology TM ^F of the F-layer TriBA-mNoC (taking a 4-layer network as an example, its root node code o ^4-1 = ooo. In addition, if the first-layer nodes are identified as the kernel, then this figure is the corresponding TriBA -Schematic diagram of the topology of the NoC;

Figure 4 is a schematic diagram of the tMesh construction method (only 1, 2, 3 layers, that is, 3, 9, 27 cores, multi-core as an example);

(a) Schematic diagram of tMesh layout of 1-layer TriBA-NoC;

(b) Schematic diagram of the tMesh layout of the 2-layer TriBA-NoC;

(c) Schematic diagram of the tMesh layout of the 3-layer TriBA-NoC;

Fig. 5 is a schematic diagram of first horizontal and then vertical and first vertical and then horizontal in wiring;

6 is a horizontal (vertical) schematic diagram of interconnection between TriBA-mNoC nodes in wiring;

Fig. 7 is a schematic diagram of an equivalent application mode of tMesh.

detailed description

The content of the present invention will be described in detail below in conjunction with the accompanying drawings.

1. Layout scheme in tMesh

According to the construction method of TriBA-cNoC, the characteristics of Tile and vertical and horizontal wiring, the tMesh layout (referred to as F-layer tMesh) design of F-layer TriBA-NoC is hereby given:

According to the above process, the precise mathematical definition of the tMesh layout scheme of F-layer TriBA-CMPs is easily obtained

in, Represents the collection of all Tile contained in the f-layer processor located at (x, y); Represents a single-element collection composed of Tile located at (x, y), and the Tile is used for L _f Cache; C _{(x, y)} is the Tile located at C _{(x, y)} , which is used for the kernel. According to Figure 4, it can be deduced that the maximum distance between L _f Cache and L _f+1 Cache is twice the length of the Tile side, and the connection method is shown in Figure 4 in detail. In addition, the above formula is a recursive formula, and it is not easy to see the result directly, but if it is fully expanded, it will be very complicated. Therefore, the following simple C++ program is given to check the distribution of tiles:

In the above program, according to the above-mentioned recursive formula, the Tile type and distribution in the 4-layer tMesh are realized in a recursive manner. The function void TS(int f, int deltaX=0, int deltaY=0) in the program is a recursive function, which represents the Tile distribution of the f-layer tMesh, where deltaX and deltaY represent the origin coordinates of the tMesh, that is, the original origin is (1 , 1) The layout is translated vertically by deltaY and horizontally by deltaX.

If you want to get the layout of n-layer tMesh, change the statement TS(4,0,0) in main() to TS(n,0,0), and change the initialization value of the global variable LEN to 2 ⁿ . The output of the program in the console window is similar to the following table

Using the above layout scheme, the F-layer tMesh corresponds to the F-layer TriBA-CMPs, which contains 3 ^F cores, up to F+1 layer Cache, and the area of the f (2≤F) level Cache unit is equivalent to 2 ^{f- 1} × 2 ^f-1 tiles, whose shape is geometrically similar to the tile shape.

2. Wiring scheme in tMesh

Usually, tMesh routing can be performed at any time (that is, connecting the tiles according to certain rules), but this way of describing the routing algorithm is confusing. Here we will complete the corresponding level of routing in each step of the layout, such as Algorithm 4.

Because what the present invention provides is a layout and wiring scheme when an abstract topology structure is physically realized on a chip network. Because the topology describes the common abstract features of a class of networks, no matter what the topology is, it will be deleted in specific applications. The same is true for the tMesh of the present invention. Here, the following specific implementation methods are specially given to show its specific application features, but the present invention is not limited to these specific application methods:

Example 1:

Claims related to the wiring of tMesh include the options of first horizontal and then vertical or first vertical and then horizontal. Figure 5 illustrates the features of these two options with 3-core (ie, 1-layer) tMesh wiring. In this figure, when the upper left and lower right coreTiles of TriBA- _cNoC are interconnected, they can be wired horizontally and then vertically or vertically and then horizontally; Route in portrait or portrait then landscape.

Example 2:

Because TriBA-mNoC may have multiple input and output ports when it is actually implemented, its horizontal (vertical) connections may have multiple connections as shown in Figure 6. In the TriBA-mNoC wiring of layer f tMesh, when the L _f level Cache units in the upper left and lower right f-1 layer tMesh are respectively connected to the L _f+1 level Cache in the f layer tMesh, there are 2 ^f in the L _f level Cache units ^-2 cacheTiles are adjacent to L _f+1 level Cache horizontally and vertically respectively, so they can be connected through 2 ^f-2 horizontal and vertical wirings respectively, or can be connected through any one of 2 ^f-2 horizontal and vertical wirings or Multiple lines are connected by wiring; when the L _f level Cache unit in the lower left f-1 layer tMesh is connected to the L _f+1 level Cache in the f layer tMesh, the cacheTile and the L _{f +1} level Cache unit in the upper right corner of the L f level Cache unit The cacheTile in the lower right corner is connected to achieve, and the specific wiring can be carried out horizontally and then vertically or first vertically and then horizontally. Figure 6 shows the wiring of TriBA-mNoC in tMesh when f=3.

Example 3:

As shown in Figure 7, tMesh can be applied after horizontal or vertical reflection and rotation at any angle to meet different application requirements.

The specific description above further elaborates the purpose, technical solution and beneficial effect of the invention. It should be understood that the above description is only a specific embodiment of the present invention and is not used to limit the protection of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (4)

1. A layout and wiring scheme tMesh of a multi/many-core architecture TriBA-CMPs is characterized in that: the method comprises an F layer tMesh layout method and a tMesh wiring method, wherein F is a natural number;

the tMesh layout method comprises the following steps:

step 1: layout 1 layer tMesh: the layer comprises 3 coreTile and 1Cache unit, wherein the coreTile represents the Tile used for kernel layout, the Cache represents a Cache memory, and the 1Cache unit of the layer comprises 1 cacheTile which represents the Tile used for the Cache unit; and:

3 coreTile are respectively positioned at the upper left, lower left and lower right positions, and each coreTile corresponds to the original TC¹Node x of₁∈ {3,1,2}, i.e. the numbers are 3,1 and 2 respectively;

1 cacheTile is positioned in the upper right area and forms an L2-level Cache unit, and the cacheTile marking the level is L₂；

If F is 1, quitting; otherwise, let f be 2;

step 2: layout f layer tMesh: the layer comprises 3 f-1 layers of tMesh and 1Cache unit, and the Cache unit of the layer comprises 4^f-1A cacheTile; and:

the 3 f-1 layers of tMesh are respectively positioned at the upper left, lower left and lower right positions at TC^fMiddle numbers are respectivelyAndeach f-1 layer of tMesh corresponds to an original TC^f-1Node (a) ofWherein x_i∈{3,1,2}，1≤i≤f-1；

1Cache unit is positioned in the upper right region to form L_f+1A level Cache unit for marking all cacheTile of the level as L_f+1；

Let f be f + 1;

if F is F +1, quitting; otherwise, returning to the step 2 to lay out the next layer of tMesh;

the tMesh wiring method comprises TriBA-cNoC wiring and TriBA-mNoC wiring, and comprises the following specific steps:

step 1: wire 1 layer tMesh:

1-layer TriBA-cNoC wiring: the router with the numbers of 3 and 1, namely the router corresponding to the upper left and lower left cores, is directly connected through longitudinal wiring; the router cores are numbered 1 and 2, namely the routers corresponding to the lower left and lower right inner cores are directly connected through transverse wiring; the routers corresponding to coreTile, numbered 2 and 3, i.e., the lower right and upper left cores, are connected by one of two ways: firstly transverse and then longitudinal or firstly longitudinal and then transverse;

1-layer TriBA-mNOC wiring: the horizontal wiring is directly connected with the upper left core router and an interface provided by an L2-level Cache unit; the vertical wiring is directly connected with the lower right kernel router and an interface provided by an L2-level Cache unit; the lower left core router is connected with an interface provided by an L2 level Cache unit through wiring in one of the following two ways: firstly transverse and then longitudinal or firstly longitudinal and then transverse;

if F is 1, quitting; otherwise, let f be 2;

step 2: routing f layer tMesh:

f-layer TriBA-cNoC wiring: number 31^f-1And 13^f-1The routers corresponding to the coreTile are directly connected through longitudinal wiring; number 12^f-1And 21^f-1The routers corresponding to the coreTile are directly connected through transverse wiring; number 32^f-1And 23^f-1The router corresponding to the coreTile is connected by one of the following two ways: firstly transverse and then longitudinal or firstly longitudinal and then transverse;

f-layer TriBA-mNOC wiring: l of the top left f-1 layer tMesh_fL of level Cache unit and local f layer tMesh_f+1The interfaces of the level Cache units are connected through transverse wiring; bottom right f-1 layer tMesh L_fL of level Cache unit and local f layer tMesh_f+1Interfaces of the level Cache units are connected through longitudinal wiring; l of the bottom left f-1 layer tMesh_fL of level Cache unit and local f layer tMesh_f+1The interfaces of the level Cache units are connected through wiring in one of the following two ways: firstly transverse and then longitudinal or firstly longitudinal and then transverse;

let f be f + 1;

if F is F +1, quitting; otherwise, returning to step 2 to wire the next layer of tMesh.

2. The method of claim 1, wherein the routing is performed by one of the following two methods: the layout layer 1 adopts a certain connection mode, and then the wiring of the subsequent layer preferably adopts the same mode.

3. The method of claim 1, wherein the place-and-route scheme tMesh is the same after being rotated or mapped.

4. A place-and-route scheme tMesh for multi/many-core architecture tria-CMPs according to any of claims 1-3, wherein: tMesh routing method step 2L of the top left f-1 layer tMesh_fL of level Cache unit and local f layer tMesh_f+1The interfaces of the level Cache units are connected through transverse wiring and L of the lower-right f-1 layer tMesh_fL of level Cache unit and local f layer tMesh_f+1When interfaces of the level Cache units are connected through longitudinal wiring, L_fIn the stage Cache unit has 2^f-2A cacheTile and L_f+1The stages of Cache are respectively adjacent in the transverse direction and the longitudinal direction, so that the stages can respectively pass through 2^f-2The strips are wired transversely and longitudinally, or respectively 2^f-2Any one or more of the transverse and longitudinal wirings of the strip are wired to be connected.