CN107507815A - Welding pad structure and CSP method for packing - Google Patents

Abstract

The invention provides a kind of welding pad structure and CSP method for packing, since the metal level of the bottom, the distance of each the layer metal level to the chip edge is sequentially reduced, form step structure, when CSP is encapsulated, each layer metal level can be all exposed by etching, each layer metal level is set to be contacted with the second metal layer at back, considerably increase contact area, contact resistance is reduced, improves the reliability of encapsulation, and the encapsulation not necessarily forms silicon hole, technique is simple, reduces packaging cost.

Description

Pad structure and CSP packaging method

technical field

The invention relates to the technical field of semiconductors, in particular to a pad structure and a CSP packaging method.

Background technique

Currently, mainstream image sensor (Image Seneor) chip packaging technologies include: COB (Chip on Board) and CSP (Chip Scale Packaging). Among them, CSP refers to the chip packaging technology in which the chip size package and the chip core size are basically the same. The CSP core area and package area are about 1:1.1. Any package that meets this standard can be called CSP. Such a packaging form greatly improves the integration on the printed circuit board (PCB), reduces the volume and weight of the electronic device, and improves the performance of the product.

CSP packaging is to redistribute the pads (Pad) on the front of the CIS (CMOS image sensor) chip to the back of the chip in a certain way, thereby reducing the packaging area. At present, the method of redistributing the pads on the front side to the back side is mainly the through-silicon via method, that is, the through-silicon via is formed on the silicon substrate on the back of the chip by etching, and then the insulation treatment is performed and the hole is filled with metal. , and redistributed on the back side.

However, this packaging method has a complicated structure, a difficult process, and is expensive.

Contents of the invention

The object of the present invention is to provide a welding pad structure and a CSP packaging method, which do not need to form through-silicon vias, are simple in process, low in packaging cost, reduce contact resistance, and improve packaging reliability.

In order to achieve the above object, the present invention provides a pad structure, which is located in a chip and includes a substrate, a bottom metal layer on the substrate, a multilayer middle metal layer and a top metal layer in sequence, from Starting from the bottom metal layer, the distance from each metal layer to the edge of the chip decreases successively, forming a stepped structure.

Optionally, in the pad structure, starting from the underlying metal layer, the cross-sectional area of each metal layer increases sequentially.

Optionally, the pad structure further includes an interlayer dielectric layer located between the various metal layers and between the underlying metal layer and the substrate.

Optionally, the pad structure further includes a passivation layer covering the metal layer of the top layer and exposing a part of the metal layer of the top layer.

Optionally, in the pad structure, the metal layers of adjacent layers are connected through contact holes.

Optionally, in the pad structure, the pad structure is connected to the internal circuit structure of the chip through the underlying metal layer.

The present invention also provides a kind of CSP encapsulation method, and chip is encapsulated, and described chip comprises above-mentioned pad structure, and described encapsulation method comprises the following steps:

Step S01: Etching the back of the bonding pad structure on the edge of the chip to expose the stepped metal layers;

Step S02 : sequentially forming an insulating layer, a second metal layer and a protection layer on the back of the chip.

Optionally, in the CSP packaging method, in step S01, the substrate on the back of the pad structure is first etched to expose the interlayer dielectric layer; then the interlayer dielectric layer is etched , exposing each layer of metal layers in a stepped shape.

Optionally, in the CSP packaging method, a trench is formed on the substrate by etching, and the bottom of the trench stops on the interlayer dielectric layer at the bottom of the pad structure.

Optionally, in the CSP packaging method, in step S02, after the insulating layer is formed, each metal layer in the pad structure is exposed by photolithography and etching.

Optionally, in the CSP packaging method, in step S02, after forming the second metal layer, a patterned second metal layer is formed by photolithography and etching.

Optionally, in the CSP packaging method, in step S02, after forming the protective layer, photolithography and etching are performed to form at least one via hole on the protective layer.

Optionally, in the CSP packaging method, step S03 is further included, disposing solder balls in the through holes of the protection layer to be in contact with the second metal layer.

Compared with the prior art, in the bonding pad structure and CSP packaging method provided by the present invention, in the bonding pad structure, starting from the bottom metal layer, the distances from the metal layers of each layer to the edge of the chip are successively reduced , forming a ladder-like structure. When CSP is packaged, each layer of metal layer can be exposed by etching, so that each layer of metal layer can be in contact with the second metal layer on the back, which greatly increases the contact area and reduces the contact resistance. The reliability of the package is improved, and the package does not need to form through-silicon holes, the process is simple, and the package cost is reduced.

Description of drawings

FIG. 1 is a schematic structural diagram of a chip including a pad structure provided by Embodiment 1 of the present invention.

FIG. 2 is a flow chart of the CSP encapsulation method provided by Embodiment 2 of the present invention.

3 , 4 , 7 , 9 , 11 , and 13 are structural schematic diagrams of chips in each step of the CSP packaging method provided by Embodiment 2 of the present invention.

5, 6, 8, 10 and 12 are schematic diagrams of pad structures in each step of the CSP packaging method provided by Embodiment 2 of the present invention.

detailed description

In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

Secondly, the present invention is described in detail by means of schematic diagrams. When describing the examples of the present invention in detail, for the convenience of illustration, the schematic diagrams are not partially enlarged according to the general scale, which should not be used as a limitation of the present invention.

The core idea of the present invention is that, in the bonding pad structure, starting from the bottom metal layer, the distances from the metal layers of each layer to the edge of the chip are successively reduced to form a stepped structure. During CSP packaging, by engraving Corrosion can expose each layer of metal layers, so that each layer of metal layers can be in contact with the second metal layer on the back, greatly increasing the contact area, reducing contact resistance, improving the reliability of the package, and the package does not need to be formed Through-silicon vias, the process is simple, and the packaging cost is reduced.

[Example 1]

The present invention proposes a bonding pad structure, please refer to FIG. 1 , which is a schematic diagram of a chip structure including a bonding pad structure provided by an embodiment of the present invention. The chip 10 includes a pad structure 10a and an internal circuit structure 10b, the pad structure 10a is located on the edge of the chip 10, the pad structure 10a includes a substrate 11, and the pad structure 10a located on the substrate 11 in turn The metal layer M1 of the bottom layer, the metal layer in the middle of multiple layers (only one middle metal layer M2 is shown in FIG. 1 ) and the metal layer M3 of the top layer, starting from the metal layer M1 of the bottom layer, the metal layers of each layer The distances from the layers to the edge AA' of the chip decrease successively, forming a stepped structure.

The pad structure 10a also includes an interlayer dielectric layer 12 and a passivation layer 13, the interlayer dielectric layer 12 is located between each metal layer and between the underlying metal layer M1 and the substrate 11, the The passivation layer 13 covers the top metal layer M3, and the passivation layer 13 exposes a part of the upper surface of the top metal layer M3. A contact hole 14 is formed on the interlayer dielectric layer 12 between each metal layer, and the contact hole 14 is filled with a metal material, and the adjacent metal layers are connected through the contact hole 14 . Moreover, the pad structure 10a is connected to the internal circuit structure 10b through the underlying metal layer M1.

The substrate 11 may be a silicon substrate, such as one of single crystal silicon, polycrystalline silicon or amorphous silicon, or silicon on insulator (Silicon On Insulator, SOI), or a silicon germanium compound. In this embodiment, the substrate 11 is a silicon substrate. It should be noted that semiconductor structures such as gate, source and drain have been formed on the substrate 11 in the internal circuit structure 10b, and the semiconductor structure can be electrically connected to the outside through the metal interconnection structure and the pad structure, so that Realize various functions of the device. Multiple metal layers include, but are not limited to, aluminum or copper materials. The material of the interlayer dielectric layer 12 and the passivation layer 13 can be silicon oxide, silicon nitride, silicon oxynitride and the like. In this embodiment, the interlayer dielectric layer 12 and the passivation layer 13 are silicon oxide.

It should be noted that, in the above-mentioned welding structure provided by the embodiment of the present invention, the number of layers of the metal layer is three layers. In a specific embodiment, the number of layers of the metal layer in the internal circuit structure 10b may be determined according to the actual situation. etc. to determine the number of metal layers in the pad structure 10a. Moreover, since generally, the pad structure 10a and the top structure of the internal circuit structure 10b are formed in the same process, the number of metal layers of the pad structure 10a is the same as that required in the internal circuit structure 10b. The number of layers of the metal layer is the same.

Starting from the bottom metal layer M1, the distances from each metal layer to the edge AA' of the chip 10 decrease successively to form a stepped structure. Preferably, the areas of the metal layers of each layer increase successively. The edge of the pad structure 10a away from the internal circuit structure 10b forms a stepped structure, and the substrate 11 and the interlayer dielectric layer 12 are respectively etched once from the bottom of the chip 10 during the subsequent packaging process. , all the metal layers can be exposed, so that each metal layer can be in contact with the subsequent metal layer, which greatly increases the contact area, reduces the contact resistance, and improves the reliability of the package.

It should be noted that the above-mentioned pad structure provided by the embodiments of the present invention can be applied to any device provided with a pad structure, and is especially suitable for a device that requires relatively high contact resistance.

[Example 2]

The present invention provides a CSP packaging method for packaging a chip, and the pad structure in the chip adopts the pad structure described in Embodiment 1. Fig. 2 is the process flowchart of the CSP encapsulation method in the second embodiment of the present invention, as shown in Fig. 2, the present invention proposes a kind of CSP encapsulation method, comprises the following steps:

Step S01: Etching the back of the bonding pad structure on the edge of the chip to expose the stepped metal layers;

Step S02 : sequentially forming an insulating layer, a second metal layer and a protection layer on the back of the chip.

Figures 3, 4, 7, 9, 11, and 13 are schematic structural views of chips in each step of the CSP packaging method provided by Embodiment 2 of the present invention, and Figures 5, 6, 8, 10, and 12 are provided by Embodiment 2 of the present invention The schematic diagram of the pad structure in each step of the CSP packaging method, please refer to Figure 2, and in conjunction with Figures 3 to 13, describe the CSP packaging method proposed by the present invention in detail:

In step S01, a chip is firstly provided, and the solder tab structure in the chip adopts the solder tab structure described in Embodiment 1. As shown in FIG. 3 , the chip includes a substrate 101 and a transparent cover plate 102, located at The pad structure 103 and the passivation layer 104 between the substrate 101 and the transparent cover 102 , and the gel substance 105 for connecting the silicon substrate 101 and the transparent cover 102 . The substrate 101 may be a silicon substrate, such as one of single crystal silicon, polycrystalline silicon or amorphous silicon, or silicon on insulator (Silicon On Insulator, SOI), or a silicon germanium compound. In this embodiment, the substrate 101 is a silicon substrate. It should be noted that semiconductor structures (not shown in FIG. 3 ) such as a gate, a source, and a drain have been formed on the substrate 101, and the semiconductor structure can be connected to an external circuit through a metal interconnection structure and a pad structure. Connect, so as to realize various functions of the device.

Then, the substrate 101 is etched at the bottom of the pad structure 103 at the edge of the chip to form a trench 106, and the bottom of the trench 106 stops on the interlayer dielectric layer 12 at the bottom of the pad structure 103 , exposing the interlayer dielectric layer 12, the schematic structural diagram of the chip is shown in FIG. 4, and the enlarged schematic diagram of the dotted circle in FIG. 4 is shown in FIG. 5, which is the structural schematic diagram of the pad structure 103 in this step.

Finally, the interlayer dielectric layer 12 is etched to expose the stepped metal layers. In this embodiment, the material of the interlayer dielectric layer 12 is silicon oxide, that is, silicon oxide etching is performed once. Thus, the underlying metal layer M1 and a part of other metal layers can be exposed, as shown in FIG. 6 .

In step S03, first, an insulating layer 107 is formed on the back of the chip. The material of the insulating layer 107 can be silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the insulating layer 107 is oxide silicon. The process for forming the insulating layer 107 includes but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD). Then, the metal layers in the pad structure 103 are exposed by photolithography and etching on the insulating layer 107, and the structural schematic diagram of the obtained chip is shown in Figure 7, and the enlarged schematic diagram of the dotted circle in Figure 7 is as follows As shown in FIG. 8 , it is a structural schematic diagram of the pad structure 103 in this step.

Next, a second metal layer 108 is formed on the back of the chip, and the second metal layer 108 includes but not limited to aluminum or copper material. Patterning is formed by performing photolithography and etching on the second metal layer 108. The patterned second metal layer can be a pre-designed pattern, and the chip structure finally formed is shown in FIG. 9 . The pad structure is shown in FIG. 10 , and FIG. 10 is an enlarged schematic diagram of the dotted circle in FIG. 9 .

Finally, a protective layer 109 is formed on the back of the chip, and the protective layer 109 is made of organic resin or other materials known to those skilled in the art. By performing photolithography and etching on the protective layer 109, at least one through hole 110 is formed to expose the second metal layer 108 for connection in subsequent processes. The final chip structure is shown in FIG. 11 , and finally formed The bonding pad structure of FIG. 12 is shown in FIG. 12 , and FIG. 12 is a schematic diagram of the method at the dotted circle in FIG. 11 .

It also includes a step S04 of arranging solder balls 111 in the through holes 110 of the protection layer to be in contact with the second metal layer, finally forming the structure as shown in FIG. 13 .

The CSP packaging method provided by the embodiment of the present invention exposes each layer of metal layers in a stepped shape through one etching, so that each layer of metal layers can be in contact with the second metal layer 108 on the back, greatly increasing the contact between each layer of metal layers and The contact area of the second metal layer 108 reduces the contact resistance and improves the reliability of the packaging, and the packaging method does not need to form through-silicon holes, the process is simple, and the packaging cost is reduced.

To sum up, in the bonding pad structure and CSP packaging method provided by the present invention, in the bonding pad structure, starting from the bottom metal layer, the distances from the metal layers of each layer to the edge of the chip are successively reduced, forming Stepped structure, when CSP is packaged, each layer of metal layer can be exposed by etching, so that each layer of metal layer can be in contact with the second metal layer on the back, which greatly increases the contact area, reduces the contact resistance, and improves the The reliability of the packaging is high, and the packaging does not need to form through-silicon holes, the process is simple, and the packaging cost is reduced.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.

Claims (13)

1. A welding pad structure, located in a chip, comprising a substrate, a metal layer located at the bottom of the substrate, a metal layer in the middle of the multilayer and a metal layer on the top layer successively, it is characterized in that, from the Starting from the bottom metal layer, the distance from each metal layer to the edge of the chip decreases successively, forming a stepped structure. 2 . The pad structure according to claim 1 , wherein, starting from the bottom metal layer, the cross-sectional area of each metal layer increases sequentially. 3 . 3 . The pad structure according to claim 1 , further comprising an interlayer dielectric layer located between the metal layers and between the underlying metal layer and the substrate. 4 . 4. The pad structure according to claim 3, further comprising a passivation layer covering the metal layer of the top layer and exposing a part of the metal layer of the top layer. 5 . The pad structure according to claim 4 , wherein the metal layers of adjacent layers are connected through contact holes. 5 . 6. The bonding pad structure according to claim 5, wherein the bonding pad structure is connected to the internal circuit structure of the chip through the underlying metal layer. 7. A CSP encapsulation method for encapsulating a chip, characterized in that the chip comprises the pad structure according to any one of claims 1 to 6, and the encapsulation method comprises the following steps: Step S01: Etching the back of the bonding pad structure on the edge of the chip to expose the stepped metal layers; Step S02 : sequentially forming an insulating layer, a second metal layer and a protection layer on the back of the chip. 8. The CSP packaging method according to claim 7, characterized in that, in step S01, at first the substrate on the back of the pad structure is etched to expose the interlayer dielectric layer; then the interlayer The dielectric layer is etched to expose various metal layers in a stepped shape. 9. The CSP packaging method according to claim 8, wherein a groove is formed on the substrate by etching, and the bottom of the groove stops on the interlayer dielectric layer at the bottom of the pad structure. 10 . The CSP packaging method according to claim 7 , wherein in step S02 , after forming the insulating layer, each metal layer in the pad structure is exposed by photolithography and etching. 11 . 11. The CSP packaging method according to claim 10, wherein in step S02, after forming the second metal layer, a patterned second metal layer is formed by photolithography and etching. 12 . The CSP packaging method according to claim 11 , wherein in step S02 , after forming the protective layer, photolithography and etching are performed to form at least one via hole on the protective layer. 13 . 13 . The CSP packaging method according to claim 12 , further comprising step S03 , disposing solder balls in the through holes of the protective layer to contact the second metal layer. 14 .