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CN107481926A - A kind of filling method of metal tungsten - Google Patents

A kind of filling method of metal tungsten Download PDF

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Publication number
CN107481926A
CN107481926A CN201710772342.9A CN201710772342A CN107481926A CN 107481926 A CN107481926 A CN 107481926A CN 201710772342 A CN201710772342 A CN 201710772342A CN 107481926 A CN107481926 A CN 107481926A
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tungsten
filling
layer
flow rate
temperature
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彭浩
左明光
詹侃
许爱春
万先进
吴关平
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Yangtze Memory Technologies Co Ltd
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C23C16/14Deposition of only one other metal element
    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/031Manufacture or treatment of data-storage electrodes
    • H10D64/037Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

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Abstract

The present invention provides a kind of fill method of tungsten, filling applied to the control gate of 3D NAND devices, silicon nitride layer in stack layer of the fill process in 3D NAND devices is carried out after being removed, in fill process, reacting gas is hydrogen and tungsten hexafluoride, and pressure is 5 30torr, and temperature is 250 430 DEG C, the flow of hydrogen is 7500 20000sccm, and the flow of tungsten hexafluoride is 60 500sccm.This method is particularly suitable for use in the filling of more deep hole and more high-aspect-ratio, and deposition during filling is low, can effectively reduce the filling defect in the gap and cavity in filling, improve filling quality.

Description

一种金属钨的填充方法A kind of filling method of metal tungsten

技术领域technical field

本发明涉及3D NAND存储器件及其制造领域,特别涉及一种金属钨的填充方法。The invention relates to the field of 3D NAND storage devices and its manufacture, in particular to a method for filling metal tungsten.

背景技术Background technique

NAND闪存是一种比硬盘驱动器更好的存储设备,随着人们追求功耗低、质量轻和性能佳的非易失存储产品,在电子产品中得到了广泛的应用。目前,平面结构的NAND闪存已近实际扩展的极限,为了进一步的提高存储容量,降低每比特的存储成本,提出了3D结构的NAND存储器。NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed.

在3D NAND存储器结构中,采用垂直堆叠多层数据存储单元的方式,实现堆叠式的3D NAND存储器结构。在形成3D NAND存储器时,首先,在衬底上形成氮化硅(Si3N4)层和氧化硅(SiO2)层的堆叠层,堆叠层的侧壁为阶梯形貌;而后,在堆叠层中形成沟道孔(Channelhole),沟道孔用于形成存储区;在沟道孔中形成存储区之后,将堆叠层中的氮化硅层去除,进而进行金属材料的填充,从而将堆叠层中的氮化硅层替换为金属层,每一层的金属层为每一层存储单元的控制栅,堆叠层的每一层阶梯用于形成每一层控制栅的接触塞。In the 3D NAND memory structure, a stacked 3D NAND memory structure is realized by vertically stacking multiple layers of data storage units. When forming a 3D NAND memory, first, a stacked layer of silicon nitride (Si 3 N 4 ) layer and silicon oxide (SiO 2 ) layer is formed on the substrate, and the sidewall of the stacked layer has a stepped shape; A channel hole (Channelhole) is formed in the layer, and the channel hole is used to form a storage area; after the storage area is formed in the channel hole, the silicon nitride layer in the stack layer is removed, and then the metal material is filled, so that the stack The silicon nitride layer in each layer is replaced by a metal layer, the metal layer of each layer is the control gate of each layer of memory cells, and each step of the stacked layers is used to form a contact plug of each layer of control gate.

目前,通常是采用化学气相沉积(CVD)工艺,进行金属钨(W)的填充,来形成金属层。而随着集成度的不断提高,堆叠层的层数也不断增加,栅线的尺寸也不断减小,在填充过程中,会出现缝隙(seam)或者空洞(void)的缺陷,这会导致漏电以及发热异常等问题,影响器件的良率和可靠性。Currently, a chemical vapor deposition (CVD) process is usually used to fill metal tungsten (W) to form a metal layer. With the continuous improvement of integration, the number of stacked layers is also increasing, and the size of the gate lines is also decreasing. During the filling process, defects such as seams or voids will appear, which will lead to leakage. And problems such as abnormal heating affect the yield and reliability of the device.

发明内容Contents of the invention

有鉴于此,本发明的目的在于提供一种金属钨的填充方法,减少填充缺陷,提高填充质量。In view of this, the object of the present invention is to provide a filling method for metal tungsten, which can reduce filling defects and improve filling quality.

为实现上述目的,本发明有如下技术方案:To achieve the above object, the present invention has the following technical solutions:

一种金属钨的填充方法,在衬底上形成具有3D NAND器件的堆叠层,且所述堆叠层中的氮化硅层被去除之后;进行金属钨的填充,所述金属钨的填充工艺包括:A method for filling metal tungsten, forming a stacked layer with a 3D NAND device on a substrate, and after the silicon nitride layer in the stacked layer is removed; filling with metal tungsten, the filling process of metal tungsten includes :

反应气体为氢气和六氟化钨,压力为5-30torr,温度为250-430℃,氢气的流量为7500-20000sccm,六氟化钨的流量为60-500sccm。The reaction gas is hydrogen and tungsten hexafluoride, the pressure is 5-30torr, the temperature is 250-430°C, the flow rate of hydrogen gas is 7500-20000sccm, and the flow rate of tungsten hexafluoride is 60-500sccm.

可选地,在进行金属钨的填充之前,还包括钨种子层的沉积。Optionally, before the metal tungsten is filled, the deposition of a tungsten seed layer is also included.

可选地,所述钨种子层的沉积工艺包括:反应气体为乙硼烷和六氟化钨,压力、温度以及六氟化钨的流量分别与所述金属钨的填充工艺中的压力、温度以及六氟化钨的流量相同,乙硼烷的流量为300-750sccm。Optionally, the deposition process of the tungsten seed layer includes: the reaction gas is diborane and tungsten hexafluoride, and the pressure, temperature and flow rate of tungsten hexafluoride are respectively related to the pressure and temperature in the filling process of the metal tungsten The flow rate of tungsten hexafluoride is the same, and the flow rate of diborane is 300-750 sccm.

可选地,乙硼烷的流量为400-500sccm。Optionally, the flow rate of diborane is 400-500 sccm.

可选地,所述堆叠层中的去除的氮化硅层的层数为32层或64层。Optionally, the number of removed silicon nitride layers in the stacked layers is 32 or 64 layers.

可选地,所述金属钨的填充工艺中,压力为5-15torr。Optionally, in the filling process of metal tungsten, the pressure is 5-15 torr.

可选地,所述金属钨的填充工艺中,温度为250-300℃,六氟化钨的流量为100-300sccm,氢气的流量为9000-19000。Optionally, in the filling process of metal tungsten, the temperature is 250-300°C, the flow rate of tungsten hexafluoride is 100-300 sccm, and the flow rate of hydrogen gas is 9000-19000.

可选地,所述金属钨的填充工艺中,压力为30torr,温度为250℃,六氟化钨的流量为60sccm,氢气的流量为9500sccm。Optionally, in the filling process of metal tungsten, the pressure is 30 torr, the temperature is 250° C., the flow rate of tungsten hexafluoride is 60 sccm, and the flow rate of hydrogen gas is 9500 sccm.

本发明实施例提供的金属钨的填充方法,应用于3D NAND器件的控制栅的填充,在填充工艺在3DNAND器件的堆叠层中的氮化硅层被去除之后进行,在填充工艺中,反应气体为氢气和六氟化钨,压力为5-30torr,温度为250-430℃,氢气的流量为7500-20000sccm,六氟化钨的流量为60-500sccm。该方法尤其适用于更深孔和更高深宽比的填充,填充时的沉积率低,可以有效减少填充中的缝隙以及空洞的填充缺陷,提高填充质量。The filling method of metal tungsten provided by the embodiment of the present invention is applied to the filling of the control gate of the 3D NAND device, and is performed after the silicon nitride layer in the stacked layer of the 3D NAND device is removed in the filling process. In the filling process, the reaction gas It is hydrogen and tungsten hexafluoride, the pressure is 5-30torr, the temperature is 250-430°C, the flow rate of hydrogen gas is 7500-20000sccm, and the flow rate of tungsten hexafluoride is 60-500sccm. This method is especially suitable for the filling of deeper holes and higher aspect ratios. The deposition rate during filling is low, which can effectively reduce the gaps and filling defects in filling, and improve the filling quality.

附图说明Description of drawings

为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present invention, those skilled in the art can also obtain other drawings based on these drawings without creative work.

图1-图5示出了3D NAND器件制造过程中的剖面结构示意图。1 to 5 show schematic cross-sectional structures during the manufacturing process of 3D NAND devices.

具体实施方式detailed description

为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

在下面的描述中阐述了很多具体细节以便于充分理解本发明,但是本发明还可以采用其他不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下做类似推广,因此本发明不受下面公开的具体实施例的限制。In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

其次,本发明结合示意图进行详细描述,在详述本发明实施例时,为便于说明,表示器件结构的剖面图会不依一般比例作局部放大,而且所述示意图只是示例,其在此不应限制本发明保护的范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

正如背景技术中的描述,在3D NAND存储器的制造工艺中,采用垂直堆叠多层数据存储单元的方式,实现堆叠式的3D NAND存储器结构,在形成控制栅时,是将堆叠层中的氮化硅层去除之后,填充进金属钨,从而形成控制栅,填充的位置位于两层氧化硅层之间,填充中容易出现缝隙(seam)或者空洞(void)的缺陷,尤其是在集成度不断提高之后,堆叠层的层数也不断增加,栅线的尺寸也不断减小,缺陷更加明显,在器件使用中,会出现漏电的问题以及发热异常等问题,影响器件的良率和可靠性。As described in the background technology, in the manufacturing process of 3D NAND memory, the stacked 3D NAND memory structure is realized by vertically stacking multi-layer data storage cells. When forming the control gate, the nitride in the stacked layer is After the silicon layer is removed, it is filled with metal tungsten to form a control gate. The filling position is located between two silicon oxide layers. Seam or void defects are prone to appear during filling, especially when the integration level continues to increase. Afterwards, the number of stacked layers continued to increase, the size of the gate lines also continued to decrease, and the defects became more obvious. During the use of the device, there will be problems such as leakage and abnormal heating, which will affect the yield and reliability of the device.

为此,本发明提出了一种金属钨的填充方法,在衬底上形成具有3D NAND器件的堆叠层,且所述堆叠层中的氮化硅层被去除之后;进行金属钨的填充,所述金属钨的填充工艺包括:For this reason, the present invention proposes a method for filling metal tungsten, forming a stacked layer with a 3D NAND device on the substrate, and after the silicon nitride layer in the stacked layer is removed; filling with metal tungsten, so The filling process of metal tungsten includes:

反应气体为氢气和六氟化钨,压力为5-30torr,温度为250-430℃,氢气的流量为7500-20000sccm,六氟化钨的流量为60-500sccm。The reaction gas is hydrogen and tungsten hexafluoride, the pressure is 5-30torr, the temperature is 250-430°C, the flow rate of hydrogen gas is 7500-20000sccm, and the flow rate of tungsten hexafluoride is 60-500sccm.

该方法为3D NAND器件制造中形成控制栅时的金属钨的填充,该方法尤其适用于更深孔和更高深宽比的填充,填充时的沉积率低,可以有效减少填充中的缝隙以及空洞的填充缺陷,提高填充质量。This method is the filling of metal tungsten when forming the control gate in the manufacture of 3D NAND devices. This method is especially suitable for filling deeper holes and higher aspect ratios. The deposition rate during filling is low, which can effectively reduce gaps and voids in filling. Fill defects and improve filling quality.

为了更好地理解本发明的技术方案和技术效果,以下将结合具体的实施例进行详细的描述。In order to better understand the technical solutions and technical effects of the present invention, the following will be described in detail in conjunction with specific embodiments.

参考图1所示,该方法是在衬底100上形成具有3D NAND器件的堆叠层110,且所述堆叠层110中的氮化硅层1102被去除之后进行的。Referring to FIG. 1 , the method is performed after forming a stack layer 110 with 3D NAND devices on a substrate 100 and removing the silicon nitride layer 1102 in the stack layer 110 .

为了更好的理解本发明的技术方案,先结合具体的实施例对金属钨填充之前的制造工艺进行详细的描述。In order to better understand the technical solution of the present invention, the manufacturing process before metal tungsten filling will be described in detail in combination with specific examples.

首先,提供衬底100,在衬底100上形成堆叠层110,所述堆叠层110为氮化物层1102和氧化物层1101交替层叠而形成,参考图1所示。Firstly, a substrate 100 is provided, and a stacked layer 110 is formed on the substrate 100. The stacked layer 110 is formed by alternately stacking nitride layers 1102 and oxide layers 1101, as shown in FIG. 1 .

衬底100为半导体衬底,例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅,Silicon OnInsulator)或GOI(绝缘体上锗,GermaniumOnInsulator)等。在其他实施例中,所述半导体衬底还可以为包括其他元素半导体或化合物半导体的衬底,例如GaAs、InP或SiC等,还可以为叠层结构,例如Si/SiGe等,还可以其他外延结构,例如SGOI(绝缘体上锗硅)等。通常地,衬底为体硅衬底。The substrate 100 is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator, Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator) and the like. In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other epitaxial Structures, such as SGOI (silicon germanium on insulator), etc. Typically, the substrate is a bulk silicon substrate.

由氮化硅层和氧化物层交替层叠来形成堆叠层110,根据垂直方向所需形成的存储单元的个数来确定堆叠层110的层数,堆叠层110的层数例如可以为32层、64层等,此处堆叠层的层数是指其中氮化硅层的层数,该氮化硅层为牺牲层,在后续的步骤中将被替换为金属层,为存储器件的控制栅,该层数决定了垂直方向上存储单元的个数,因此,堆叠层的层数越多,越能提高集成度。The stacked layer 110 is formed by alternately stacking silicon nitride layers and oxide layers, and the number of layers of the stacked layer 110 is determined according to the number of memory cells required to be formed in the vertical direction. The number of layers of the stacked layer 110 can be, for example, 32 layers, 64 layers, etc. The number of stacked layers here refers to the number of layers of the silicon nitride layer. The silicon nitride layer is a sacrificial layer, which will be replaced by a metal layer in subsequent steps, and is the control gate of the storage device. The number of layers determines the number of storage units in the vertical direction. Therefore, the more layers there are in the stack, the more integration can be improved.

可以采用化学气相沉积、原子层沉积或其他合适的沉积方法,依次交替沉积氮化硅和氧化硅,形成该堆叠层110;而后,通过刻蚀工艺,使得堆叠层110的边缘为阶梯结构,阶梯结构用于后续形成控制栅上的接触,堆叠层的中央区域用于形成沟道孔和沟道孔中的存储区。The stacked layer 110 can be formed by alternately depositing silicon nitride and silicon oxide sequentially by using chemical vapor deposition, atomic layer deposition or other suitable deposition methods; The structure is used to subsequently form a contact on the control gate, and the central area of the stacked layer is used to form a channel hole and a storage area in the channel hole.

接着,在堆叠层中形成沟道孔120。Next, channel holes 120 are formed in the stacked layers.

该沟道孔120为堆叠层110中的通孔,可以采用刻蚀技术,例如RIE(反应离子刻蚀)的方法,刻蚀堆叠层,直到暴露出衬底表面,或过刻蚀部分衬底,从而,来形成该沟道孔120。形成沟道孔120之后,通常,通过选择性外延生长(Selective EpitaxialGrowth),先在沟道孔110底部原位生长出外延结构122,该外延结构122起到连接沟道孔中的存储区的作用,以及在去除氮化硅层时起到支撑堆叠层的作用。The channel hole 120 is a through hole in the stack layer 110, and an etching technique, such as RIE (Reactive Ion Etching) method, may be used to etch the stack layer until the substrate surface is exposed, or a part of the substrate may be over-etched. , thereby forming the channel hole 120 . After the channel hole 120 is formed, usually, by selective epitaxial growth (Selective Epitaxial Growth), an epitaxial structure 122 is grown in situ at the bottom of the channel hole 110, and the epitaxial structure 122 plays a role of connecting the storage area in the channel hole , and to support the stacked layers while removing the silicon nitride layer.

而后,在沟道孔中形成存储区。Then, a memory region is formed in the channel hole.

NAND存储器件的存储区包括电荷捕获层和沟道层,该步骤中,先在沟道孔中形成电荷捕获层,具体实施例中,电荷捕获层为ONO的叠层,ONO(Oxide-Ntride-Oxide)即氧化物、氮化物和氧化物。可以通过原子层沉积(ALD)的方法来形成该ONO的电荷捕获层。在沉积之后,沟道孔的侧壁以及底部都覆盖了电荷捕获层。而后,进行沟道层的形成,具体实施例中,采用多晶硅来形成沟道层。最后在沟道孔中填充氧化物,从而在沟道孔中完成存储区的制造。The storage area of the NAND storage device includes a charge trapping layer and a channel layer. In this step, the charge trapping layer is first formed in the channel hole. In a specific embodiment, the charge trapping layer is a stack of ONO, ONO (Oxide-Ntride- Oxide) is oxide, nitride and oxide. The charge trapping layer of the ONO can be formed by atomic layer deposition (ALD). After deposition, the sidewalls as well as the bottom of the channel hole are covered with the charge trapping layer. Then, a channel layer is formed. In a specific embodiment, polysilicon is used to form the channel layer. Finally, oxide is filled in the channel hole, thereby completing the fabrication of the storage area in the channel hole.

而后,参考图2刻蚀堆叠层110,形成栅线缝隙(Gate Line Seam)130,通过栅线缝隙130将堆叠层110中的氮化硅层1102去除,参考图3所示。Then, referring to FIG. 2 , the stacked layer 110 is etched to form a gate line seam (Gate Line Seam) 130 , and the silicon nitride layer 1102 in the stacked layer 110 is removed through the gate line seam 130 , as shown in FIG. 3 .

在去除堆叠层中的氮化硅层1102时,选择对氮化硅和氧化硅的高选择比的酸液,实现去除氮化硅的同时,避免氧化硅的去除,在实际工艺中,通常采用磷酸(H3PO4)进行氮化硅层的去除。When removing the silicon nitride layer 1102 in the stacked layer, an acid solution with a high selectivity ratio to silicon nitride and silicon oxide is selected to realize the removal of silicon nitride while avoiding the removal of silicon oxide. In the actual process, usually adopt Phosphoric acid (H 3 PO 4 ) performs the removal of the silicon nitride layer.

在氮化硅层去除之后,参考图3所示,堆叠层110为镂空结构,在氧化物层1101之间为空缺层1103,在其中填充金属后形成栅线,为存储单元的控制栅。本发明的金属钨的填充方法就是在氮化硅层去除之后,进行的金属钨的填充,相较于其他半导体工艺中钨的形成,在该镂空结构中填充金属钨,需要更低的填充速率,来提高填充质量,避免填充缺陷的产生。After the removal of the silicon nitride layer, as shown in FIG. 3 , the stacked layer 110 is a hollow structure, and between the oxide layers 1101 is a vacant layer 1103 , which is filled with metal to form a gate line, which is the control gate of the memory cell. The metal tungsten filling method of the present invention is to fill the metal tungsten after the removal of the silicon nitride layer. Compared with the formation of tungsten in other semiconductor processes, filling the metal tungsten in the hollow structure requires a lower filling rate. , to improve filling quality and avoid filling defects.

化学气相沉积(CVD)沉积钨时,采用的反应气体为氢气(H2)和六氟化钨(WF6),反应速率也就是沉积速率的公式如下:When chemical vapor deposition (CVD) deposits tungsten, the reaction gases used are hydrogen (H 2 ) and tungsten hexafluoride (WF 6 ), and the reaction rate, that is, the deposition rate formula is as follows:

DepRate=R0e-E/kT[H2]0.5[WF6]0 DepRate=R 0 e -E/kT [H 2 ] 0.5 [WF 6 ] 0

其中:K、R0、E为相关的沉积系数;[H2]为氢气的分压;[WF6]为WF6的分压;T为温度。Among them: K, R 0 , E are relative deposition coefficients; [H 2 ] is partial pressure of hydrogen; [WF 6 ] is partial pressure of WF 6 ; T is temperature.

可以看到,主要是通过反应时的温度以及反应气体的分压来降低沉积时的速率,而对于3D NAND器件中镂空结构填充时,单单通过气体分压和温度的降低,来降低沉积速率,会带来金属钨的电阻率高和应力变大的问题,而此时金属钨作为存储器的控制栅,电阻率高和应力变大会带来性能上的问题,无法同时满足填充质量和性能上的要求。It can be seen that the deposition rate is mainly reduced by the temperature of the reaction and the partial pressure of the reaction gas, while for the filling of the hollow structure in the 3D NAND device, the deposition rate is reduced only by the reduction of the gas partial pressure and temperature. It will bring the problems of high resistivity and increased stress of metal tungsten. At this time, metal tungsten is used as the control gate of the memory, and the high resistivity and increased stress will cause performance problems, which cannot meet the filling quality and performance requirements at the same time. Require.

为此,发明人通过研究,提出了针对于上述3D NAND器件中的栅线的填充的问题,提出了一种金属钨的填充方法,此时,衬底100上的堆叠层110为镂空结构,参考图3所示,填充时的工艺包括:For this reason, the inventor, through research, proposed the problem of filling the gate lines in the above-mentioned 3D NAND device, and proposed a filling method of metal tungsten. At this time, the stacked layer 110 on the substrate 100 is a hollow structure, Referring to Figure 3, the filling process includes:

反应气体为氢气和六氟化钨,压力为5-30torr,温度为250-430℃,氢气的流量为7500-20000sccm,六氟化钨的流量为60-500sccm。The reaction gas is hydrogen and tungsten hexafluoride, the pressure is 5-30torr, the temperature is 250-430°C, the flow rate of hydrogen gas is 7500-20000sccm, and the flow rate of tungsten hexafluoride is 60-500sccm.

在该填充中,将沉积时的压力进一步降低,结合适当的温度和流量,能够获得较好的填充质量,同时保证电阻率和应力等性能也满足要求。In this filling, the pressure during deposition is further reduced, combined with appropriate temperature and flow rate, better filling quality can be obtained, and at the same time, properties such as resistivity and stress can also meet the requirements.

在进行钨填充之前,更优地,先进行钨种子层的沉积。Before the tungsten filling, preferably, the tungsten seed layer is deposited first.

在钨种子层的沉积工艺中,反应气体为乙硼烷(B2H6)和六氟化钨,钨种子层和钨填充通常在同一设备中进行,在这两个沉积中压力、温度和六氟化钨气体流量在整个过程中的设置可以是相同的,具体沉积时,首先,从温度范围250-430℃中选择工艺温度,从压力范围5-30torr中选择工艺压力,B2H6的流量范围为300-750sccm,WF6的流量为60-500sccm,在此工艺条件下,进行钨的沉积,形成钨种子层;之后,停止B2H6的供应,并通入氢气,氢气的流量为7500-20000sccm,其他的工艺条件不变,保持前一沉积时的温度、压力以及WF6的流量,进行更厚层的钨的填充,在填充之后,氧化物层1101之间填充了钨的金属层,从而,在堆叠层的空缺层中形成栅线1104,参考图4所示,同时在栅线缝隙130的侧壁以及堆叠上也会沉积一层金属钨层140,而后,可以通过湿法刻蚀工艺,将该部分的金属钨层140去除,参考图5所示。In the deposition process of the tungsten seed layer, the reaction gases are diborane (B 2 H 6 ) and tungsten hexafluoride, the tungsten seed layer and the tungsten filling are usually performed in the same equipment, and the pressure, temperature and The setting of tungsten hexafluoride gas flow rate in the whole process can be the same. During the specific deposition, firstly, select the process temperature from the temperature range of 250-430°C, select the process pressure from the pressure range of 5-30torr, B 2 H 6 The flow range of WF 6 is 300-750sccm, and the flow rate of WF 6 is 60-500sccm. Under these process conditions, tungsten is deposited to form a tungsten seed layer; after that, the supply of B 2 H 6 is stopped, and hydrogen gas is introduced. The flow rate is 7500-20000 sccm, other process conditions remain unchanged, the temperature, pressure and flow rate of WF 6 during the previous deposition are maintained, and a thicker layer of tungsten is filled. After filling, the gap between the oxide layers 1101 is filled with tungsten metal layer, so that the gate line 1104 is formed in the vacant layer of the stack layer, as shown in FIG. The wet etching process removes the part of the metal tungsten layer 140 , as shown in FIG. 5 .

在更为优选的实施例中,压力的范围为5-15torr,温度的范围为250-300℃,B2H6的流量范围为750-1500sccm,WF6的流量范围为100-300sccm,H2的流量范围为9000-19000sccm。需要说明的是,以上温度、压力、流量等参数的范围是指,在沉积工艺中,这些参数从该范围中选择参数值。In a more preferred embodiment, the range of pressure is 5-15 torr, the range of temperature is 250-300°C, the flow rate of B 2 H 6 is in the range of 750-1500 sccm, the flow rate of WF 6 is in the range of 100-300 sccm, H 2 The flow range is 9000-19000sccm. It should be noted that the above ranges of parameters such as temperature, pressure, and flow rate mean that in the deposition process, these parameters are selected from the ranges.

在一个更优的实施例中,所述金属钨的填充工艺中,压力为30torr,温度为250℃,六氟化钨的流量为60sccm,B2H6的流量为450sccm,氢气的流量为9500sccm,在该工艺条件下,沉积速率为 In a more preferred embodiment, in the filling process of metal tungsten, the pressure is 30 torr, the temperature is 250°C, the flow rate of tungsten hexafluoride is 60 sccm, the flow rate of B2H6 is 450 sccm, and the flow rate of hydrogen gas is 9500 sccm , under this process condition, the deposition rate is

在一个具体的实施例中,压力为40torr,温度为300℃,WF6的流量为400sccm,H2的流量为19000sccm,此时,钨的沉积速率为 In a specific embodiment, the pressure is 40torr, the temperature is 300°C, the flow of WF 6 is 400sccm, and the flow of H 2 is 19000sccm. At this time, the deposition rate of tungsten is

在一个具体的实施例中,压力为30torr,温度为300℃,WF6的流量为400sccm,H2的流量为19000sccm,此时,钨的沉积速率为 In a specific embodiment, the pressure is 30torr, the temperature is 300°C, the flow of WF 6 is 400sccm, and the flow of H 2 is 19000sccm. At this time, the deposition rate of tungsten is

在一个具体的实施例中,压力为40torr,温度为250℃,WF6的流量为400sccm,H2的流量为19000sccm,此时,钨的沉积速率为 In a specific embodiment, the pressure is 40torr, the temperature is 250°C, the flow of WF 6 is 400sccm, and the flow of H 2 is 19000sccm. At this time, the deposition rate of tungsten is

在一个具体的实施例中,压力为30torr,温度为250℃,WF6的流量为400sccm,H2的流量为19000sccm,此时,钨的沉积速率为 In a specific embodiment, the pressure is 30 torr, the temperature is 250°C, the flow of WF 6 is 400 sccm, and the flow of H 2 is 19000 sccm. At this time, the deposition rate of tungsten is

以上的金属钨的沉积尤其适用于更深孔和更高深宽比的填充,应用于32层、64层的3D存储器件的栅线填充工艺中,填充时的沉积率低,可以有效减少填充中的缝隙以及空洞的填充缺陷,提高填充质量,同时保证栅线的电阻率和应力等性能满足要求。The above metal tungsten deposition is especially suitable for the filling of deeper holes and higher aspect ratios. It is applied in the gate line filling process of 32-layer and 64-layer 3D memory devices. The deposition rate during filling is low, which can effectively reduce the filling process. Filling defects in gaps and cavities improves the quality of filling, while ensuring that the resistivity and stress of the grid line meet the requirements.

以上所述仅是本发明的优选实施方式,虽然本发明已以较佳实施例披露如上,然而并非用以限定本发明。任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。The above descriptions are only preferred implementations of the present invention. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent of equivalent change Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (8)

1.一种金属钨的填充方法,其特征在于,在衬底上形成具有3D NAND器件的堆叠层,且所述堆叠层中的氮化硅层被去除之后;进行金属钨的填充,所述金属钨的填充工艺包括:1. A method for filling metal tungsten, characterized in that, on a substrate, a stacked layer with a 3D NAND device is formed, and after the silicon nitride layer in the stacked layer is removed; the filling of metal tungsten is carried out, the The filling process of metal tungsten includes: 反应气体为氢气和六氟化钨,压力为5-30torr,温度为250-430℃,氢气的流量为7500-20000sccm,六氟化钨的流量为60-500sccm。The reaction gas is hydrogen and tungsten hexafluoride, the pressure is 5-30torr, the temperature is 250-430°C, the flow rate of hydrogen gas is 7500-20000sccm, and the flow rate of tungsten hexafluoride is 60-500sccm. 2.根据权利要求1所述的方法,其特征在于,在进行金属钨的填充之前,还包括钨种子层的沉积。2 . The method according to claim 1 , further comprising depositing a tungsten seed layer before filling the metal tungsten. 3 . 3.根据权利要求2所述的方法,其特征在于,所述钨种子层的沉积工艺包括:反应气体为乙硼烷和六氟化钨,压力、温度以及六氟化钨的流量分别与所述金属钨的填充工艺中的压力、温度以及六氟化钨的流量相同,乙硼烷的流量为300-750sccm。3. method according to claim 2, is characterized in that, the deposition process of described tungsten seed layer comprises: reaction gas is diborane and tungsten hexafluoride, and the flow rate of pressure, temperature and tungsten hexafluoride are respectively with the described tungsten hexafluoride The pressure, temperature and flow rate of tungsten hexafluoride in the filling process of metal tungsten are the same, and the flow rate of diborane is 300-750 sccm. 4.根据权利要求3所述的方法,其特征在于,乙硼烷的流量为400-500sccm。4. The method according to claim 3, characterized in that the flow of diborane is 400-500 sccm. 5.根据权利要求1所述的方法,其特征在于,所述堆叠层中的去除的氮化硅层的层数为32层或64层。5 . The method according to claim 1 , wherein the number of removed silicon nitride layers in the stacked layers is 32 layers or 64 layers. 6.根据权利要求1-5中任一项所述的方法,其特征在于,所述金属钨的填充工艺中,压力为5-15torr。6. The method according to any one of claims 1-5, characterized in that, in the filling process of the metal tungsten, the pressure is 5-15 torr. 7.根据权利要求6所述的方法,其特征在于,所述金属钨的填充工艺中,温度为250-300℃,六氟化钨的流量为100-300sccm,氢气的流量为9000-19000。7. The method according to claim 6, characterized in that, in the filling process of metal tungsten, the temperature is 250-300°C, the flow rate of tungsten hexafluoride is 100-300 sccm, and the flow rate of hydrogen gas is 9000-19000. 8.根据权利要求1-5中任一项所述的方法,其特征在于,所述金属钨的填充工艺中,压力为30torr,温度为250℃,六氟化钨的流量为60sccm,氢气的流量为9500sccm。8. The method according to any one of claims 1-5, characterized in that, in the filling process of metal tungsten, the pressure is 30 torr, the temperature is 250°C, the flow rate of tungsten hexafluoride is 60 sccm, and the flow rate of hydrogen The flow rate is 9500sccm.
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