CN107481759B - External double-voltage input selection switch circuit and electronic device - Google Patents
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Abstract
The invention provides an external double-voltage input selection switch circuit and an electronic device, wherein the selection switch circuit comprises a reference voltage control unit, a voltage lifting unit and a first NMOS transistor, wherein: the reference voltage control unit is configured to output a control voltage signal to the voltage lifting unit based on a reference voltage; the voltage raising unit is connected to the grid electrode of the first NMOS transistor and configured to output a grid electrode voltage to the grid electrode based on the control voltage signal; the drain of the first NMOS transistor is connected to the output terminal of the selection switch circuit, and the source of the first NMOS transistor is connected to a negative charge pump bias voltage. According to the invention, by means of the combined action of the reference voltage control unit and the voltage raising unit, the voltage difference between the grid voltage and the substrate voltage of the first NMOS transistor can be controlled to be less than 4V, the reliability of the first NMOS transistor is improved, and the voltage output by the selection switch circuit meets the requirements of programming and erasing operations of the NVM storage unit.
Description
Technical Field
The invention relates to a semiconductor manufacturing process, in particular to an external double-voltage input selection switch circuit and an electronic device.
Background
Memory cells in non-volatile memory (NVM) circuits require a high negative charge pump bias voltage (pump bias), such as a positive or negative bias, for programming and erasing operations. The above programming and erasing operation processes do not have any problem if the nonvolatile memory chip can support a high breakdown voltage and a strong gate oxide breakdown characteristic (GOI). However, the existing Internet of Things (Internet of Things) process applies a medium voltage device (e.g. 3.3V device) with low power consumption to program and erase operations of the NVM memory cell, which limits the improvement of the breakdown voltage and gate oxide breakdown characteristics of the NVM memory cell when the NVM memory cell operates under a higher bias condition.
Disclosure of Invention
To overcome the defects of the prior art, the present invention provides an external dual-voltage input selection switch circuit, which comprises a reference voltage control unit, a voltage raising unit and a first NMOS transistor, wherein:
the reference voltage control unit is configured to output a control voltage signal to the voltage raising unit based on a reference voltage;
the voltage raising unit is connected to the grid electrode of the first NMOS transistor and configured to output a grid electrode voltage to the grid electrode based on the control voltage signal;
the source of the first NMOS transistor is connected to the output end of the selection switch circuit, and the drain of the first NMOS transistor is connected to a negative charge pump bias voltage.
Illustratively, the voltage raising unit comprises a diode string and a second NMOS transistor, and a first end of the diode string is connected to a source of the second NMOS transistor.
Illustratively, the control voltage signal is connected to a gate of the second NMOS transistor, a drain of the second NMOS transistor being connected to the negative charge pump bias voltage.
Illustratively, the first input terminal of the voltage boost unit is connected to a control signal for controlling the diode string switch, the source of the second NMOS transistor is connected to the output terminal of the voltage boost unit, and the output terminal is connected to the gate of the first NMOS transistor.
Illustratively, the diode string is formed by connecting a plurality of PMOS transistors in series, and in the diode string, the source of the PMOS transistor is connected with the drain of the adjacent PMOS transistor, and the source of each PMOS transistor is connected with the gate.
Exemplarily, the voltage boost unit further comprises a third switch for controlling the diode string switchA PMOS transistor, a control signal for controlling the diode string switch is connected to the gate of the third PMOS transistor, and the drain of the third PMOS transistor is connected to a high power supply voltage VddAnd the source of the third PMOS transistor is connected to the second end of the diode string.
Illustratively, the first input terminal of the reference voltage control unit is connected to a low supply voltage VSSA second input terminal of the reference voltage control unit is connected to a reference voltage VREFAnd the output end of the reference voltage control unit is connected to the grid electrode of the second NMOS transistor.
Illustratively, the first input terminal of the reference voltage control unit is connected to a drain of a third NMOS transistor, the second input terminal of the reference voltage control unit is connected to a gate of the third NMOS transistor, a source of the third NMOS transistor is connected to a source of a first PMOS transistor, a source and a gate of the first PMOS transistor are connected together and to a gate of a second PMOS transistor, a drain of the first PMOS transistor and a drain of the second PMOS transistor are connected together and to a high supply voltage VddThe source of the second PMOS transistor is connected to a first end of another diode string, and a second end of the another diode string is connected to the output end of the reference voltage control unit.
Illustratively, the gate voltage of the first NMOS transistor is a sum of the negative charge pump bias voltage and a product of a number of PMOS transistors in the diode string and a threshold voltage of each of the PMOS transistors.
In one embodiment, the present invention also provides an electronic device including the external dual voltage input selection switch circuit.
According to the invention, when the first NMOS transistor is a medium-voltage device (such as a 3.3V device), the voltage difference between the gate voltage and the substrate voltage of the first NMOS transistor can be controlled to be less than 4V by means of the combined action of the reference voltage control unit and the voltage raising unit, so that the reliability of the first NMOS transistor is improved, and the first NMOS transistor is driven to be a medium-voltage deviceA voltage V output from the drain of the NMOS transistorOUTThe requirements of programming and erasing operations of the NVM memory unit are satisfied.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 is a schematic diagram of a conventional external dual voltage input selection switch circuit;
FIG. 2 is a schematic diagram of an external dual voltage input selection switch circuit according to an exemplary embodiment one of the present invention;
FIG. 3 is a schematic diagram of simulation results obtained from a simulation run of the external dual voltage input selection switch circuit shown in FIG. 2;
fig. 4 is a schematic diagram of an electronic device according to a second exemplary embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that although a transistor may be described using the terms first, second, third, etc. to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The existing internet of things technology applies a medium-voltage device (such as a 3.3V device) with low power consumption to programming and erasing operations of the NVM memory cell, which limits the improvement of the breakdown voltage and gate oxide breakdown characteristics of the NVM memory cell when the NVM memory cell operates under a higher bias condition.
As shown in fig. 1, a schematic diagram of a conventional external dual voltage input selection switch circuit is shown, by which a negative charge pump bias voltage required for programming and erasing operations of an NVM memory cell can be output.
The negative voltage transmission circuit 100 has a first input terminal connected to the operating voltage V, a second input terminal, and an output terminalCCTypically 1.5V, and a second input terminal connected to a negative charge pump bias voltage VNNAnd is typically-6.0V. The output terminal is connected to the gate of the NMOS transistor 101. The drain of the NMOS transistor 101 is connected to a voltage VNNThe source of the NMOS transistor 101 is connected to a voltage VOUTVoltage V ofOUTA negative charge pump bias voltage or other bias voltage for output.
The voltage V to which the first input terminal of the negative voltage transfer circuit 100 is connectedCC1.5V, the voltage V connected to the second input terminal of the negative voltage transmission circuit 100NNand-6.0V, when the generated logic signal of the negative voltage transmitting circuit 100 selects the voltage output from the output terminal to be 1.5V, the voltage difference (bias difference) between the gate and the substrate of the NMOS transistor 101 is 7.5V, and when the generated logic signal of the negative voltage transmitting circuit 100 selects the voltage output from the output terminal to be-6.0V, the voltage difference between the gate and the substrate of the NMOS transistor 101 is 0V.
One end of the diode 102 is connected to a voltage VNNThe other end of the diode 102 is connected to a voltage VCC。
If a high voltage device (e.g., over 5.0V device) is applied to the program and erase operations of the NVM memory cell, a breakdown voltage and a gate oxide breakdown characteristic over 10V can be supported, and even if the value of the voltage difference between the gate and the substrate of the NMOS transistor 101 is more than 7.5V, the operation of the external dual voltage input selection switch circuit does not have any problem.
If a low or medium voltage device is applied to the programming and erasing operations of the NVM memory cell, the transmission value of the negative charge pump bias voltage is too low, resulting in the degradation of the reliability of the device, and the external dual voltage input selection switch circuit cannot be used as the external dual voltage input selection switch circuit in the internet of things process. For example, applying a 3.3V device to program and erase operations of an NVM memory cell, the 3.3V device will not be able to support a voltage difference greater than 4V, thereby affecting the reliability of the NMOS transistor 101, resulting in a V output from the source of the NMOS transistor 101OUTDoes not meet the requirements.
In order to solve the above technical problem, the present invention provides a new external dual-voltage input selection switch circuit, which includes a reference voltage control unit, a voltage raising unit, and a first NMOS transistor, wherein: the reference voltage control unit is configured to output a control voltage signal to the voltage raising unit based on a reference voltage; the voltage raising unit is connected to the grid electrode of the first NMOS transistor and configured to output a grid electrode voltage to the grid electrode based on the control voltage signal; the source of the first NMOS transistor is connected to the output end of the selection switch circuit, and the drain of the first NMOS transistor is connected to a negative charge pump bias voltage.
The voltage raising unit comprises a diode string and a second NMOS transistor, and the first end of the diode string is connected with the source electrode of the second NMOS transistor. The control voltage signal is connected to a gate of the second NMOS transistor, and a drain of the second NMOS transistor is connected to the negative charge pump bias voltage. The first input end of the voltage lifting unit is connected to a control signal for controlling the diode string switch, the source electrode of the second NMOS transistor is connected to the output end of the voltage lifting unit, and the output end of the second NMOS transistor is connected to the grid electrode of the first NMOS transistor. The diode string is formed by connecting a plurality of PMOS transistors in series, and the diode string is formed by connecting a plurality of PMOS transistors in seriesIn the string, the source of the PMOS transistor is connected with the drain of the adjacent PMOS transistor, and the source of each PMOS transistor is connected with the gate. The voltage raising unit further comprises a third PMOS transistor for controlling the diode string switch, a control signal for controlling the diode string switch is connected to a gate of the third PMOS transistor, and a drain of the third PMOS transistor is connected to a high power supply voltage VddAnd the source of the third PMOS transistor is connected to the second end of the diode string.
The first input end of the reference voltage control unit is connected to a low power supply voltage VSSA second input terminal of the reference voltage control unit is connected to a reference voltage VREFAnd the output end of the reference voltage control unit is connected to the grid electrode of the second NMOS transistor. A first input terminal of the reference voltage control unit is connected to a drain of a third NMOS transistor, a second input terminal of the reference voltage control unit is connected to a gate of the third NMOS transistor, a source of the third NMOS transistor is connected to a source of a first PMOS transistor, a source and a gate of the first PMOS transistor are connected together and to a gate of a second PMOS transistor, a drain of the first PMOS transistor and a drain of the second PMOS transistor are connected together and to a high power supply voltage VddThe source of the second PMOS transistor is connected to a first end of another diode string, and a second end of the another diode string is connected to the output end of the reference voltage control unit. The gate voltage of the first NMOS transistor is the sum of the negative charge pump bias voltage and the product of the number of PMOS transistors in the diode string and the threshold voltage of each of the PMOS transistors.
According to the invention, when the first NMOS transistor is a medium-voltage device (such as a 3.3V device), the voltage output by the voltage raising unit to the gate of the first NMOS transistor is-2V to-3V, and by means of the cooperation of the reference voltage control unit and the voltage raising unit, the voltage difference between the gate voltage and the substrate voltage of the first NMOS transistor can be controlled to be less than 4V, so that the reliability of the first NMOS transistor is improved,making a voltage V output from a source of the first NMOS transistorOUTThe requirements of programming and erasing operations of the NVM memory unit are satisfied.
The external dual-voltage input selection switch circuit proposed by the present invention is explained below with reference to an exemplary embodiment to solve the above problems.
[ exemplary embodiment one ]
Referring to fig. 2, there is shown a schematic diagram of an external dual voltage input selection switch circuit according to an exemplary embodiment one of the present invention.
The external dual voltage input selection switch circuit includes a reference voltage control unit 200, a voltage boosting unit 201, and a first NMOS transistor N1.
The reference voltage control unit 200 is used for generating a gate voltage of the second NMOS transistor N2 and controlling a voltage difference between the gate voltage of the first NMOS transistor N1 and a substrate voltage by means of the gate voltage of the second NMOS transistor N2.
The first input terminal (drain of the third NMOS transistor N3) of the reference voltage control unit 200 is connected to the low supply voltage VSSThe second input terminal (the gate of the third NMOS transistor N3) of the reference voltage control unit 200 is connected to the reference voltage VREF(e.g., 1.2V). The source of the third NMOS transistor N3 is connected to the source of the first PMOS transistor P1, the source and gate of the first PMOS transistor P1 are connected together and to the gate of the second PMOS transistor P2, the drain of the first PMOS transistor P1 and the drain of the second PMOS transistor P2 are connected together and to the high supply voltage VddThe source of the second PMOS transistor P2 is connected to the first end of the first diode string (input terminal, drain of the starting PMOS transistor constituting the first diode string), and the second end of the first diode string (output terminal, source of the last PMOS transistor constituting the first diode string) is connected to the output terminal of the reference voltage control unit 200. The first diode string is formed by connecting a plurality of PMOS transistors in series, the number of the PMOS transistors is not limited to three shown in the figure, and can be selected according to actual needs, in the first diode string, the source of the PMOS transistor is connected with the drain of the adjacent PMOS transistor, and the source of each PMOS transistorConnected with the grid. The output terminal of the reference voltage control unit 200 is connected to the gate of the second NMOS transistor N2.
The input terminal of the voltage boost unit 201 (the gate of the third PMOS transistor P3) is connected to a control signal EN (from a control signal commonly used in the art for controlling the switching of the second diode string in the voltage boost unit 201), and the drain of the third PMOS transistor P3 is connected to the high supply voltage VddThe source of the third PMOS transistor P3 is connected to the second end of the second diode string (input, drain of the starting PMOS transistor constituting the second diode string), and the first end of the second diode string (output, source of the last PMOS transistor constituting the second diode string) is connected to the source of the second NMOS transistor N2 and the gate of the first NMOS transistor N1. The second diode string is formed by connecting a plurality of PMOS transistors in series, the number of the PMOS transistors is not limited to three shown in the figure, and may be selected according to actual needs. The output terminal of the voltage boosting unit 201 is connected to the gate of the first NMOS transistor N1.
The voltage raising unit 201 is used for controlling the gate voltage of the first NMOS transistor N1, i.e. the gate voltage of the first NMOS transistor N1 is the negative charge pump bias voltage VNN-6.0V and the product of the number of PMOS transistors in the second diode string and the threshold voltage of each PMOS transistor.
The source of the first NMOS transistor N1 is connected to a voltage VOUTVoltage V ofOUTThe drain of the first NMOS transistor N1 is connected to a negative charge pump bias voltage V for the negative charge pump bias voltage required for the programming and erasing operations of the NVM memory cell output by the external dual voltage input selection switch circuitNN(-6.0V). The drain of the second NMOS transistor N2 is also connected to the voltage VNN(-6.0V)。
According to the external dual voltage input selection switch circuit of the first exemplary embodiment of the present invention, when the first NMOS transistor N1 is a medium voltage device (e.g., 3.3V device), the reference voltage control unit 200 and the voltage raising are used to control the output voltage of the first NMOS transistor N1The boosting unit 201 can control the voltage difference between the gate voltage and the substrate voltage of the first NMOS transistor N1 to be less than 4V, and enhance the reliability of the first NMOS transistor N1, so that the voltage V output from the drain of the first NMOS transistor N1OUTThe requirements of programming and erasing operations of the NVM memory unit are satisfied.
Referring to fig. 3, by simulating the operation of the external dual voltage input selection switch circuit shown in fig. 2, it can be seen that, when the first NMOS transistor N1 is turned on, the voltage V output from the source of the first NMOS transistor N1OUTFor a stable-6.0V, when the first NMOS transistor N1 is turned off, a voltage V output from the source of the first NMOS transistor N1OUTIs a stable floating bias voltage (floating bias).
[ second exemplary embodiment ]
The present invention also provides an electronic device including the external dual voltage input selection switch circuit according to the second exemplary embodiment of the present invention. The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or may be any intermediate product including the external dual-voltage input selection switch circuit.
Wherein figure 4 shows an example of a handset. The exterior of the cellular phone 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like, which are included in a housing 401.
The internal components of the electronic device include the external dual voltage input selection switch circuit described in the second exemplary embodiment, and thus have better performance.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. An external dual-voltage input selection switch circuit, comprising a reference voltage control unit, a voltage raising unit and a first NMOS transistor, wherein:
the reference voltage control unit is configured to output a control voltage signal to the voltage raising unit based on a reference voltage;
the voltage raising unit is connected to the grid electrode of the first NMOS transistor and configured to output a grid electrode voltage to the grid electrode based on the control voltage signal, the voltage raising unit comprises a diode string and a second NMOS transistor, and the first end of the diode string is connected with the source electrode of the second NMOS transistor;
the source of the first NMOS transistor is connected to the output end of the selection switch circuit, and the drain of the first NMOS transistor is connected to a negative charge pump bias voltage.
2. The selection switch circuit of claim 1, wherein the control voltage signal is connected to a gate of the second NMOS transistor, and a drain of the second NMOS transistor is connected to the negative charge pump bias voltage.
3. The selection switch circuit of claim 1, wherein a first input terminal of the voltage boost unit is connected to a control signal for controlling the diode string switch, a source of the second NMOS transistor is connected to an output terminal of the voltage boost unit, and the output terminal is connected to a gate of the first NMOS transistor.
4. The selection switch circuit of claim 1, wherein the diode string is formed by a plurality of PMOS transistors connected in series, wherein in the diode string, the source of the PMOS transistor is connected to the drain of the adjacent PMOS transistor, and the source of each PMOS transistor is connected to the gate.
5. The selection switch circuit of claim 1, wherein the voltage boost unit further comprises a third PMOS transistor for controlling the diode string switch, a control signal for controlling the diode string switch is connected to a gate of the third PMOS transistor, and a drain of the third PMOS transistor is connected to a high supply voltage VddAnd the source of the third PMOS transistor is connected to the second end of the diode string.
6. The selection switch circuit of claim 1, wherein the first input terminal of the reference voltage control unit is connected to a low supply voltage VSSA second input terminal of the reference voltage control unit is connected to a reference voltage VREFAnd the output end of the reference voltage control unit is connected to the grid electrode of the second NMOS transistor.
7. The selection switch circuit of claim 6, wherein the first input terminal of the reference voltage control unit is connected to a drain of a third NMOS transistor, the second input terminal of the reference voltage control unit is connected to a gate of the third NMOS transistor, a source of the third NMOS transistor is connected to a source of a first PMOS transistor, a source and a gate of the first PMOS transistor are connected together and to a gate of a second PMOS transistor, a drain of the first PMOS transistor and a drain of the second PMOS transistor are connected together and to a high supply voltage VddThe source of the second PMOS transistor is connected to a first end of another diode string, and a second end of the another diode string is connected to the output end of the reference voltage control unit.
8. The selection switch circuit of claim 4, wherein the gate voltage of the first NMOS transistor is a sum of the negative charge pump bias voltage and a product of a number of PMOS transistors in the diode string and a threshold voltage of each of the PMOS transistors.
9. An electronic device, characterized in that it comprises an external dual voltage input selection switch circuit according to any one of claims 1-8.
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| CN110262771B (en) * | 2019-05-09 | 2021-07-13 | 中国科学院微电子研究所 | A basic operation circuit based on MOS transistor and its extension circuit |
| CN110391733A (en) * | 2019-08-28 | 2019-10-29 | 芯好半导体(成都)有限公司 | A kind of power supply circuit, power supply method and power supply device |
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| CN101110257A (en) * | 2006-07-18 | 2008-01-23 | 钰创科技股份有限公司 | Negative voltage generator |
| CN102332303A (en) * | 2011-07-13 | 2012-01-25 | 清华大学 | Negative voltage level shifting circuit for flash memory |
| CN102365685A (en) * | 2009-03-31 | 2012-02-29 | 飞思卡尔半导体公司 | Negative voltage generation |
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| JP4989927B2 (en) * | 2006-06-23 | 2012-08-01 | 三星電子株式会社 | Negative potential discharge circuit |
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| US5532915A (en) * | 1994-03-23 | 1996-07-02 | Intel Corporation | Method and apparatus for providing an ultra low power regulated negative charge pump |
| CN101110257A (en) * | 2006-07-18 | 2008-01-23 | 钰创科技股份有限公司 | Negative voltage generator |
| CN102365685A (en) * | 2009-03-31 | 2012-02-29 | 飞思卡尔半导体公司 | Negative voltage generation |
| CN102332303A (en) * | 2011-07-13 | 2012-01-25 | 清华大学 | Negative voltage level shifting circuit for flash memory |
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