CN107465400B - Relaxation oscillator with adjustable temperature coefficient - Google Patents
Relaxation oscillator with adjustable temperature coefficient Download PDFInfo
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- CN107465400B CN107465400B CN201710818402.6A CN201710818402A CN107465400B CN 107465400 B CN107465400 B CN 107465400B CN 201710818402 A CN201710818402 A CN 201710818402A CN 107465400 B CN107465400 B CN 107465400B
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- 230000001105 regulatory effect Effects 0.000 claims abstract description 12
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 8
- 238000009966 trimming Methods 0.000 description 8
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0231—Astable circuits
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Abstract
The invention discloses a temperature coefficient adjustable relaxation oscillator, which comprises a reference voltage generation circuit BGP, a regulated power supply circuit LDO and an oscillator circuit OSC, wherein the reference voltage generation circuit BGP is connected with the regulated power supply circuit LDO, the regulated power supply circuit LDO is connected with the oscillator circuit, the reference voltage generation circuit BGP comprises a voltage comparator A0, a resistor R1 and a transistor V1, the oscillator circuit OSC comprises an amplifier A1, transistors V2-V6, comparators CM1 and CM2, current sources I1-I3, capacitors C1 and C2 and NAND gates U1 and U2.
Description
Technical Field
The invention relates to a relaxation oscillator, in particular to a relaxation oscillator with an adjustable temperature coefficient.
Background
The oscillator plays a very important role in MCU, and is commonly used for system clock timing and the like. Although the crystal oscillator has a high frequency stability, i.e., a small voltage coefficient and temperature coefficient. But it is inconvenient to integrate with peripheral devices by either increasing the number of PADs. Relaxation oscillation can realize full internal integration, and the realization formulas are two:
these two formulas correspond to different solutions, respectively. The first is to generate a reference current and a reference voltage, the reference current charges the capacitor when the capacitor voltage reaches V REF The time is half a period, and the charging current and the reference voltage have higher temperature coefficient and voltage coefficientHigher precision. The second current is generated by reference voltage, ">
As can be seen from the formula, the frequency does not change with the voltage, the temperature coefficient of the resistor can be formed into a resistor with smaller temperature coefficient according to a certain proportion by the resistors with positive temperature coefficient and negative temperature coefficient, thus realizing lower temperature coefficient, and the method has the advantages that a high-precision V is not necessarily needed REF . The two schemes do not consider the influence of time delay and process change along with temperature on frequency, the time delay duty ratio of a circuit is larger and larger along with the higher frequency, and the working state of a comparator in the circuit and other circuits are influenced by voltage, temperature and process, so that the precision of the frequency is influenced. The novel temperature trimming scheme is provided on the structure of the basic relaxation oscillator, trimming can be performed according to the specific condition of each chip, and the output frequency precision and the product yield are improved.
Disclosure of Invention
The invention aims to provide a relaxation oscillator with adjustable temperature coefficient so as to solve the problems in the background art.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the relaxation oscillator with the adjustable temperature coefficient comprises a reference voltage generating circuit BGP, a regulated power supply circuit LDO and an oscillator circuit OSC, and is characterized in that the reference voltage generating circuit BGP is connected with the regulated power supply circuit LDO, and the regulated power supply circuit LDO is connected with the oscillator circuit. The LDO circuit includes a voltage comparator A0, a resistor string R1, and a transistor V1, the oscillator circuit OSC includes an amplifier A1, comparators CM1 and CM2, current sources I1, I2, and I3, resistors R2, transistors V1, V2, V3, V4, V5, V6, capacitors C1 and C2, and nand gates U1 and U2. The forward end of the voltage amplifier A0 is connected with the output end of the reference voltage generating circuit BGP, the reverse end of the voltage amplifier A0 is connected with the resistor string R1, the output end of the voltage comparator A0 is connected with the grid electrode of the transistor V1, the source electrode of the transistor V1 is connected with the power supply, the drain electrode of the transistor V1 is connected with the resistor string R1 and outputs the voltage VLDO, the resistor string R1 also respectively outputs signals VREF1 and VREF2, the signal VREF1 is connected with the forward end of the amplifier A1, the reverse end of the amplifier A1 is connected with the resistor R2 and the source electrode of the transistor V2, the output end of the comparator A1 is connected with the grid electrode of the transistor V2, the drain electrode of the transistor V2 is connected with the voltage VLDO through the current source I1, the voltage VLDO is also connected with the transistor V3 and the transistor V5 through the current sources I2 and I3, (Q1 and Q2 represent the output of U1 and U2, not representing transistors) transistors V3 and V4 are also connected to the inverting terminal of comparator CM1 and capacitor C1, the forward terminal of comparator CM1 is connected to the inverting terminal of comparator CM2 and to VREF1, the inverting terminal of comparator CM2 is connected to capacitor C2 and to the drain terminals of transistors V5 and V6, the output terminal of comparator CM1 is connected to one input terminal of nand gate U1, the output terminal of comparator CM2 is connected to one input terminal of nand gate U2, the output terminal Q1 of nand gate U1 is connected to the other input terminal of nand gate U2 and to the gate terminals of V3 and V4, the output terminal Q2 of nand gate U2 is connected to the other input terminal of nand gate U1 and to the input terminals of nor gate U3 and the gate terminals of V5 and V6, and the output terminal of nor gate U3 is connected to the level conversion circuit.
As a further technical scheme of the invention: the nominal value of the voltage VLDO is 2.4V.
Compared with the prior art, the invention has the beneficial effects that: the invention can independently modify the temperature coefficient of each chip on the basis of the original temperature, solves the problems that the duty ratio of delay in frequency is larger and larger when the relaxation oscillator is applied to high-frequency design, and the delay is influenced by temperature and technology, so that the temperature coefficient difference between the chips is larger, thereby improving the chip yield.
Drawings
Fig. 1 is a block diagram of the present invention.
Fig. 2 is a key node waveform diagram.
Fig. 3 is a graph of frequency versus temperature for the case of I2 alone.
Fig. 4 is a graph of frequency voltage variation.
Fig. 5 is a graph showing the frequency temperature change after I3 is increased.
Fig. 6 is a circuit diagram of an I3 implementation.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A relaxation oscillator with adjustable temperature coefficient comprises a reference voltage generating circuit BGP, a regulated power supply circuit LDO and an oscillator circuit OSC, wherein the reference voltage generating circuit BGP is connected with the regulated power supply circuit LDO, and the regulated power supply circuit LDO is connected with the oscillator circuit. The LDO circuit includes a voltage comparator A0, a resistor string R1, and a transistor V1, the oscillator circuit OSC includes an amplifier A1, comparators CM1 and CM2, current sources I1, I2, and I3, resistors R2, transistors V1, V2, V3, V4, V5, V6, capacitors C1 and C2, and nand gates U1 and U2. The forward end of the voltage amplifier A0 is connected with the output end of the reference voltage generating circuit BGP, the reverse end of the voltage amplifier A0 is connected with the resistor string R1, the output end of the voltage comparator A0 is connected with the grid electrode of the transistor V1, the source electrode of the transistor V1 is connected with the power supply, the drain electrode of the transistor V1 is connected with the resistor string R1 and outputs the voltage VLDO, the resistor string R1 also respectively outputs signals VREF1 and VREF2, the signal VREF1 is connected with the forward end of the amplifier A1, the reverse end of the amplifier A1 is connected with the resistor R2 and the source electrode of the transistor V2, the output end of the comparator A1 is connected with the grid electrode of the transistor V2, the drain electrode of the transistor V2 is connected with the voltage VLDO through the current source I1, the voltage VLDO is also connected with the transistor V3 and the transistor V5 through the current sources I2 and I3, the drain terminals of the transistors V3 and V4 are also connected with the reverse terminal of the comparator CM1 and the capacitor C1, the forward terminal of the comparator CM1 is connected with the forward terminal of the comparator CM2 and is connected with VREF1, the reverse terminal of the comparator CM2 is connected with the capacitor C2 and the drain terminals of the transistors V5 and V6, the output terminal of the comparator CM1 is connected with one input terminal of the NAND gate U1, the output terminal Q1 of the NAND gate U1 is connected with the other input terminal of the NAND gate U2 and the gate terminals of V3 and V4, the output terminal Q2 of the NAND gate U2 is connected with the other input terminal of the NAND gate U1 and the input terminals of the NAND gate U3 and the gate terminals of V5 and V6, and the output terminal of the NAND gate U3 is connected with the level conversion circuit.
The voltage VLDO is rated at 2.4V.
The working principle of the invention is as follows: BGP generates a reference voltage which does not change with temperature and power supply voltage, provides reference voltage for LDO, and outputs 2.4V for OSC to supply power to the OSC part, and the voltage is very stable, so that the frequency of the oscillator can realize higher voltage coefficient. Since VBG is a lower temperature coefficient voltage, VREF1 and VREF2 are also lower temperature coefficient voltages. R2 can be a low temperature coefficient resistor or a combination of a positive temperature coefficient resistor and a negative temperature coefficient resistor according to a certain proportion to obtain the low temperature coefficient resistor. I 1 And I 2 Is a current mirror, I 2 Is a capacitor C 1 And C 2 By adjusting the charging current of I 2 Thereby effecting an adjustment of the frequency. So the frequency is
K is I 1 And I 2 The ratio of the current mirror. Both the capacitance and the resistance have a low temperature coefficient, and the frequency does not change with temperature and with supply voltage if the delay time is not taken into account. However, the working states of the comparator and the logic gate are affected by temperature, and a certain temperature coefficient exists in the capacitance and the resistance, and the actual frequency is +.>
The higher the frequency +.>
Smaller (less)>
The larger the temperature coefficient at frequency will eventually be reflected. R2 is a positive temperature coefficient resistor or a single low temperature coefficient resistor obtained by proportionally connecting a positive temperature coefficient resistor and a negative temperature coefficient resistor in series. FIGS. 3, 4 and 5 are simulations of a relaxation oscillator designed on a 0.18um process with an output frequency of 20MHzTrue data. Fig. 3 shows that the frequency varies with temperature only at I2, the maximum variation range of the frequency is between-0.82% and 0.14%, and some process angle variations are about-0.4%, and it can be seen that the frequency increases with temperature, and negative temperature coefficient current needs to be introduced. Fig. 4 shows the frequency change with temperature after increasing I3, which ranges from-0.42% to 0, and it can be seen that the frequency change with temperature is approximately halved and parabolic, and only changes by 0.08% in the range of 0 to 50 degrees. It can be seen that the temperature characteristics of the frequency can be greatly improved after the introduction of I3.
The implementation of I3 is shown in fig. 6. The entire module is powered by the LDO, VREF2 from the LDO in FIG. 1. MP1-MP5, mn1-Mn3 and C3 form an operational amplifier, C3 is a compensation capacitor, mn5 is a source follower, MP6-MP8 and Mn4-Mn6 are switching tubes, A, B and C are current mirrors, the corresponding tubes are the same in size, the currents of each path are equal, A has 32 paths in total, B has 1 path, C has 31 paths, and the current I3 consists of B and C together. C includes 5-way trim ports TC0_TC4.EN is the enable terminal, active high. R3 is a positive temperature coefficient resistor, and R4 is a negative temperature coefficient resistor. SelR is a resistance selection port, S2 is high when the SelR is high, mn5 is opened, R3 is short-circuited by Mn5, mn6 is turned off, at the moment, R4 is connected into a circuit, because of the negative feedback resistance formed by the operational amplifier, the voltage at the upper end of R4 is VREF2, otherwise, selR is low, two ends of R4 are short-circuited by Mn6, and the voltage at the upper ends of two ends of R3 is VREF2. So the total current flowing through the current mirror A is
Since the current mirror A has 32 paths in total, the current flowing in each path is +.>
B. C and A are mirror image tubing and the tube sizes of each are the same. Thus (2)
N is an integer of 1 to 31 depending on the difference in the high and low potentials of tc0_tc4. It can be seen how much the minimum induced trimming current is controlled by the number of A paths, while the total induced current is controlled by TC0_tc4 trimming end control. The temperature characteristic of the output frequency is only related to the capacitor C1 and the resistor R2 according to the frequency formula, but the temperature characteristic of the frequency is not completely related to the capacitor C1 and the resistor R2 because the delay and the process are affected by the temperature due to the delay and the process change. At this point I3 can be introduced as desired. R3 is a resistor with positive temperature coefficient, R4 is a resistor with negative temperature coefficient, when the frequency is high along with the height of the power voltage, selR is connected with the resistor with high R4 to generate a current with negative temperature coefficient +.>
I3 is conversely connected with R3 to generate a positive temperature coefficient current +.>
The level of TC0-TC4 is adjusted according to the change of the frequency along with the power supply voltage, when TC0-TC4 are all 0, I3 is +.>
Maximum i3=i A The increment per step is +.>
The trimming is characterized in that R2 is a small temperature coefficient resistor or a combination of a positive temperature coefficient resistor and a negative temperature coefficient resistor, so that a current I3 for trimming the frequency temperature coefficient is introduced on the basis, and the maximum value and the minimum value of the I3 are adjustable. Fig. 3 shows the temperature coefficient without I3, the frequency of which increases with increasing temperature, and the degree of variation is different for each process corner. To compensate for this, a very small and negative temperature coefficient current must be introduced. To achieve this, the SelR terminal is low, R3 is connected, and R4 is shorted. The small temperature coefficient current is realized through a current mirror, the number of paths of the current mirror A part can be set according to actual needs, and under the condition that R3, R4 and VREF2 are already set, the more the number of paths is, the smaller the current flowing through each path in the current mirror A is, namely the smaller the temperature coefficient introduced in each step is, the design value of the patent is 32, and the requirement is thatHow much current is introduced can be achieved through the TC0-TC4 trimming ports, and fig. 5 is a temperature characteristic of the trimmed frequency, and it can be seen that the frequency is significantly smaller with temperature change. Therefore, the circuit structure can realize the independent trimming of the temperature characteristic of each chip frequency, reduces the temperature coefficient of the frequency and improves the product yield. />
Claims (2)
1. A temperature coefficient adjustable relaxation oscillator comprises a reference voltage generation circuit BGP, a regulated power supply circuit LDO and an oscillator circuit OSC, and is characterized in that the reference voltage generation circuit BGP is connected with the regulated power supply circuit LDO, the regulated power supply circuit LDO is connected with the oscillator circuit, the LDO circuit comprises a voltage comparator A0, a resistor string R1 and a transistor V1, the oscillator circuit OSC comprises an amplifier A1, comparators CM1 and CM2, current sources I1, I2 and I3, a resistor R2, transistors V1, V2, V3, V4, V5 and V6, capacitors C1 and C2, NAND gates U1 and U2, the forward end of a voltage amplifier A0 is connected with the output end of the reference voltage generation circuit BGP, the reverse end of the voltage amplifier A0 is connected with a resistor string R1, the output end of the voltage comparator A0 is connected with the gate of the transistor V1, the source of the transistor V1 is connected with the power supply, the drain of the transistor V1 is connected with the resistor string R1 and outputs a voltage DO, the resistor string R1 also outputs signals VREF1 and VREF2 respectively, the signal VREF1 is connected with the forward end of the amplifier A1, the reverse end of the amplifier A1 is connected with the resistor R2 and the source electrode of the transistor V2, the output end of the comparator A1 is connected with the grid electrode of the transistor V2, the drain electrode of the transistor V2 is connected with the voltage VLDO through a current source I1, the voltage VLDO is also connected with the transistor V3 and the transistor V5 through current sources I2 and I3, the drain ends of the transistors V3 and V4 are also connected with the reverse end of the comparator CM1 and the capacitor C1, the forward end of the comparator CM1 is connected with the forward end of the comparator CM2 and is connected with the VREF1, the reverse end of the comparator CM2 is connected with the drain ends of the transistors V5 and V6, the output end of the comparator CM1 is connected with one input end of the NAND gate U1, the output end Q1 of the NAND gate U2 is connected with the other input end of the NAND gate U2 and the gate ends of V3 and V4, the output end Q2 of the NAND gate U2 is connected with the other input end of the NAND gate U1, the input end of the NAND gate U3 and the grid ends of V5 and V6, and the output end of the NAND gate U3 is connected with the level conversion circuit.
2. A temperature-coefficient-adjustable relaxation oscillator according to claim 1, characterized in that the voltage VLDO is rated at 2.4V.
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| CN107465400B true CN107465400B (en) | 2023-04-28 |
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| CN109787558B (en) * | 2018-12-28 | 2023-04-11 | 合肥中感微电子有限公司 | Oscillator circuit and trimming method thereof |
| CN111478669A (en) * | 2020-04-13 | 2020-07-31 | 上海芯跳科技有限公司 | High-precision circuit for RC oscillator |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101977035A (en) * | 2010-11-19 | 2011-02-16 | 无锡灿星科技有限公司 | Temperature compensation offset eliminated RC oscillator |
| CN201887731U (en) * | 2010-09-25 | 2011-06-29 | 苏州华芯微电子股份有限公司 | Adjustable high-precision RC oscillating circuit |
| WO2015172555A1 (en) * | 2014-05-12 | 2015-11-19 | 国家电网公司 | Frequency control method and circuit for ring oscillator |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201887731U (en) * | 2010-09-25 | 2011-06-29 | 苏州华芯微电子股份有限公司 | Adjustable high-precision RC oscillating circuit |
| CN101977035A (en) * | 2010-11-19 | 2011-02-16 | 无锡灿星科技有限公司 | Temperature compensation offset eliminated RC oscillator |
| WO2015172555A1 (en) * | 2014-05-12 | 2015-11-19 | 国家电网公司 | Frequency control method and circuit for ring oscillator |
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