CN107465217A - A kind of switching mode lithium battery charging circuit and chip without current sampling resistor - Google Patents
A kind of switching mode lithium battery charging circuit and chip without current sampling resistor Download PDFInfo
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- CN107465217A CN107465217A CN201610395747.0A CN201610395747A CN107465217A CN 107465217 A CN107465217 A CN 107465217A CN 201610395747 A CN201610395747 A CN 201610395747A CN 107465217 A CN107465217 A CN 107465217A
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- 238000005070 sampling Methods 0.000 title claims abstract description 141
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 title claims abstract description 62
- 229910052744 lithium Inorganic materials 0.000 title claims abstract description 62
- 230000000630 rising effect Effects 0.000 claims abstract description 11
- 238000004088 simulation Methods 0.000 claims description 30
- 230000005611 electricity Effects 0.000 claims description 22
- HCUOEKSZWPGJIM-YBRHCDHNSA-N (e,2e)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N/O)\C(N)=O HCUOEKSZWPGJIM-YBRHCDHNSA-N 0.000 claims description 12
- 101001109689 Homo sapiens Nuclear receptor subfamily 4 group A member 3 Proteins 0.000 claims description 12
- 101000598778 Homo sapiens Protein OSCP1 Proteins 0.000 claims description 12
- 101001067395 Mus musculus Phospholipid scramblase 1 Proteins 0.000 claims description 12
- 102100022673 Nuclear receptor subfamily 4 group A member 3 Human genes 0.000 claims description 12
- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 claims description 12
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 claims description 12
- 102100031024 CCR4-NOT transcription complex subunit 1 Human genes 0.000 claims description 9
- 102100031025 CCR4-NOT transcription complex subunit 2 Human genes 0.000 claims description 9
- 102100031033 CCR4-NOT transcription complex subunit 3 Human genes 0.000 claims description 9
- 101000919674 Caenorhabditis elegans CCR4-NOT transcription complex subunit let-711 Proteins 0.000 claims description 9
- 101001092183 Drosophila melanogaster Regulator of gene activity Proteins 0.000 claims description 9
- 101000919672 Homo sapiens CCR4-NOT transcription complex subunit 1 Proteins 0.000 claims description 9
- 101000919667 Homo sapiens CCR4-NOT transcription complex subunit 2 Proteins 0.000 claims description 9
- 101000919663 Homo sapiens CCR4-NOT transcription complex subunit 3 Proteins 0.000 claims description 9
- 102100032981 CCR4-NOT transcription complex subunit 4 Human genes 0.000 claims description 6
- 101000942594 Homo sapiens CCR4-NOT transcription complex subunit 4 Proteins 0.000 claims description 6
- 101100294409 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) NOT5 gene Proteins 0.000 claims description 6
- 230000003321 amplification Effects 0.000 claims description 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000010295 mobile communication Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Classifications
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- H02J7/0072—
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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- Electronic Switches (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The present invention is applied to lithium battery charging circuit field, there is provided a kind of switching mode lithium battery charging circuit and chip without current sampling resistor.The present invention sets an anticipation circuit and a sampling hold circuit by extra in traditional switching mode lithium battery charging circuit, 0.5 times time trigger of the logic control circuit in the conducting period of on-off circuit is prejudged circuit and send a rising edge signal to sampling hold circuit, triggering sampling hold circuit is sampled and kept to the sampled voltage signal that current sampling circuit exports and exports a current signal, and the current signal is converted to after voltage signal by the generation error voltage compared with reference voltage by reference current sampled signal amplifying circuit, logic control circuit is set to adjust the dutycycle of the ON time of on-off circuit according to the error voltage, to realize, in the case where not needing sampling resistor, controlling switch circuit carries out constant-current charge to lithium battery.
Description
Technical field
The invention belongs to lithium battery charging circuit field, more particularly to a kind of switch without current sampling resistor
Type lithium battery charging circuit and chip.
Background technology
With the continuous popularization of the mobile communication equipments such as smart mobile phone, tablet personal computer, the public moves for these
The endurance of communication apparatus requires also more and more higher.Lithium battery is with its small volume, energy density is high, without note
The advantages that property recalled as mobile communication equipment preferred supplying cell.
At present, generally use constant current switch charging circuit charges to lithium battery, however, existing constant current
Switched charge circuit needs to enter the charging current of lithium battery by the very high sampling resistor of a resistance accuracy
Row monitoring, the sampling resistor cost is higher, adds by the overall hardware of the electronic equipment of lithium battery power supply
Cost and reduce charge efficiency.
The content of the invention
It is an object of the invention to provide a kind of switching mode lithium battery charging circuit without current sampling resistor,
Aim to solve the problem that existing constant current switch charging circuit is needed by the very high sampling resistor pair of a resistance accuracy
The charging current of lithium battery is monitored, and the sampling resistor cost is higher, adds by lithium battery power supply
The overall hardware cost of electronic equipment and the problem of reduce charge efficiency.
The present invention is achieved in that a kind of switching mode lithium battery charging circuit without current sampling resistor,
The switching mode lithium battery charging circuit includes on-off circuit, current sampling circuit, inductance L, electric current and turns electricity
Volt circuit, anticipation circuit, sampling hold circuit, reference current sampled signal amplifying circuit, constant current constant voltage are cut
Change circuit, PWM comparators, logic control circuit, reference voltage sampled signal amplifying circuit and compensation electricity
Road；
The first input end of the input of the on-off circuit and the current sampling circuit is connected to external electrical altogether
Source, the output end of the on-off circuit and the second input of the current sampling circuit are connected to inductance L's altogether
One end, the positive pole of inductance L another termination lithium battery；
The output of the current sampling circuit terminates the input of the current-to-voltage converting circuit；
The output of the current-to-voltage converting circuit terminates the input of the sampling hold circuit；
The output of the sampling hold circuit terminates the first input of the reference current sampled signal amplifying circuit
End, the first logic signal input end of the sampling hold circuit connect the logical signal output of the anticipation circuit
End, the second logic signal input end of the sampling hold circuit and the logical signal of the anticipation circuit input
End is connected to the logical signal output end of the logic control circuit, the enabled input of the sampling hold circuit altogether
The enabled input of end and the anticipation circuit is connected to the enabled output end of the logic control circuit altogether；
The input termination external power source of the anticipation circuit, the output termination lithium battery of the anticipation circuit is just
Pole, the reference voltage input input reference voltage of the anticipation circuit；
Second input termination external power source of the reference current sampled signal amplifying circuit is electric to produce benchmark
Pressure, the output of the reference current sampled signal amplifying circuit terminate the first of the constant current constant voltage switching circuit
Input；
The first input end of the reference voltage sampled signal amplifying circuit connects external power source to produce benchmark electricity
Pressure, the second input of the reference voltage sampled signal amplifying circuit terminates the positive pole of the lithium battery, described
The output of reference voltage sampled signal amplifying circuit terminates the second input of the constant pressure and flow switching circuit；
The output of the constant current constant voltage switching circuit terminates the positive input terminal of the PWM comparators, described
The negative input of PWM comparators terminates the compensation circuit；
The output of the PWM comparators singly connects the input of the logic control circuit, the logic control
The output of circuit terminates the controlled end of the on-off circuit；
When the on-off circuit turns on, the current sampling circuit sampling flows into the sampling electricity of the inductance L
Flow signal, the electric current turns potential circuit the sampled current signals are converted into sampled voltage signal to be sent to
The sampling hold circuit；
At 0.5 times of moment of the conducting period of the on-off circuit, the logic control circuit triggering is described pre-
Sentence circuit and send a rising edge signal to the sampling hold circuit, make the sampling hold circuit to described
Sampled voltage signal is sampled and kept and export a current signal to put to the reference current sampled signal
Big circuit；
The current signal is converted to voltage signal and the base by the reference current sampled signal amplifying circuit
Quasi- voltage produces error voltage after being compared, the error voltage through the constant current constant voltage switching circuit and
PWM comparators are transferred to the logic control circuit, and the logic control circuit is according to the error voltage
The dutycycle of the ON time of the on-off circuit is adjusted, to control the on-off circuit to export constant charging
Electric current gives the charging of the lithium battery.
Preferably, the anticipation circuit includes the first logic device, NOT gate NOT1, NOT gate NOT2 or non-
Door NOR1, the first amplifier, the second amplifier, the 3rd amplifier, PMOS Q1~Q5, NMOS
Pipe Q6~Q11, resistance R1~R6 and electric capacity C1；
The signal input part of first logic device connects external power source, the clock signal terminal of first logic device
For the logic signal input end of the anticipation circuit, the signal output termination NOT gate of first logic device
NOT1 input, the enabled termination nor gate NOR1 of first logic device output end；
The grid of NOT gate NOT1 output end, PMOS Q1 grid and NMOS tube Q6 connects altogether；
The PMOS Q1 drain electrode of source electrode, PMOS Q2 and NMOS tube Q7 drain electrode connects altogether, PMOS
Positive pole and the first amplifier with electric capacity C1 respectively after pipe Q1 drain electrode and NMOS tube Q6 drain electrode connect altogether
Positive input connection, electric capacity C1 negative pole connects simulation ground；
NMOS tube Q6 source electrode connects NMOS tube Q8 drain electrode；
PMOS Q2 grid, PMOS Q3 grid, PMOS Q3 drain electrode and NMOS
Pipe Q9 drain electrode connects altogether, and PMOS Q2 source electrode and PMOS Q3 source electrode are connected to external power source altogether；
NMOS tube Q7 grid, NMOS tube Q8 grid, NMOS tube Q10 grid and PMOS
Pipe Q4 drain electrode connects altogether, NMOS tube Q7 source electrode, NMOS tube Q8 source electrode and NMOS tube Q10
Source electrode connect simulation ground；
NMOS tube Q9 grid connects the output end of the second amplifier, NMOS tube Q9 source electrode and second
The reverse input end of amplifier and resistance R1 one end connect altogether, resistance R1 another termination simulation ground；
PMOS Q4 grid, PMOS Q5 grid, PMOS Q5 drain electrode and NMOS
Pipe Q11 drain electrode connects altogether, and PMOS Q4 source electrode and PMOS Q5 source electrode are connected to external electrical altogether
Source；
NMOS tube Q11 grid connects the output end of the 3rd amplifier, NMOS tube Q11 source electrode,
The inverting input of three amplifiers and resistance R2 one end connect altogether, resistance R2 another termination simulation ground；
Nor gate NOR1 first input end connects NOT gate NOT2 output end, and the second of nor gate NOR1
The output end of input and the first amplifier connects the logical signal output end for forming the anticipation circuit, NOT gate altogether
NOT2 input is the enabled input for prejudging circuit；
The reverse input end of first amplifier is the reference voltage input for prejudging circuit；
The positive input of second amplifier connects altogether with resistance R3 one end and resistance R4 one end, resistance
The R3 other end is the input for prejudging circuit, and the resistance R4 other end is grounded, wherein, resistance R3
It is equal with resistance R4 resistance；
The positive input of 3rd amplifier and one end of resistance R5 one end and resistance R6 connect altogether, resistance
The R5 other end is the output end for prejudging circuit, and the resistance R6 other end is grounded, wherein, resistance R6
Resistance be three times of resistance of resistance R5；
Before being turned on after 0.5 times of moment of the conducting period of the on-off circuit to the on-off circuit,
The output end output current of the anticipation circuit makes electric capacity C1 discharge, and electric capacity C1 initial voltage is equal to described
Reference voltage；
At 0.5 times of moment of conducting start time to the conducting period of the on-off circuit of the on-off circuit
Before, the input input current of the anticipation circuit charges to electric capacity C1；
After electric capacity C1 charges, when its capacitance voltage is equal to the reference voltage again, the anticipation circuit
Judge 0.5 times of moment of the now conducting period for the on-off circuit, its logical signal output end is to described
Sampling hold circuit sends a rising edge signal.
Preferably, the sampling hold circuit includes the second logic device, NOT gate NOT3~NOT8 and door
AND1, anti-phase Schmidt trigger ST1, anti-phase Schmidt trigger ST2, nor gate NOR2, with it is non-
Door NAND1, resistance R7, resistance R8, electric capacity C2~C5, PMOS Q12, PMOS Q13,
NMOS tube Q14~Q16, switch S1 and switch S2；
The signal input part of second logic device connects external power source, signal output part, the NOT gate of the second logic device
NOT3 input, PMOS Q12 grid, NMOS tube Q14 grid and with door AND1
First input end connect altogether, the clock signal terminal of the second logic device is the first logic of the sampling hold circuit
Signal input part, the enabled termination nor gate NOR2 of the second logic device output end, NOT gate NOT3's is defeated
Go out the controlling of sampling end that end forms the sampling hold circuit；
PMOS Q12 source electrode connects external power source, the draining of PMOS Q12, anti-phase schmidt trigger
The positive pole of device ST1 input, resistance R7 one end and electric capacity C2 connects altogether；
The drain electrode connecting resistance R7 of NMOS tube 14 other end, source electrode and the electric capacity C2 of NMOS tube 14
Negative pole be connected to altogether simulation ground；
With door AND1 the second input termination NOT gate NOT4 output end, the output with door AND1 terminates
NOT gate NOT5 input, NOT gate NOT5 output end form the holding control of the sampling hold circuit
End, the NOT gate NOT4 reversed phase Schmidt trigger ST1 of input output end；
Nor gate NOR2 first input end connects NOT gate NOT6 output end, and the second of nor gate NOR2
Input termination NOT gate NOT7 output end, NOT gate NOT7 input make for the sampling hold circuit
Can input；
NOT gate NOT6 input termination NAND gate NAND1 output end, the first of NAND gate NAND1
Input termination NOT gate NOT8 output end, NAND gate NAND` the second input, PMOS Q13
Grid and NMOS tube Q15 grid connect altogether form the sampling hold circuit the second logical signal it is defeated
Enter end；
NOT gate NOT8 input termination Schmidt trigger ST2 output end, Schmidt trigger ST2's
The drain electrode of input, electric capacity C3 positive pole, resistance R8 one end and PMOS Q13 connects altogether, PMOS
Pipe Q13 source electrode connects external power source；
The NMOS tube Q15 drain electrode connecting resistance R8 other end, NMOS tube Q15 source electrode and electric capacity
C3 negative pole is connected to simulation ground altogether；
The one end for switching S1 is the input of the sampling hold circuit, switchs the S1 other end, electric capacity C4
Positive pole and switch S2 one end connect altogether；
The switch S2 other end, electric capacity C5 positive pole and NMOS tube Q16 grid connects altogether, NMOS
Pipe Q16's drains as the output end of the sampling hold circuit, electric capacity C4 negative pole, electric capacity C5 negative pole
Simulation ground is connected to altogether with NMOS tube Q16 source electrode；
In the conducting start time of the on-off circuit, the sampling hold circuit receives the anticipation electricity
The rising edge signal on road, the controlling of sampling end trigger switch S1 closures, now switch S2 and disconnect, sampling
The input input electric current of holding circuit turns the sampled voltage signal that potential circuit exports and filled to electric capacity C4
Electricity；
At 0.5 times of moment of the conducting period of the on-off circuit, the controlling of sampling end trigger switch S1 breaks
Open, now electric capacity C4 is stored with the sampled current signals corresponding to 0.5 times of moment；
Before being turned on after 0.5 times of moment of the conducting period of the on-off circuit to the on-off circuit,
The holding control terminal trigger switch S2 closures, make electric capacity C4 be charged to electric capacity C5, when electric capacity C4 electricity
When pressure is equal with electric capacity C5 voltage, the holding control terminal trigger switch S2 disconnects, and deposits electric capacity C5
The sampled current signals corresponding to 0.5 times of moment are stored up, the sampled current signals are through NMOS tube Q16
Export to the reference current sampled signal amplifying circuit.
Preferably, the reference current sampled signal amplifying circuit is included by the first equivalent current source, NMOS
The reference current that pipe Q17, NMOS tube Q18, PMOS Q19 and PMOS Q20 are formed produces
Unit；
The input of first equivalent current source and PMOS Q19 source electrode and PMOS Q20's
Source electrode connects the input for forming the reference current sampled signal amplifying circuit, first equivalent current source altogether
Output end and NMOS tube Q17 drain electrode, NMOS tube Q17 grid and NMOS tube Q18
Grid connects altogether, and NMOS tube Q17 source electrode and NMOS tube Q18 source electrode are connected to simulation ground altogether；
PMOS Q19 grid, PMOS Q20 grid, PMOS Q19 drain electrode and NMOS
Pipe Q18 drain electrode connects altogether, and PMOS Q20 drain electrode is the reference current sampled signal amplifying circuit
First input end and output end；
First equivalent current source produces a reference current and flows through PMOS Q20, the reference current and
The sampled current signals of sampling hold circuit output by PMOS Q20 and NMOS tube Q16 it
Between equivalent resistance form error voltage and export to the constant current constant voltage switching circuit.
Preferably, the reference current sampled signal amplifying circuit includes error amplifier and reference voltage produces
Unit；The reference voltage generation unit includes the second equivalent current source, NMOS tube Q21, NMOS tube
Q22, resistance R9 and resistance R10；
The positive input of the error amplifier and resistance R9 one end connect the composition reference current and adopted altogether
The first input end of sample signal amplification circuit, the reverse input end of the error amplifier and the one of resistance R10
The drain electrode at end and NMOS tube Q21 is connect altogether, and the output end of the error amplifier is adopted for the reference current
The output end of sample signal amplification circuit；
The other end of the input of second equivalent current source and the resistance R9 other end and resistance R10 is total to
The second input for forming the reference current sampled signal amplifying circuit is connect, second equivalent current source
Output end and NMOS tube Q21 drain electrode, NMOS tube Q21 grid and NMOS tube Q22 grid
Extremely connect altogether, NMOS tube Q21 source electrode and NMOS tube Q22 source electrode are connected to simulation ground altogether；
Second equivalent current source produces a reference current and flows through resistance R10, makes to produce on resistance R10
Reference voltage is exported to the reverse input end of the error amplifier, the sampling of the sampling hold circuit output
Current signal is converted into voltage signal by resistance R9, and the error amplifier is to the voltage signal and institute
The difference stated between reference voltage is amplified, and is cut so as to produce error voltage and export to the constant current constant voltage
Change circuit.
Preferably, the electric current, which turns potential circuit, includes NMOS tube Q23, NMOS tube Q23 drain electrode
Input and output end that the electric current turns potential circuit, NMOS tube Q23 source are formed after being connected with grid
Pole connects simulation ground；
NMOS tube Q23 drain electrode, which inputs the sampled current signals and is converted to sampled voltage signal, passes through it
Grid is exported to the sampling hold circuit.
Preferably, the on-off circuit includes PMOS Q24 and diode D1；
PMOS Q24 grid is the controlled end of the on-off circuit, and PMOS Q24 drain electrode is institute
The input of on-off circuit is stated, PMOS Q24 source electrode connects described in composition altogether with diode D1 negative pole
The output end of on-off circuit, diode D1 plus earth.
Preferably, the on-off circuit also includes NMOS tube Q25；
NMOS tube Q25 grid is another controlled end of the on-off circuit, NMOS tube Q25's
Drain electrode connects the source electrode of the PMOS Q24, NMOS tube Q25 source ground.
Preferably, the switching mode lithium battery charging circuit also includes resistance R11, resistance R12 and electric capacity C6；
Resistance R11 one end, electric capacity C6 positive pole, the inductance L other end are connected to the positive pole of lithium battery altogether,
The resistance R11 other end, resistance R12 one end and the second of the reference voltage sampled signal amplifying circuit
Input connects altogether, and resistance the R12 other end, electric capacity C6 negative pole and the negative pole of lithium battery are connected to ground altogether.
The present invention also provides a kind of switching mode lithium cell charging chip without current sampling resistor, the switch
Type lithium cell charging chip includes the switching mode lithium battery charging circuit as described in preceding any one.
Compared with prior art, its advantage is the present invention：
By setting an anticipation circuit and a sampling hold circuit, make logic control circuit in on-off circuit
Conducting the period 0.5 times of time trigger prejudge circuit to sampling hold circuit send a rising edge signal,
Triggering sampling hold circuit is sampled and kept and exported to the sampled voltage signal that current sampling circuit exports
One current signal, and the current signal is converted to by voltage by reference current sampled signal amplifying circuit
After signal compared with reference voltage generation error voltage, enable logic control circuit according to the error
The dutycycle of the ON time of voltage control switch circuit, controlled with realizing in the case where not needing sampling resistor
On-off circuit processed carries out constant-current charge to lithium battery.
Brief description of the drawings
Fig. 1 is the switching mode lithium battery charging circuit provided in an embodiment of the present invention without current sampling resistor
Basic structure block diagram；
Fig. 2 is the switching mode lithium battery charging circuit provided in an embodiment of the present invention without current sampling resistor
Concrete structure block diagram；
Fig. 3 is the circuit theory diagrams of anticipation circuit provided in an embodiment of the present invention；
Fig. 4 is that electric current provided in an embodiment of the present invention turns voltage cell, sampling hold circuit and reference current and adopted
The circuit theory diagrams of sample signal amplification circuit；
Fig. 5 is the circuit theory diagrams of reference current sampled signal amplifying circuit provided in an embodiment of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with accompanying drawing and reality
Example is applied, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only
To explain the present invention, it is not intended to limit the present invention.
As shown in figure 1, the switching mode lithium battery charging circuit without current sampling resistor that the present embodiment provides
Turn potential circuit 30, anticipation circuit including on-off circuit 10, current sampling circuit 20, inductance L, electric current
40th, sampling hold circuit 50, reference current sampled signal amplifying circuit 60, constant current constant voltage switching circuit 70,
PWM comparators 80, logic control circuit 90, reference voltage sampled signal amplifying circuit 00 and compensation electricity
Road 01.
The input of on-off circuit 10 and the first input end of current sampling circuit 20 are connected to external power source altogether
VIN, the output end of on-off circuit 10 are connected to inductance L's altogether with the second input of current sampling circuit 20
One end, inductance L another termination lithium battery BAT positive pole；
The input of the output termination current-to-voltage converting circuit 30 of current sampling circuit 20；
The input of the output termination sampling hold circuit 50 of current-to-voltage converting circuit 30；
The first input end of the output termination reference current sampled signal amplifying circuit 60 of sampling hold circuit 50,
First logic signal input end of sampling hold circuit 50 connects the logical signal output end of anticipation circuit 40, adopts
Second logic signal input end of sample holding circuit 50 is connected to altogether with prejudging the logic signal input end 40 of circuit
The logical signal output end of logic control circuit 90, enabled input and the anticipation electricity of sampling hold circuit 50
The enabled input on road 40 is connected to the enabled output end of logic control circuit 90 altogether；
The input termination external power source VIN of circuit 40 is prejudged, the output termination lithium battery of anticipation circuit 40
Positive pole, prejudge the reference voltage input input reference voltage of circuit 40；
Second input of reference current sampled signal amplifying circuit 60 terminates external power source to produce reference voltage,
The first input end of the output termination constant current constant voltage switching circuit 70 of reference current sampled signal amplifying circuit 60；
The first input end of reference voltage sampled signal amplifying circuit 00 connects external power source to produce reference voltage,
Second input termination lithium battery BAT of reference voltage sampled signal amplifying circuit 00 positive pole, reference voltage
Second input of the output termination constant pressure and flow switching circuit 70 of sampled signal amplifying circuit 00；
The positive input terminal of the output termination PWM comparators 80 of constant current constant voltage switching circuit 70, PWM compare
The negative input termination compensation circuit 01 of device 80；
The output of PWM comparators 80 singly connects the input of logic control circuit 90, logic control circuit 90
Output termination on-off circuit 10 controlled end；
In the present embodiment, on-off circuit 10 includes PMOS Q24 and diode D1；PMOS
Q24 grid is the controlled end of on-off circuit 10, and PMOS Q24 drain electrode is the defeated of on-off circuit 10
Entering end, PMOS Q24 source electrode connects the output end for forming on-off circuit 10 with diode D1 negative pole altogether,
Diode D1 plus earth.
When on-off circuit 10 turns on, the sampling of current sampling circuit 20 flows into inductance L sampled current signals,
Electric current turns potential circuit 30 sampled current signals is converted into sampled voltage signal to be sent to sampling hold circuit
50；
At 0.5 times of moment of the conducting period of on-off circuit, the triggering anticipation circuit 40 of logic control circuit 90
A rising edge signal is sent to sampling hold circuit 50, makes sampling hold circuit 50 to sampled voltage signal
Sampled and kept and export a current signal to reference current sampled signal amplifying circuit 60；
Current signal is converted to voltage signal and entered with reference voltage by reference current sampled signal amplifying circuit 60
Error voltage is produced after row, the error voltage is through constant current constant voltage switching circuit 70 and PWM comparators
80 are transferred to logic control circuit 90, and logic control circuit 90 adjusts on-off circuit according to the error voltage
The dutycycle of 10 ON time, constant charging current is exported with controlling switch circuit 10 and gives lithium battery BAT
Charging.
As shown in Fig. 2 the switching mode lithium cell charging electricity without current sampling resistor provided in the present embodiment
Road also includes resistance R11, resistance R12 and electric capacity C6；Resistance R11 one end, electric capacity C6 positive pole,
The inductance L other end is connected to the positive pole of lithium battery altogether, the resistance R11 other end, resistance R12 one end with
Second input of reference voltage sampled signal amplifying circuit 00 connects altogether, resistance the R12 other end, electric capacity
C6 negative pole and lithium battery BAT negative pole are connected to ground altogether.
On-off circuit 10 also includes NMOS tube Q25, and NMOS tube Q25 grid is on-off circuit 10
Another controlled end, NMOS tube Q25 drain electrode meets the source electrode of the PMOS Q24, NMOS
Pipe Q25 source ground.
Reference current sampled signal amplifying circuit 60 includes error amplifier 61 and reference voltage generation unit
62, wherein, the positive input of error amplifier 61 is as reference current sampled signal amplifying circuit 60
Input is connected with the output end of sampling hold circuit 50, and the output end of error amplifier 61 is as benchmark electricity
The output end of stream sampled signal amplifying circuit 60 is connected with the input for the constant pressure switch unit that flows over；Reference voltage
The output end of generation unit 62 is connected with the reverse input end of error amplifier 61, for inputting external power source
To produce reference voltage.
The power tube that logic control circuit 90 includes logic unit 91, is connected with the output end of logic unit 91
Driver element 92 and the oscillator 93 being connected with logic unit 91, wherein, the first of logic unit 91
Input is the input of logic control circuit 90, and the Enable Pin of logic unit 91 is logic control circuit 90
Enabled output end, the logical signal end of power tube driver element 92 is believed for the logic of logic control circuit 90
Number output end, the second input of the output termination logic unit 91 of oscillator 93, is logic unit 91
Clock signal is provided.
Reference voltage sampled signal amplifying circuit 00 includes error amplifier 001 and reference voltage generation unit
002, wherein, the reverse input end of error amplifier 001 is as reference voltage sampled signal amplifying circuit 00
The second input, the output end of error amplifier 001 is as reference voltage sampled signal amplifying circuit 00
Output end with flow over constant pressure switch unit input be connected；The output end of reference voltage generation unit 002
It is connected with the positive input of error amplifier 001, for inputting external power source to produce reference voltage.
Compensation circuit 01 has gathered current sample, slope compensation and bias current overlaying function.
As shown in figure 3, in the present embodiment, anticipation circuit 40 include the first logic device 41, NOT gate NOT1,
NOT gate NOT2, nor gate NOR1, the first amplifier 42, the second amplifier 43, the 3rd amplifier 44,
PMOS Q1~Q5, NMOS tube Q6~Q11, resistance R1~R6 and electric capacity C1.
The signal input part D of first logic device 41 connects external power source VDD, the clock of the first logic device 41
Signal end CLK is the logic signal input end Power_PMOS_Turn_ON_Logic of anticipation circuit 40,
The signal output part Q of first logic device 41 connects NOT gate NOT1 input, and the first logic device 41 enables
EndConnect nor gate NOR1 output end；
The grid of NOT gate NOT1 output end, PMOS Q1 grid and NMOS tube Q6 connects altogether；
The PMOS Q1 drain electrode of source electrode, PMOS Q2 and NMOS tube Q7 drain electrode connects altogether, PMOS
Positive pole and the first amplifier with electric capacity C1 respectively after pipe Q1 drain electrode and NMOS tube Q6 drain electrode connect altogether
42 positive input connection, electric capacity C1 negative pole connect simulation ground；
NMOS tube Q6 source electrode connects NMOS tube Q8 drain electrode；
PMOS Q2 grid, PMOS Q3 grid, PMOS Q3 drain electrode and NMOS
Pipe Q9 drain electrode connects altogether, and PMOS Q2 source electrode and PMOS Q3 source electrode are connected to external power source altogether
VDD；
NMOS tube Q7 grid, NMOS tube Q8 grid, NMOS tube Q10 grid and PMOS
Pipe Q4 drain electrode connects altogether, NMOS tube Q7 source electrode, NMOS tube Q8 source electrode and NMOS tube Q10
Source electrode connect simulation ground；
NMOS tube Q9 grid connects the output end of the second amplifier 43, NMOS tube Q9 source electrode and
The reverse input end of two amplifiers 43 and resistance R1 one end connect altogether, resistance R1 another termination simulation ground；
PMOS Q4 grid, PMOS Q5 grid, PMOS Q5 drain electrode and NMOS
Pipe Q11 drain electrode connects altogether, and PMOS Q4 source electrode and PMOS Q5 source electrode are connected to external electrical altogether
Source VDD；
NMOS tube Q11 grid connects the output end of the 3rd amplifier 44, NMOS tube Q11 source electrode,
The inverting input of 3rd amplifier 44 and resistance R2 one end connect altogether, resistance R2 another termination simulation
Ground；
Nor gate NOR1 first input end connects NOT gate NOT2 output end, and the second of nor gate NOR1
The output end of input and the first amplifier 42 connects the logical signal output end for forming anticipation circuit 40 altogether
OUT, NOT gate NOT2 input are the enabled input Enable of anticipation circuit 40；
The reverse input end of first amplifier 42 is the reference voltage input V of anticipation circuit 40Initial；
The positive input of second amplifier 43 and one end of resistance R3 one end and resistance R4 connect altogether, electricity
The other end for hindering R3 is the input VIN of anticipation circuit 40, and the resistance R4 other end is grounded, wherein,
Resistance R3 and resistance R4 resistance are equal；
The positive input of 3rd amplifier 44 and one end of resistance R5 one end and resistance R6 connect altogether, electricity
The other end for hindering R5 is the output end VOUT of anticipation circuit 40, and the resistance R6 other end is grounded, wherein,
Resistance R6 resistance is three times of resistance R5 resistance；
Before being turned on after 0.5 times of moment of the conducting period of on-off circuit 10 to on-off circuit 10, in advance
Sentencing the output end output current of circuit 40 makes electric capacity C1 discharge, and electric capacity C1 initial voltage is equal to benchmark electricity
Pressure；
On-off circuit 10 conducting start time to on-off circuit 10 turn on the period 0.5 times of moment it
Before, the input input current for prejudging circuit 40 charges to electric capacity C1；
After electric capacity C1 charges, when its capacitance voltage is equal to reference voltage again, anticipation circuit 40 judges this
When for on-off circuit 10 the conducting period 0.5 times of moment, its logical signal output end is to sampling hold circuit
50 send a rising edge signal.
As shown in Fig. 4 or Fig. 5, current sampling circuit 20 an equivalent current source-representation, the equivalent electric
The input and output end in stream source are respectively the input and output end of the current sampling circuit 20, and electric current is adopted
Sample circuit 20 samples to the current signal of external power source, and output sampled current signals Isense to electric current turns
The input of potential circuit 30.
As shown in Fig. 4 or Fig. 5, electric current, which turns potential circuit 30, includes NMOS tube Q23, NMOS tube Q23
Drain electrode be connected with grid after form electric current and turn the input and output end of potential circuit 30, NMOS tube Q23
Source electrode connect simulation ground；
NMOS tube Q23 drain electrode inputs the sampled current signals Isense and is converted to sampled voltage signal
Exported by its grid to sampling hold circuit 50.
As shown in figure 4, sampling hold circuit 50 include the second logic device 51, NOT gate NOT3~NOT8,
With door AND1, anti-phase Schmidt trigger ST1, anti-phase Schmidt trigger ST2, nor gate NOR2,
NAND gate NAND1, resistance R7, resistance R8, electric capacity C2~C5, PMOS Q12, PMOS
Q13, NMOS tube Q14~Q16, switch S1 and switch S2；
The signal input part D of second logic device 51 connects external power source VDD, the signal of the second logic device 51
Output end Q, NOT gate NOT3 input, PMOS Q12 grid, NMOS tube Q14 grid
Pole and connect altogether with door AND1 first input end, the clock signal terminal CLK of the second logic device 51 is described
First logic signal input end of sampling hold circuit 50, the Enable Pin of the second logic device 51Connect nor gate
NOR2 output end, NOT gate NOT3 output end form the controlling of sampling end of the sampling hold circuit 50
Sample；
PMOS Q12 source electrode meets external power source VDD, the draining of PMOS Q12, it is anti-phase apply it is close
The positive pole of special trigger ST1 input, resistance R7 one end and electric capacity C2 connects altogether；
The NMOS tube Q14 drain electrode connecting resistance R7 other end, source electrode and the electric capacity C2 of NMOS tube 14
Negative pole be connected to altogether simulation ground；
With door AND1 the second input termination NOT gate NOT4 output end, the output with door AND1 terminates
NOT gate NOT5 input, NOT gate NOT5 output end form the holding of the sampling hold circuit 50
Control terminal Charge, NOT gate the NOT4 reversed phase Schmidt trigger ST1 of input output end；
Nor gate NOR2 first input end connects NOT gate NOT6 output end, and the second of nor gate NOR2
Input termination NOT gate NOT7 output end, NOT gate NOT7 input is the sampling hold circuit 50
Enabled input Enable；
NOT gate NOT6 input termination NAND gate NAND1 output end, the first of NAND gate NAND1
Input termination NOT gate NOT8 output end, NAND gate NAND` the second input, PMOS Q13
Grid and NMOS tube Q15 grid connect the second logical signal for forming the sampling hold circuit 50 altogether
Input Power_PMOS_Turn_ON_Logic；
NOT gate NOT8 input termination Schmidt trigger ST2 output end, Schmidt trigger ST2's
The drain electrode of input, electric capacity C3 positive pole, resistance R8 one end and PMOS Q13 connects altogether, PMOS
Pipe Q13 source electrode connects external power source；
The NMOS tube Q15 drain electrode connecting resistance R8 other end, NMOS tube Q15 source electrode and electric capacity
C3 negative pole is connected to simulation ground altogether；
The one end for switching S1 is the input of the sampling hold circuit 50, switchs the S1 other end, electricity
One end of the positive pole and switch S2 that hold C4 connects altogether；
The switch S2 other end, electric capacity C5 positive pole and NMOS tube Q16 grid connects altogether, NMOS
Pipe Q16 drain electrode is the output end of the sampling hold circuit 50, electric capacity C4 negative pole, electric capacity C5
Negative pole and NMOS tube Q16 source electrode are connected to simulation ground altogether；
In the conducting start time of on-off circuit 10, sampling hold circuit 50 receives anticipation circuit 40
Rising edge signal, controlling of sampling end Sample trigger switch S1 closure, now switch S2 and break
Open, the input input current of sampling hold circuit 50 turn sampled voltage signal that potential circuit 30 exports to
Electric capacity C4 charges；
At 0.5 times of moment of the conducting period of on-off circuit 10, the controlling of sampling end Sample triggerings are opened
Close S1 to disconnect, now electric capacity C4 is stored with the sampled current signals corresponding to 0.5 times of moment；
Before being turned on after 0.5 times of moment of the conducting period of on-off circuit 10 to on-off circuit 10, institute
State and keep control terminal Charge trigger switch S2 closures, electric capacity C4 is charged to electric capacity C5, work as electric capacity
When C4 voltage is equal with electric capacity C5 voltage, the holding control terminal Charge trigger switch S2 disconnects,
Electric capacity C5 is set to store the sampled current signals corresponding to 0.5 times of moment, the sampled current signals warp
NMOS tube Q16 is exported to reference current sampled signal amplifying circuit 60.
As shown in figure 4, reference current sampled signal amplifying circuit 60 includes error amplifier 61 and benchmark electricity
Press generation unit 62；Reference voltage generation unit 62 include the second equivalent current source 621, NMOS tube Q21,
NMOS tube Q22, resistance R9 and resistance R10；
The positive input of error amplifier 61 connects and forms reference current sampled signal altogether with resistance R9 one end
The first input end of amplifying circuit 60, the reverse input end of error amplifier 61 and resistance R10 one end and
NMOS tube Q21 drain electrode connects altogether, and current sampling signal amplifies on the basis of the output end of error amplifier 61
The output end of circuit 60；
The other end of the input of second equivalent current source 621 and the resistance R9 other end and resistance R10 is total to
Connect the second input for forming reference current sampled signal amplifying circuit 60, the second equivalent current source 621 it is defeated
Go out end and NMOS tube Q21 drain electrode, NMOS tube Q21 grid and NMOS tube Q22 grid
Connect altogether, NMOS tube Q21 source electrode and NMOS tube Q22 source electrode are connected to simulation ground altogether；
Second equivalent current source 621 produces a reference current and flows through resistance R10, makes to produce on resistance R10
Reference voltage is exported to the reverse input end of error amplifier, the sampled current signals of sampling hold circuit output
Be converted into voltage signal by resistance R9, error amplifier to the voltage signal and the reference voltage it
Between difference be amplified, give constant current constant voltage switching circuit so as to produce error voltage and export.
As shown in figure 5, in the present embodiment, reference current sampled signal amplifying circuit 60 is included by first etc.
Imitate current source 63, NMOS tube Q17, NMOS tube Q18, PMOS Q19 and PMOS Q20
The reference current generation unit of composition；
The source of the input of first equivalent current source 63 and PMOS Q19 source electrode and PMOS Q20
Extremely connect the input for forming reference current sampled signal amplifying circuit 60 altogether, the first equivalent current source 63 it is defeated
Go out end and NMOS tube Q17 drain electrode, NMOS tube Q17 grid and NMOS tube Q18 grid
Connect altogether, NMOS tube Q17 source electrode and NMOS tube Q18 source electrode are connected to simulation ground altogether；
PMOS Q19 grid, PMOS Q20 grid, PMOS Q19 drain electrode and NMOS
Pipe Q18 drain electrode connects altogether, current sampling signal amplifying circuit 60 on the basis of PMOS Q20 drain electrode
First input end and output end；
First equivalent current source 63 produce a reference current flow through PMOS Q20, the reference current and
The sampled current signals that sampling hold circuit 50 exports pass through between PMOS Q20 and NMOS tube Q16
Equivalent resistance form error voltage and export to constant current constant voltage switching circuit 70.
The embodiment of the present invention also provides a kind of switching mode lithium cell charging chip without current sampling resistor, bag
Include foregoing switching mode lithium battery charging circuit.In a particular application, on-off circuit can be arranged on institute
State outside switching mode lithium cell charging chip, the switching mode lithium cell charging chip internal can also be integrated in.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in this hair
All any modification, equivalent and improvement made within bright spirit and principle etc., should be included in the present invention
Protection domain within.
Claims (10)
1. a kind of switching mode lithium battery charging circuit without current sampling resistor, it is characterised in that described to open
Pass type lithium battery charging circuit includes on-off circuit, current sampling circuit, inductance L, electric current turn potential circuit,
Prejudge circuit, sampling hold circuit, reference current sampled signal amplifying circuit, constant current constant voltage switching circuit,
PWM comparators, logic control circuit, reference voltage sampled signal amplifying circuit and compensation circuit；
The first input end of the input of the on-off circuit and the current sampling circuit is connected to external electrical altogether
Source, the output end of the on-off circuit and the second input of the current sampling circuit are connected to inductance L's altogether
One end, the positive pole of inductance L another termination lithium battery；
The output of the current sampling circuit terminates the input of the current-to-voltage converting circuit；
The output of the current-to-voltage converting circuit terminates the input of the sampling hold circuit；
The output of the sampling hold circuit terminates the first input of the reference current sampled signal amplifying circuit
End, the first logic signal input end of the sampling hold circuit connect the logical signal output of the anticipation circuit
End, the second logic signal input end of the sampling hold circuit and the logical signal of the anticipation circuit input
End is connected to the logical signal output end of the logic control circuit, the enabled input of the sampling hold circuit altogether
The enabled input of end and the anticipation circuit is connected to the enabled output end of the logic control circuit altogether；
The input termination external power source of the anticipation circuit, the output termination lithium battery of the anticipation circuit is just
Pole, the reference voltage input input reference voltage of the anticipation circuit；
Second input termination external power source of the reference current sampled signal amplifying circuit is electric to produce benchmark
Pressure, the output of the reference current sampled signal amplifying circuit terminate the first of the constant current constant voltage switching circuit
Input；
The first input end of the reference voltage sampled signal amplifying circuit connects external power source to produce benchmark electricity
Pressure, the second input of the reference voltage sampled signal amplifying circuit terminates the positive pole of the lithium battery, described
The output of reference voltage sampled signal amplifying circuit terminates the second input of the constant pressure and flow switching circuit；
The output of the constant current constant voltage switching circuit terminates the positive input terminal of the PWM comparators, described
The negative input of PWM comparators terminates the compensation circuit；
The output of the PWM comparators singly connects the input of the logic control circuit, the logic control
The output of circuit terminates the controlled end of the on-off circuit；
When the on-off circuit turns on, the current sampling circuit sampling flows into the sampling electricity of the inductance L
Flow signal, the electric current turns potential circuit the sampled current signals are converted into sampled voltage signal to be sent to
The sampling hold circuit；
At 0.5 times of moment of the conducting period of the on-off circuit, the logic control circuit triggering is described pre-
Sentence circuit and send a rising edge signal to the sampling hold circuit, make the sampling hold circuit to described
Sampled voltage signal is sampled and kept and export a current signal to put to the reference current sampled signal
Big circuit；
The current signal is converted to voltage signal and the base by the reference current sampled signal amplifying circuit
Quasi- voltage produces error voltage after being compared, the error voltage through the constant current constant voltage switching circuit and
PWM comparators are transferred to the logic control circuit, and the logic control circuit is according to the error voltage
The dutycycle of the ON time of the on-off circuit is adjusted, to control the on-off circuit to export constant charging
Electric current gives the charging of the lithium battery.
2. the switching mode lithium battery charging circuit without current sampling resistor as claimed in claim 1, it is special
Sign is, the anticipation circuit include the first logic device, NOT gate NOT1, NOT gate NOT2, nor gate NOR1,
First amplifier, the second amplifier, the 3rd amplifier, PMOS Q1~Q5, NMOS tube Q6~Q11,
Resistance R1~R6 and electric capacity C1；
The signal input part of first logic device connects external power source, the clock signal terminal of first logic device
For the logic signal input end of the anticipation circuit, the signal output termination NOT gate of first logic device
NOT1 input, the enabled termination nor gate NOR1 of first logic device output end；
The grid of NOT gate NOT1 output end, PMOS Q1 grid and NMOS tube Q6 connects altogether；
The PMOS Q1 drain electrode of source electrode, PMOS Q2 and NMOS tube Q7 drain electrode connects altogether, PMOS
Positive pole and the first amplifier with electric capacity C1 respectively after pipe Q1 drain electrode and NMOS tube Q6 drain electrode connect altogether
Positive input connection, electric capacity C1 negative pole connects simulation ground；
NMOS tube Q6 source electrode connects NMOS tube Q8 drain electrode；
PMOS Q2 grid, PMOS Q3 grid, PMOS Q3 drain electrode and NMOS
Pipe Q9 drain electrode connects altogether, and PMOS Q2 source electrode and PMOS Q3 source electrode are connected to external power source altogether；
NMOS tube Q7 grid, NMOS tube Q8 grid, NMOS tube Q10 grid and PMOS
Pipe Q4 drain electrode connects altogether, NMOS tube Q7 source electrode, NMOS tube Q8 source electrode and NMOS tube Q10
Source electrode connect simulation ground；
NMOS tube Q9 grid connects the output end of the second amplifier, NMOS tube Q9 source electrode and second
The reverse input end of amplifier and resistance R1 one end connect altogether, resistance R1 another termination simulation ground；
PMOS Q4 grid, PMOS Q5 grid, PMOS Q5 drain electrode and NMOS
Pipe Q11 drain electrode connects altogether, and PMOS Q4 source electrode and PMOS Q5 source electrode are connected to external electrical altogether
Source；
NMOS tube Q11 grid connects the output end of the 3rd amplifier, NMOS tube Q11 source electrode,
The inverting input of three amplifiers and resistance R2 one end connect altogether, resistance R2 another termination simulation ground；
Nor gate NOR1 first input end connects NOT gate NOT2 output end, and the second of nor gate NOR1
The output end of input and the first amplifier connects the logical signal output end for forming the anticipation circuit, NOT gate altogether
NOT2 input is the enabled input for prejudging circuit；
The reverse input end of first amplifier is the reference voltage input for prejudging circuit；
The positive input of second amplifier connects altogether with resistance R3 one end and resistance R4 one end, resistance
The R3 other end is the input for prejudging circuit, and the resistance R4 other end is grounded, wherein, resistance R3
It is equal with resistance R4 resistance；
The positive input of 3rd amplifier and one end of resistance R5 one end and resistance R6 connect altogether, resistance
The R5 other end is the output end for prejudging circuit, and the resistance R6 other end is grounded, wherein, resistance R6
Resistance be three times of resistance of resistance R5；
Before being turned on after 0.5 times of moment of the conducting period of the on-off circuit to the on-off circuit,
The output end output current of the anticipation circuit makes electric capacity C1 discharge, and electric capacity C1 initial voltage is equal to described
Reference voltage；
At 0.5 times of moment of conducting start time to the conducting period of the on-off circuit of the on-off circuit
Before, the input input current of the anticipation circuit charges to electric capacity C1；
After electric capacity C1 charges, when its capacitance voltage is equal to the reference voltage again, the anticipation circuit
Judge 0.5 times of moment of the now conducting period for the on-off circuit, its logical signal output end is to described
Sampling hold circuit sends a rising edge signal.
3. the switching mode lithium battery charging circuit without current sampling resistor as claimed in claim 1, it is special
Sign is, the sampling hold circuit include the second logic device, NOT gate NOT3~NOT8, with door AND1,
Anti-phase Schmidt trigger ST1, anti-phase Schmidt trigger ST2, nor gate NOR2, NAND gate NAND1,
Resistance R7, resistance R8, electric capacity C2~C5, PMOS Q12, PMOS Q13, NMOS tube
Q14~Q16, switch S1 and switch S2；
The signal input part of second logic device connects external power source, signal output part, the NOT gate of the second logic device
NOT3 input, PMOS Q12 grid, NMOS tube Q14 grid and with door AND1
First input end connect altogether, the clock signal terminal of the second logic device is the first logic of the sampling hold circuit
Signal input part, the enabled termination nor gate NOR2 of the second logic device output end, NOT gate NOT3's is defeated
Go out the controlling of sampling end that end forms the sampling hold circuit；
PMOS Q12 source electrode connects external power source, the draining of PMOS Q12, anti-phase schmidt trigger
The positive pole of device ST1 input, resistance R7 one end and electric capacity C2 connects altogether；
The drain electrode connecting resistance R7 of NMOS tube 14 other end, source electrode and the electric capacity C2 of NMOS tube 14
Negative pole be connected to altogether simulation ground；
With door AND1 the second input termination NOT gate NOT4 output end, the output with door AND1 terminates
NOT gate NOT5 input, NOT gate NOT5 output end form the holding control of the sampling hold circuit
End, the NOT gate NOT4 reversed phase Schmidt trigger ST1 of input output end；
Nor gate NOR2 first input end connects NOT gate NOT6 output end, and the second of nor gate NOR2
Input termination NOT gate NOT7 output end, NOT gate NOT7 input make for the sampling hold circuit
Can input；
NOT gate NOT6 input termination NAND gate NAND1 output end, the first of NAND gate NAND1
Input termination NOT gate NOT8 output end, NAND gate NAND` the second input, PMOS Q13
Grid and NMOS tube Q15 grid connect altogether form the sampling hold circuit the second logical signal it is defeated
Enter end；
NOT gate NOT8 input termination Schmidt trigger ST2 output end, Schmidt trigger ST2's
The drain electrode of input, electric capacity C3 positive pole, resistance R8 one end and PMOS Q13 connects altogether, PMOS
Pipe Q13 source electrode connects external power source；
The NMOS tube Q15 drain electrode connecting resistance R8 other end, NMOS tube Q15 source electrode and electric capacity
C3 negative pole is connected to simulation ground altogether；
The one end for switching S1 is the input of the sampling hold circuit, switchs the S1 other end, electric capacity C4
Positive pole and switch S2 one end connect altogether；
The switch S2 other end, electric capacity C5 positive pole and NMOS tube Q16 grid connects altogether, NMOS
Pipe Q16's drains as the output end of the sampling hold circuit, electric capacity C4 negative pole, electric capacity C5 negative pole
Simulation ground is connected to altogether with NMOS tube Q16 source electrode；
In the conducting start time of the on-off circuit, the sampling hold circuit receives the anticipation electricity
The rising edge signal on road, the controlling of sampling end trigger switch S1 closures, now switch S2 and disconnect, sampling
The input input electric current of holding circuit turns the sampled voltage signal that potential circuit exports and filled to electric capacity C4
Electricity；
At 0.5 times of moment of the conducting period of the on-off circuit, the controlling of sampling end trigger switch S1 breaks
Open, now electric capacity C4 is stored with the sampled current signals corresponding to 0.5 times of moment；
Before being turned on after 0.5 times of moment of the conducting period of the on-off circuit to the on-off circuit,
The holding control terminal trigger switch S2 closures, make electric capacity C4 be charged to electric capacity C5, when electric capacity C4 electricity
When pressure is equal with electric capacity C5 voltage, the holding control terminal trigger switch S2 disconnects, and deposits electric capacity C5
The sampled current signals corresponding to 0.5 times of moment are stored up, the sampled current signals are through NMOS tube Q16
Export to the reference current sampled signal amplifying circuit.
4. the switching mode lithium battery charging circuit without current sampling resistor as claimed in claim 3, it is special
Sign is that the reference current sampled signal amplifying circuit is included by the first equivalent current source, NMOS tube
The reference current generation unit that Q17, NMOS tube Q18, PMOS Q19 and PMOS Q20 are formed；
The input of first equivalent current source and PMOS Q19 source electrode and PMOS Q20's
Source electrode connects the input for forming the reference current sampled signal amplifying circuit, first equivalent current source altogether
Output end and NMOS tube Q17 drain electrode, NMOS tube Q17 grid and NMOS tube Q18
Grid connects altogether, and NMOS tube Q17 source electrode and NMOS tube Q18 source electrode are connected to simulation ground altogether；
PMOS Q19 grid, PMOS Q20 grid, PMOS Q19 drain electrode and NMOS
Pipe Q18 drain electrode connects altogether, and PMOS Q20 drain electrode is the reference current sampled signal amplifying circuit
First input end and output end；
First equivalent current source produces a reference current and flows through PMOS Q20, the reference current and
The sampled current signals of sampling hold circuit output by PMOS Q20 and NMOS tube Q16 it
Between equivalent resistance form error voltage and export to the constant current constant voltage switching circuit.
5. the switching mode lithium battery charging circuit without current sampling resistor as claimed in claim 1, it is special
Sign is that the reference current sampled signal amplifying circuit includes error amplifier and reference voltage generation unit；
The reference voltage generation unit include the second equivalent current source, NMOS tube Q21, NMOS tube Q22,
Resistance R9 and resistance R10；
The positive input of the error amplifier and resistance R9 one end connect the composition reference current and adopted altogether
The first input end of sample signal amplification circuit, the reverse input end of the error amplifier and the one of resistance R10
The drain electrode at end and NMOS tube Q21 is connect altogether, and the output end of the error amplifier is adopted for the reference current
The output end of sample signal amplification circuit；
The other end of the input of second equivalent current source and the resistance R9 other end and resistance R10 is total to
The second input for forming the reference current sampled signal amplifying circuit is connect, second equivalent current source
Output end and NMOS tube Q21 drain electrode, NMOS tube Q21 grid and NMOS tube Q22 grid
Extremely connect altogether, NMOS tube Q21 source electrode and NMOS tube Q22 source electrode are connected to simulation ground altogether；
Second equivalent current source produces a reference current and flows through resistance R10, makes to produce on resistance R10
Reference voltage is exported to the reverse input end of the error amplifier, the sampling of the sampling hold circuit output
Current signal is converted into voltage signal by resistance R9, and the error amplifier is to the voltage signal and institute
The difference stated between reference voltage is amplified, and is cut so as to produce error voltage and export to the constant current constant voltage
Change circuit.
6. the switching mode lithium battery without current sampling resistor as described in claim 1 or 4 or 5 any one
Charging circuit, it is characterised in that the electric current, which turns potential circuit, includes NMOS tube Q23, NMOS tube
Q23 drain electrode forms the input and output end that the electric current turns potential circuit, NMOS after being connected with grid
Pipe Q23 source electrode connects simulation ground；
NMOS tube Q23 drain electrode, which inputs the sampled current signals and is converted to sampled voltage signal, passes through it
Grid is exported to the sampling hold circuit.
7. the switching mode lithium battery charging circuit without current sampling resistor as claimed in claim 1, it is special
Sign is that the on-off circuit includes PMOS Q24 and diode D1；
PMOS Q24 grid is the controlled end of the on-off circuit, and PMOS Q24 drain electrode is institute
The input of on-off circuit is stated, PMOS Q24 source electrode connects described in composition altogether with diode D1 negative pole
The output end of on-off circuit, diode D1 plus earth.
8. the switching mode lithium battery charging circuit without current sampling resistor as claimed in claim 7, it is special
Sign is that the on-off circuit also includes NMOS tube Q25；
NMOS tube Q25 grid is another controlled end of the on-off circuit, NMOS tube Q25's
Drain electrode connects the source electrode of the PMOS Q24, NMOS tube Q25 source ground.
9. the switching mode lithium battery charging circuit without current sampling resistor as claimed in claim 1, it is special
Sign is that the switching mode lithium battery charging circuit also includes resistance R11, resistance R12 and electric capacity C6；
Resistance R11 one end, electric capacity C6 positive pole, the inductance L other end are connected to the positive pole of lithium battery altogether,
The resistance R11 other end, resistance R12 one end and the second of the reference voltage sampled signal amplifying circuit
Input connects altogether, and resistance the R12 other end, electric capacity C6 negative pole and the negative pole of lithium battery are connected to ground altogether.
10. a kind of switching mode lithium cell charging chip without current sampling resistor, it is characterised in that described to open
Pass type lithium cell charging chip includes the switching mode lithium cell charging electricity as described in any one of claim 1~9
Road.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111224446A (en) * | 2020-02-26 | 2020-06-02 | 湖南品腾电子科技有限公司 | Lithium battery charging circuit |
| CN113922683A (en) * | 2021-09-26 | 2022-01-11 | 西北工业大学 | Single-stage wireless charging circuit based on digital rectifier |
| CN113933671A (en) * | 2021-09-01 | 2022-01-14 | 郑州嘉晨电器有限公司 | MOS device temperature detection device |
| CN115882700A (en) * | 2023-03-08 | 2023-03-31 | 合肥乘翎微电子有限公司 | Control circuit of direct current-direct current converter with wide conversion ratio |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013113236A1 (en) * | 2012-02-03 | 2013-08-08 | 无锡华润上华半导体有限公司 | Secondary battery charging device |
| CN103378617A (en) * | 2012-04-18 | 2013-10-30 | 钰泰科技（上海）有限公司 | Lithium battery charging circuit |
| CN103401420A (en) * | 2013-07-03 | 2013-11-20 | 西安电子科技大学 | Adaptive turn-on time generation circuit applied to DC-DC converter |
| CN103457320A (en) * | 2013-08-22 | 2013-12-18 | 电子科技大学 | Lithium ion battery switch charging circuit |
-
2016
- 2016-06-03 CN CN201610395747.0A patent/CN107465217B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013113236A1 (en) * | 2012-02-03 | 2013-08-08 | 无锡华润上华半导体有限公司 | Secondary battery charging device |
| CN103378617A (en) * | 2012-04-18 | 2013-10-30 | 钰泰科技（上海）有限公司 | Lithium battery charging circuit |
| CN103401420A (en) * | 2013-07-03 | 2013-11-20 | 西安电子科技大学 | Adaptive turn-on time generation circuit applied to DC-DC converter |
| CN103457320A (en) * | 2013-08-22 | 2013-12-18 | 电子科技大学 | Lithium ion battery switch charging circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111224446A (en) * | 2020-02-26 | 2020-06-02 | 湖南品腾电子科技有限公司 | Lithium battery charging circuit |
| CN111224446B (en) * | 2020-02-26 | 2021-07-09 | 湖南品腾电子科技有限公司 | Lithium battery charging circuit |
| CN113933671A (en) * | 2021-09-01 | 2022-01-14 | 郑州嘉晨电器有限公司 | MOS device temperature detection device |
| CN113922683A (en) * | 2021-09-26 | 2022-01-11 | 西北工业大学 | Single-stage wireless charging circuit based on digital rectifier |
| CN113922683B (en) * | 2021-09-26 | 2023-10-03 | 西北工业大学 | Single-stage wireless charging circuit based on digital rectifier |
| CN115882700A (en) * | 2023-03-08 | 2023-03-31 | 合肥乘翎微电子有限公司 | Control circuit of direct current-direct current converter with wide conversion ratio |
| CN115882700B (en) * | 2023-03-08 | 2023-04-28 | 合肥乘翎微电子有限公司 | Control circuit of direct current-direct current converter with wide conversion ratio |
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| CN107465217B (en) | 2023-03-21 |
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