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CN107452688A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN107452688A
CN107452688A CN201710258116.9A CN201710258116A CN107452688A CN 107452688 A CN107452688 A CN 107452688A CN 201710258116 A CN201710258116 A CN 201710258116A CN 107452688 A CN107452688 A CN 107452688A
Authority
CN
China
Prior art keywords
control
semiconductor element
base plate
housing
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710258116.9A
Other languages
Chinese (zh)
Other versions
CN107452688B (en
Inventor
村上晴彦
米山玲
木村义孝
白滨孝之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN107452688A publication Critical patent/CN107452688A/en
Application granted granted Critical
Publication of CN107452688B publication Critical patent/CN107452688B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3737—Organic materials with or without a thermoconductive filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/38—Cooling arrangements using the Peltier effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Inverter Devices (AREA)

Abstract

There is semiconductor device (100) base plate (1), housing (3), power semiconductor (5) and control to use semiconductor element (6).Housing (3) is arranged on base plate (1).Power semiconductor (5) is configured on the base plate (1) in housing (3).Control is configured at the inside of housing (3) with semiconductor element (6).In housing (3) side opposite with base plate (1) formed with opening portion (21).Also have the lid (23) of opening portion (21) occlusion of housing (3).At lid (23) place, when overlooking with control with least a portion in the overlapping region of semiconductor element (6) formed with hole portion (25).

Description

Semiconductor device
Technical field
The present invention relates to a kind of semiconductor device, especially, it is related to being encapsulated by resin to power semiconductor Structure semiconductor device.
Background technology
Electric control semiconductor module is by IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal Oxide Semiconductor Field Effect Transistor)、FWDi(Free Wheeling Diode) It is equipped on Deng as the power semiconductor that switching device uses in framework.Above-mentioned semiconductor module is referred to as power model.
In the field of power model, the power model for being referred to as SPM (IPM) be present, it not only there is power partly to lead Volume elements part, also there is the control circuit for being driven and protecting to power semiconductor.As SPM, such as Know the structure disclosed in Japanese Unexamined Patent Publication 2006-121861 publications.
For SPM, from the angle for the decline for suppressing its action, it is necessary to by radiating etc. and internal The part of the heating in portion is cooled down.But in Japanese Unexamined Patent Publication 2006-121861 publications, the substrate of control circuit is controlled Circuit substrate processed is packaged by insulating resin.Therefore, to being installed on the control semiconductor element of the control circuit substrate The electronic units such as part, which carry out cooling, becomes difficult.
The content of the invention
The present invention in view of above-mentioned problem and propose, can be expeditiously in intelligent power its object is to provide one kind The semiconductor device that the control of the control circuit substrate installation of module is cooled down with semiconductor element.
The semiconductor device of the present invention has base plate, housing, power semiconductor and control semiconductor element.Housing is set It is placed on base plate.Power semiconductor is configured on the base plate in housing.Control is configured at semiconductor element The inside of housing.In housing side opposite with base plate formed with opening portion.Also have the lid of the opening port blocking of housing. At lid, when overlooking, at least a portion in the region overlapping with control semiconductor element is formed with hole portion.
The following detailed description related to the present invention understood in conjunction with the accompanying drawings, make the above and other mesh of the present invention , feature, scheme and advantage become clear and definite.
Brief description of the drawings
Fig. 1 is the general profile chart of the structure for the semiconductor device for representing embodiment 1.
Fig. 2 is for each part of the semiconductor device of pie graph 1, shows the exploded perspective view of the configuration of each part.
Fig. 3 be the outline for the structure for representing the control semiconductor element configured with the region III of dotted line in Fig. 1 just View.
Fig. 4 is the general profile chart of the structure for the semiconductor device for representing comparative example.
Fig. 5 is for each part of the semiconductor device of pie graph 4, shows the exploded perspective view of the configuration of each part.
Fig. 6 is the general profile chart of the structure for the semiconductor device for representing embodiment 2.
Fig. 7 is the general profile chart of the 1st of the detailed morphology for representing the region A with dotted line in Fig. 6.
Fig. 8 is the general profile chart of the 2nd of the detailed morphology for representing the region A with dotted line in Fig. 6.
Fig. 9 is the general profile chart of the structure for the semiconductor device for representing embodiment 3.
Figure 10 is the general profile chart of the structure for the semiconductor device for representing embodiment 4.
Figure 11 is the general profile chart of the structure for the semiconductor device for representing embodiment 5.
Figure 12 is the general profile chart for the structure for representing Peltier's element.
Figure 13 is to represent the control semiconductor element that the region III with dotted line in Fig. 1 in embodiment 6 is configured Structure outline elevation.
Figure 14 is the general profile chart of the structure for the semiconductor device for representing embodiment 7.
Embodiment
Below, based on accompanying drawing, an embodiment is illustrated.
Embodiment 1.
First, using Fig. 1, the structure of the semiconductor device 100 of present embodiment is illustrated.Reference picture 1, present embodiment Semiconductor device 100 be the intelligence for mainly having base plate 1, housing 3, power semiconductor 5 and control semiconductor element 6 Can power model.
Base plate 1 is configured at the foot in the entirety of semiconductor device 100, is with the bottom overall as semiconductor device 100 The part of such as writing board shape of the effect of seat.Base plate 1 has when overlooking in a main surface 1A of such as rectangular shape And another main surface 1B of side in contrast.In addition, herein, by the upside of Fig. 1 in the main surface of 1 couple of base plate 1 Main surface be set to a main surface 1A, the main surface of Fig. 1 downside is set to another main surface 1B.It is preferred that base plate 1 by The metal materials such as aluminium are formed.
Housing 3 is arranged to be engaged on base plate 1 i.e. on a main surface 1A, is configured at and base plate 1 when being and overlooking The part of overlapping frame shape region, that there is rectangle in outermost region.That is, housing 3 is configured to surround base when overlooking The central portion of seat board 1.If housing 3 is installed on base plate 1, it is integrally formed the two, then it is bottom to turn into base plate 1 Face, with housing 3 it is the container-like of side.As following forms, i.e. be in base plate 1 in the inside of the container-like part On the portion of centre, each part described later is equipped with the part surrounded by housing 3.Housing 3 is formed by insulating materials such as resins.
Housing 3 has housing wall portion 3A, housing upper surface 3B and housing lower surface 3C.Housing wall portion 3A is the main of housing 3 Part, upper and lowers of the housing wall portion 3A in Fig. 1 upwardly extend, so as to form together with base plate 1 part surrounded by housing 3 For container-like resettlement section.Housing upper surface 3B is the face of housing wall portion 3A topmost.Housing lower surface 3C be housing 3 most The face of bottom, the part engaged comprising a main surface 1A with base plate 1.It is preferred that housing 3 is including housing lower surface 3C's Foot, the inner side compared with housing wall portion 3A and housing upper surface 3B when overlooking forms wider.So, for example, with housing The situation in the region of inner sides of the lower surface 3C not comprising housing wall portion 3A is compared, due to that can increase housing lower surface 3C and pedestal The area of the part of one main surface 1A engagement of plate 1, therefore housing 3 can be more firmly fixed on base plate 1.
Power semiconductor 5 is configured on the base plate 1 at the region surrounded in housing 3 by housing 3.Specifically, Power semiconductor 5 is configured at the inside for the container-like part being made up of base plate 1 and housing 3.Power semiconductor 5 It is installed on power semiconductor substrate 8.
Power semiconductor substrate 8 is equipped on a main surface 1A of the base plate 1 of the inside of the part of said vesse shape. Power semiconductor has insulated substrate 10 and Wiring pattern 11,12,13 with substrate 8.Insulated substrate 10 is, for example, to have when overlooking There is the part of the writing board shape of rectangular shape, there is a main surface 10A and in contrast another main surface 10B of side. Wiring pattern 11 and Wiring pattern 12 are each other on the upside of Fig. 1 that compartment of terrain is placed in the main surface of 1 couple of insulated substrate 10 Main surface is on a main surface 10A.In addition, on the main surface of the downside of insulated substrate 10 be another main surface 10B it On be placed with Wiring pattern 13.Formed it is preferred that insulated substrate 10 is waited by ceramics with the material of insulating properties, Wiring pattern 11,12, 13 are formed by metal materials such as copper.Wiring pattern 11,12,13 is directly engaged in insulated substrate (not via connection members such as solders) On 10 main surface 10A, 10B.
Power semiconductor 5 be placed in main surface on the upside of Fig. 1 of such as Wiring pattern 11 of power semiconductor substrate 8 it On.Power semiconductor 5 is equipped with the power semiconductor element such as IGBT, MOSFET, FWDi.Preferably comprise power semiconductor The chip of element 5 is formed by such as carborundum.
In Fig. 1, from the angle simplified to figure, single power semiconductor 5 is only illustrated.It is but actual On, as shown in Fig. 2 exploded perspective view, preferably on the direction along a main surface 10A of insulated substrate 10 each other across Multiple power semiconductors 5 are placed with every ground.Therefore, power semiconductor 5 is not limited to be placed in power semiconductor base On the main surface of the upside of the Wiring pattern 11 of plate 8, on the main surface for the upside that Wiring pattern 12 can also be placed in.
Control semiconductor element 6 is configured at the region that the inside of housing 3 is surrounded by housing 3.Specifically, control is with partly leading Volume elements part 6 is configured at the inside for the container-like part being made up of base plate 1 and housing 3 in the same manner as power semiconductor 5. Control semiconductor element 6 is installed on control circuit substrate 9.
Control circuit substrate 9 is, for example, the part of the writing board shape when overlooking with rectangular shape, is to have a main surface Another main surface 9B of 9A and in contrast side printed base plate.Control and be and control circuit with the mounting of semiconductor element 6 Contacted on one main surface 9A of substrate 9.Control semiconductor element 6 is the driving and guarantor for power semiconductor 5 The semiconductor element for protecting and setting.In addition, though it is not shown, but also taken on a main surface 9A of control circuit substrate 9 It is loaded with peripheral circuit etc..
It is preferred that control circuit substrate 9 and being installed on the control of control circuit substrate 9 with semiconductor element 6 and power semiconductor base Plate 8 and the power semiconductor 5 of power semiconductor substrate 8 is installed on Fig. 1 above-below direction each other across compartment of terrain It is configured at base plate 1 opposite side i.e. Fig. 1 upside of the power semiconductor with substrate 8.
In addition, in Fig. 1, from the angle simplified to figure, only illustrate single control semiconductor element 6.But It is, in fact, as shown in Fig. 2 exploded perspective view, preferably on the direction along a main surface 10A of insulated substrate 10 each other Multiple control semiconductor elements 6 are placed with across compartment of terrain.As shown in Fig. 2 herein, such as control is placed with the following manner System uses semiconductor element 6, i.e. when overlooking, control semiconductor element 6 is arranged in the row of the distal side of figure and the row of proximal lateral This 2 row.Control with half in the left and right directions (length direction during vertical view) along Fig. 2 of the row with distal side 1 Dui adjacent to each other The suitable position in the position of the centre of conductor element 6, it is placed with the control semiconductor element 6 of the row of proximal lateral.Conversely, with The left and right directions along Fig. 2 of the row of proximal lateral 1 pair of control suitable position in the position of the centre of semiconductor element 6 adjacent to each other Put, be placed with the control semiconductor element 6 of the row of distal side.As described above, row that can also be in Fig. 2 proximal lateral and distal end Between the row of side, control semiconductor element 6 is configured with position (staggered position) different from each other.
It is preferred that control circuit substrate 9 is made up of resin materials such as glass epoxy resins.The size during vertical view of control circuit substrate 9 Specific power semiconductor substrate 8 is big.The reason is that power semiconductor is directly placed in a main table of base plate 1 with substrate 8 On the 1A of face, housing 3 extends to inner side at housing lower surface 3C compared with other regions, correspondingly, can configure work( The area of plane in region of the area of plane in the region of rate semiconductor substrate 8 than that can configure control circuit substrate 9 is small.But Be not limited to above-mentioned form, control circuit substrate 9 can also specific power semiconductor substrate 8 it is small.
In Fig. 1, control circuit substrate 9 is in the size that the region entirety surrounded by housing 3 is occupied when overlooking, and turns into control electricity The form that the housing wall portion 3A of base board 9 and housing 3 is in contact with each other.But above-mentioned form is not limited to, such as can also be, in shell There is interval between the outer rim of body wall portion 3A and control circuit substrate 9.
It is the region on the upside of Fig. 1 in the side opposite with base plate 1 of housing 3 formed with opening portion 21.Can be from the opening portion 21 Power semiconductor 5 and control are inserted in the container-like component comprising housing 3 with each part such as semiconductor element 6.
Lid 23 is configured with a manner of the occlusion of opening portion 21 by the topmost of above-mentioned housing 3.It is preferred that lid 23 is insulated by resin etc. Material is formed.Lid 23 is configured at the overall topmost of semiconductor device 100 in a manner of relative with base plate 1.In addition, in Fig. 1 In turn into following forms, i.e. the outer edge surface of lid 23 contacts with housing wall portion 3A inwall, so as to by the occlusion of opening portion 21.But Following forms can also be turned into, i.e. lid 23 covers housing upper surface 3B, so as to which opening portion 21 is inaccessible.
In lid 23 formed with hole portion 25, the hole portion 25 is with from a main surface on the thickness direction of lid 23 to reaching phase therewith The mode on another the main surface tossed about runs through lid 23.Hole portion 25 is formed in the following manner, i.e. by hole portion 25 with When the relative mode of base plate 1 is configured, at least one when overlooking with control with the overlapping region of semiconductor element 6 is included Point.More preferably hole portion 25 is formed in the following manner, i.e. when overlooking with control with the vertical view of semiconductor element 6 when entirety weight It is folded.
Because hole portion 25 is formed in the region overlapping with control semiconductor element 6, therefore, if as shown in Fig. 2 formed Semiconductor element 6 is used in multiple controls, then preferably alsos form multiple hole portions 25.Therefore, in Fig. 1, from the angle simplified to figure Degree sets out and only illustrates single hole portion 25, but in fact, as shown in Figure 2 formed with multiple hole portions 25.
Accordingly it is also possible to control with the same manner as semiconductor element 6, hole portion 25 is in the row of Fig. 2 proximal lateral and the row of distal side Between be configured at position different from each other (staggered position).Also, due to hole portion 25 be with control semiconductor element 6 What overlapping mode was formed, thus more preferably its flat shape be with the identical shape of control semiconductor element 6, e.g. with The identical rectangular shape of semiconductor element 6 is used in control.But the flat shape not limited to this of hole portion 25, such as can also be round Shape.
Each part illustrated above is attached and encapsulated in the following manner.First, the housing 3 shown in Fig. 1 can also Formed with main electrode terminal 15 on surface on the inside of it.Main electrode terminal 15 can also have following continuous forms, i.e. From on the upper space with extending to the region than housing wall portion 3A more in the inner part in the same manner as housing lower surface 3C, by shell On the surface of body wall portion 3A inner side, to reaching housing upper surface 3B.It is preferred that main electrode terminal 15 is by metal materials such as copper Film is formed.
Power semiconductor substrate 8 is for example engaged on base plate 1 main surface 1A by solder 31.That is, in work( The Wiring pattern 13 of another main surface 10B sides configuration of rate semiconductor substrate 8 is engaged in base plate 1 by solder 31. In addition, the power semiconductor 5 for being installed on power semiconductor substrate 8 is for example engaged in Wiring pattern 11 by solder 31 Surface on.
The power semiconductor 5 of shaped like chips is engaged in power semiconductor substrate 8 by solder 31, on the other hand, control There is different form with semiconductor element 6.Reference picture 3, control have packaging part 61 and lead frame with semiconductor element 6 Frame 62.
Portion chip, being for example made up of silicon with semiconductor element as composition control is contained in the inside of packaging part 61 Part.Such as in the case where control semiconductor element 6 is the control semiconductor element of surface installation type, preferred package 61 has Have in the flat board extended up along the control is carried with a main surface 9A of the control circuit substrate 9 of semiconductor element 6 side Shape.In addition, the structure of the inside of packaging part 61 is arbitrary.Lead frame 62 is electrically connected with the chip in above-mentioned packaging part 61 Connect, the input and output of horizontal electrical signal can be entered with the outside of control semiconductor element 6.Preferred package 61 is by resin material structure Into lead frame 62 is made up of metal materials such as copper.
The control semiconductor element 6 of structure shown in Fig. 3 is placed on a main surface 9A of control circuit substrate 9, is drawn The leading section of wire frame 62 is electrically connected by solder etc. and terminal on a main surface 9A of control circuit substrate 9 etc..By This, control semiconductor element 6 is installed in control circuit substrate 9.
Control signal terminal 32 is connected to control circuit substrate 9, and control signal terminal 33 is connected to the part as housing 3 Such as the region along housing lower surface 3C.The control signal terminal 32 of the side of control circuit substrate 9 is to be used to realize control with partly leading The terminal of the input and output of electric signal between the outside of volume elements part 6 and semiconductor device 100.Therefore, control signal terminal 32 It is configured to, by extending to the top of lid 23, so as to reach to the outside of semiconductor device 100.In addition, control signal terminal 33 It is the terminal for carrying out the control of power semiconductor 5 and setting.It is preferred that control signal terminal 32,33 is by metal materials such as copper Material is formed.
It is electrically connected in terminal (not shown) that power semiconductor 5 is set etc. and control signal terminal 33 by bonding line 34 Connect.Bonding line 34 is the thin-line-shaped part being made up of metal materials such as aluminium.Bonding line 34 for example can be used for power and partly lead The electrical connection of volume elements part 5 and Wiring pattern 12, can be also used for the electrical connection of Wiring pattern 12 and main electrode terminal 15.
Resin material 35 is filled with the inside for the container-like part being made up of base plate 1 and housing 3.Resin material 35 configures To be filled to the region especially only on the downside of Fig. 1 of control circuit substrate 9 in the inside of the part of said vesse shape. That is, resin material 35 is configured to, by the power semiconductor surface of substrate 8 and power semiconductor 5, housing wall portion 3A The part on the surface of side, the part on surface of main electrode terminal 15 etc. cover.Therefore, resin material 35 is configured to, and will not Control is covered with the surface of semiconductor element 6.With regard to control with for semiconductor element 6, due to configuring lid 23 directly over it Hole portion 25, therefore control is turned into the same manner as the outside of semiconductor device 100 with the surface of semiconductor element 6 and for example connect with air Tactile form.
Resin material 35 is the resin materials such as Silica hydrogel or epoxy resin, as described above, it is preferred to be filled in the following manner, That is, with the grade of substrate 8 it is under Fig. 1 more by the side of base plate 1 than control circuit substrate 9 to power semiconductor 5 and power semiconductor The region of side is packaged.
Below, while the comparative example to present embodiment illustrates, the action effect of present embodiment is illustrated.
Reference picture 4 and Fig. 5, the semiconductor device 900 of comparative example is with essentially identical with the semiconductor device 100 of present embodiment Structure.Therefore, for semiconductor device 900, pair with the identical structural element of semiconductor device 100 mark identical with reference to marking Number, its explanation is not repeated.Difference of the semiconductor device 900 compared with semiconductor device 100 is, does not form hole in lid 23 Portion 25.
For being built-in with the SPM of silicon power semiconductor 5, it is contemplated that the hair caused by switching losses Junction temperature that is hot and making power semiconductor rises this case, generally enters in the low frequency region less than or equal to 20kHz or so Exercise and use.On the other hand, it is built-in with the SPM of silicon carbide power semiconductor element 5 and is built-in with silicon power semiconductor The SPM of element 5 is compared to that can carry out high temperature action, even being more than or equal to 50kHz and being less than or equal to 100kHz frequency field can also be used, and can also be acted in the high-frequency region more than 100kHz.
But be greater than or the action of the SPM of high-frequency region equal to 50kHz for, control semiconductor element The increase of 6 caloric value turns into problem.That is, for semiconductor device 900, although can be via base plate 1 in user side pair Power semiconductor 5 is cooled down, but it is difficult to carry out cooling with semiconductor element 6 to control in user side.
Therefore, it is overlapping with semiconductor element 6 with control in the vertical view of lid 23 for the semiconductor device 100 of present embodiment Region at least a portion formed with hole portion 25.Thereby, it is possible to be semiconductor device 100 using from the top of the lid 23 Outside air etc. is cooled down to control with semiconductor element 6, can suppress the excessive temperature of control semiconductor element 6 Rise.
Also, in order to improve cooling effectiveness, such as wind more preferably is set with the upper surface of semiconductor element 6 in control in user side The cooling devices such as fan.By setting hole portion 25, so as to realize the setting of above-mentioned cooling device in user side.Thereby, it is possible to Air cooling is carried out with semiconductor element 6 to control, improves and suppresses the effect that its temperature rises.By with upper type, present embodiment Power semiconductor 5 can not only efficiently be radiated, additionally it is possible to which control is efficiently dissipated with semiconductor element 6 Heat.
Embodiment 2
Reference picture 6, the semiconductor device 200 of present embodiment have the semiconductor device 100 with the embodiment 1 shown in Fig. 1 Essentially identical configuration.Therefore, pair will with Fig. 1 identical structure of semiconductor device 100 for Fig. 6 semiconductor device 200 Element mark identical reference numeral, does not repeat its explanation.Difference of the semiconductor device 200 compared with semiconductor device 100 exists In control is different with the position on Fig. 6 above-below direction of semiconductor element 6.
As described above, control semiconductor element 6 is the structure for having packaging part 61 and lead frame 62, but control is considered herein System one main surface 6A of semiconductor element 6 and another main surface 6B of side in contrast.One main surface 6A is control Main surface of the system on the upside of Fig. 6 in a pair of main surfaces of the main body (such as main body of packaging part 61) of semiconductor element 6, it is another Individual main surface 6B is the main surface on the downside of Fig. 6.In addition, similarly consider for lid 23 a main surface 23A on the upside of Fig. 6 with And another main surface 23B of side in contrast.
As shown in the region A with dotted line in Fig. 6, in the present embodiment, the hole portion 25 of lid 23 when overlooking and controls It is overlapping with the entirety during vertical view of semiconductor element 6.And it is configured to, control semiconductor element 6 is inserted into hole portion 25. Reference picture 7 or, in Fig. 6 region A, lid 23 is configured at and controlled with a main surface 23A of 1 opposite side of base plate System position coplanar one main surface 6A of the 1 opposite side of same base plate of semiconductor element 6.Or reference picture 8, can also It is, in Fig. 6 region A, compared to a main surface 6A with 1 opposite side of base plate for control semiconductor element 6, lid 23 It is configured at a main surface 23A of 1 opposite side of base plate on the downside of the i.e. Fig. 6 in the side of base plate 1.In the case of fig. 8, a main table Face 6A is raised upward with size H compared with a main surface 23A.
In the present embodiment, compared with embodiment 1, control is integrally configured with semiconductor element 6 and control circuit substrate 9 In the top of semiconductor device 200.Therefore, the region of the lower section of control circuit substrate 9 is the region for being filled resin material 35 Deepened compared with embodiment 1 on Fig. 6 above-below direction, the inside for the container-like part being made up of base plate 1 and housing 3 Substantially overall covered by resin material 35.
Below, the action effect of present embodiment is illustrated.Present embodiment remove realize the action effect of embodiment 1 with Outside, following action effect is also realized.
In embodiment 1, the upper space of lid 23 is disposed above relative to control with the upper space of semiconductor element 6, Control is configured at the inside for the container-like part being made up of base plate 1 and housing 3 with the upper space of semiconductor element 6.Cause This, it is difficult that cooling device is attached into control with the upper space of semiconductor element 6 in user side.But by such as originally Embodiment is upper space i.e. one of the main surface 23A with control with semiconductor element 6 like that by the upper space of lid 23 Individual main surface 6A is compared to lower section is configured at, so as to easily touch a main surface of control semiconductor element 6 as user 6A state.Therefore, compared with embodiment 1, become that the cooling devices such as radiating fin easily are attached into one in user side On main surface 6A.By installing the cooling device, so as to suppress the effect that the excessive temperature of control semiconductor element 6 rises Fruit is improved.
Embodiment 3
Reference picture 9, the semiconductor device 300 of present embodiment have the semiconductor device 100 with the embodiment 1 shown in Fig. 1 Essentially identical configuration.Therefore, pair will with Fig. 1 identical structure of semiconductor device 100 for Fig. 9 semiconductor device 300 Element mark identical reference numeral, does not repeat its explanation.Difference of the semiconductor device 300 compared with semiconductor device 100 exists In, also there is heat sink 41 on a main surface 6A with base plate 1 opposite side of the control with semiconductor element 6, radiate Plate 41 is configured to the occlusion of hole portion 25 of the lid 23 directly over control semiconductor element 6.
It is preferred that heat sink 41 is formed by metallic plates such as aluminium.Additionally, it is preferred that heat sink 41 is with one by control with semiconductor element 6 The mode that main surface 6A is integrally covered contacts with main surface 6A.In fig.9, heat sink 41 and control putting down with semiconductor element 6 Face area equation.But the flat shape of heat sink 41 is substantially arbitrary, it is possible to have is partly extend out to during vertical view The size in the control outside (that is, heat sink 41 is bigger than control semiconductor element 6) of semiconductor element 6.
Heat sink 41 is configured to, and its lowest surface is contacted with control with a main surface 6A of semiconductor element 6, and its most upper table Face is by the dead end for most leaning on the side of base plate 1 (Fig. 9 downside) of hole portion 25, and the region adjacent with hole portion 25 during with overlooking Lid 23 another main surface 23B contact.Therefore, for semiconductor device 300, with dissipating when hole portion 25 is only configured at vertical view The part in the overlapping region of hot plate 41, the area of plane of hole portion 25 are smaller than heat sink 41.In heat sink 41 and control with partly leading In the case that the area of plane of volume elements part 6 is equal, it may also be said to be, when hole portion 25 is only configured at vertical view with control semiconductor element The part in the overlapping region of part 6, the area of plane of hole portion 25 are smaller with semiconductor element 6 than control.Thus, heat sink 41 is by hole The overall occlusion in portion 25, separate air between the inside and outside for the container-like part being made up of base plate 1 and housing 3 etc. Circulation.
Below, the action effect of present embodiment is illustrated.Present embodiment remove realize the action effect of embodiment 1 with Outside, following action effect is also realized.
In embodiment 1, by setting hole portion 25 in lid 23, so as to realize the container being made up of base plate 1 and housing 3 The circulation of air between the inside and outside of the part of shape etc..Thus, the control radiating to outside of semiconductor element 6 is imitated Rate improves, and but then, from the outside of semiconductor device 100, mixed foreign matter may be attached to control semiconductor element 6 A main surface 6A on.
Therefore, one of control semiconductor element 6 main surface 6A is covered and incited somebody to action by setting as in the present embodiment The heat sink 41 of the occlusion of hole portion 25 of lid 23, it is outer from control semiconductor element 6 to semiconductor device 100 so as to ensure The thermal diffusivity in portion, and suppress foreign matter to the attachment on a main surface 6A of control semiconductor element 6.
Embodiment 4
Reference picture 10, the semiconductor device 400 of present embodiment have the semiconductor device with the embodiment 1 shown in Fig. 1 The essentially identical configuration of semiconductor device 300 of embodiment 3 shown in 100 and Fig. 9.Therefore, for Figure 10 semiconductor Device 400, pair marks identical reference numeral with Fig. 1, Fig. 9 semiconductor device 100,300 identical structural elements, does not repeat Its explanation.
Difference of the semiconductor device 400 compared with semiconductor device 300 is that heat sink 41 includes：The part of 1st heat sink 41A, it is contained in the hole portion 25 of lid 23；And the 2nd heat sink part 41B, it prolongs from the 1st heat sink 41A part On the downside of the i.e. Figure 10 of private side for extending housing 3.The part 41B of 2nd heat sink foot uses the one of semiconductor element 6 with control Contacted on individual main surface 6A, especially, in Fig. 10, the part 41B of the 2nd heat sink and a main surface 6A entire surface connect Touch.Therefore, the part 41B of the 2nd heat sink and a main surface 6A area of plane are equal.The part 41A configurations of 1st heat sink The inwall of hole portion 25 to be covered, by the overall landfill of hole portion 25.
In Fig. 10, the area of plane of hole portion 25 is bigger with semiconductor element 6 than control, and hole portion 25 is configured to, same during with overlooking Control is overlapping with the overlapping region entirety of semiconductor element 6, and also with the same control adjacent region of the outer rim of semiconductor element 6 It is overlapping.Therefore, the 1st heat sink 41A area of plane ratio integrally filled it in a manner of the inwall of hole portion 25 is covered with The 2nd heat sink 41B that control is contacted with semiconductor element 6 is big.But such as shown in Fig. 9, in the present embodiment, can also Be hole portion 25 the area of plane it is smaller than control semiconductor element 6, be configured with heat sink 41, the heat sink 41 has the hole portion The 1st heat sink 41A part and the 2nd heat sink 41B contacted with control semiconductor element 6 below portion of 25 landfills Point.
Below, the action effect of present embodiment is illustrated.Present embodiment remove realize the action effect of embodiment 3 with Outside, following action effect is also realized.
With regard to the control heating of semiconductor element 6 is radiated to the knot of the embodiment 3 in the outside of hole portion 25 using heat sink 41 For structure, in order to further improve cooling effectiveness, fan for example more preferably also is set in the upper surface of heat sink 41 in user side Deng cooling device.But in embodiment 3, due to for a main surface 23A of lid 23 heat sink 41 it is most upper Surface is located at relatively low position, therefore the cooling device such as radiating fin is difficult to the installation on the upper surface of heat sink 41 's.
Therefore, for the semiconductor device 400 of present embodiment, heat sink 41 is set to following structures, i.e. have and be contained in The part of the 1st heat sink 41A in hole portion 25 and the 2nd heat sink 41B's that is contacted on the downside of it with control semiconductor element 6 Both parts.So, compared with embodiment 3, the upper space of heat sink 41 is configured at higher position.Therefore, it is possible to Ensure the effect that the heat sent to control with semiconductor element 6 itself realized by heat sink 41 is radiated, and So that the cooling device such as radiating fin is easily to installing on the upper surface of heat sink 41.
In addition, in Fig. 10, the 1st heat sink 41A of heat sink 41 upper space is configured at a main surface 23A with lid 23 Coplanar position is but it is also possible to be following forms, i.e. the 1st heat sink 41A upper space is convex compared with a main surface 23A Rise to top, in other words, be raised to the outside of semiconductor device 100.Nonetheless, also can easily carry out cooling device to Installation on heat sink 41, and because heat sink 41 exposes to the outside of semiconductor device 100, therefore can further carry Thermal diffusivity of the principle of readjustment, restructuring, consolidation and improvement to control with semiconductor element 6.
Embodiment 5
Reference picture 11, the semiconductor device 500 of present embodiment have the semiconductor device 200 with the embodiment 2 shown in Fig. 6 Essentially identical configuration.Therefore, for Figure 11 semiconductor device 500, the identical structure of semiconductor device 200 pair with Fig. 6 Key element marks identical reference numeral, does not repeat its explanation.Difference of the semiconductor device 500 compared with semiconductor device 200 It is that there are following structures, i.e. also there is peltier with a main surface 23A of 1 opposite side of base plate top in lid 23 Element 71.
Peltier's element 71 is configured to, in fig. 11, main a surface 23A and control semiconductor of its lowest surface and lid 23 One main surface 6A contact of element 6.But above-mentioned form is not limited to, such as can also be following forms, i.e. such as by peltier The situation that element 71 is applied to the structure shown in Fig. 8 of embodiment 2 is such, the lowest surface of Peltier's element 71 and a master Surface 6A is contacted, but is not contacted with a main surface 23A, but is floated upward relative to a main surface 23A.In addition, In the case of the semiconductor device 400 that Peltier's element 71 is applied to Figure 10 of embodiment 4, turn into the most upper of heat sink 41 The form that surface, one of lid 23 main surface 23A contact with the lowest surface of Peltier's element 71, but this structure be also can be with 's.
Using the control circuit power supply of SPM, it is used for being installed on the control of control circuit substrate 9 with partly leading Power supply of the power supply that volume elements part 6 is driven as Peltier's element 71.Thus, it is not necessary to be separately additionally provided for amber ear The power supply of note element 71.
Reference picture 12, the Peltier's element 71 of the region XII with dotted line in Figure 11 is by multiple thermoelectric elements 72, Duo Ge electricity Pole 73 and 1 pair of ceramic substrate 74 are formed.Multiple thermoelectric elements 72 are for example by the p-type semiconductor of silicon and the combination structure of n-type semiconductor Into.Herein, such as on Figure 12 left and right directions, p-type semiconductor and n-type semiconductor are alternately arranged.
Multiple electrodes 73 are formed by metal materials such as copper.Multiple electrodes 73 with it is adjacent to each other on Figure 12 left and right directions The 1 pair of both sides of thermoelectric element 72 connection, electrode 73 are handed between the region of upside of Figure 12 thermoelectric element 72 and the region of downside Alternately configure.That is, for example, if the 1st thermoelectric element 72 and the 2nd thermoelectric element 72 adjacent thereto in their upside by electrode 73 are attached, then the 2nd thermoelectric element 72 and with the 2nd thermoelectric element 72 the opposite side of the 1st thermoelectric element 72 it is adjacent the 3rd Thermoelectric element 72 is attached in their downside by electrode 73.
By being integrally connected with upper type, whole thermoelectric elements 72 and electrode 73.1 pair of ceramic substrate 74 is configured to, it is right Whole thermoelectric elements 72 and electrode 73 being clamped over and under from them after above-mentioned integration.
Below, the action effect of present embodiment is illustrated.Present embodiment removes the effect for realizing the respective embodiments described above Beyond effect, following action effect is also realized.
For the semiconductor device of the respective embodiments described above, in order to further improve cooling effect, it is necessary to be set in user side Cooling device.But in the present embodiment, there is Peltier's element 71 in a main surface 23A of lid 23 top.By This, even if being not provided with above-mentioned cooling device, also can efficiently be carried out cold via Peltier's element to control with semiconductor element 6 But.
Embodiment 6
As described above, control has packaging part 61 and the (reference of lead frame 62 with semiconductor element 6 used in each embodiment Fig. 3).Reference picture 13, in the present embodiment, at least a portion on the surface of packaging part 61 are more than or waited comprising multiple depth In 500 μm of recess 63.Above-mentioned multiple tables for being more than or equal to 2 recesses 63 and being formed at packaging part 61 across interval each other Face.For recess 63, on the surface of packaging part 61, compared with forming the region beyond the region of recess 63, depth is Figure 13 Above-below direction size be more than or equal to 500 μm.More preferably the depth of the recess 63 is more than or equal to 600 μm.
As shown in figure 13, can also the upper space of packaging part 61 be install when side opposite with the side of base plate 1 surface and This two side of the surface of the side of base plate 1 when the lowest surface of packaging part 61 is installation is formed with more than or equal to 2 recesses 63.But It is that one party that can also be only in the upper space of packaging part or lowest surface is formed with more than or equal to 2 recesses 63.
The control semiconductor element 6 of surface characteristics with above-mentioned packaging part 61 can also be applied in the respective embodiments described above The semiconductor device 100~500 of any one.In addition, for the semiconductor device of present embodiment, due to except above-mentioned encapsulation Beyond the surface of part 61, substantially there is the identical structure of semiconductor device 100~500 with the respective embodiments described above 1~5, Therefore the feature in its structure is omitted the description.
Below, the action effect of present embodiment is illustrated.Present embodiment removes the effect of the respective embodiments described above 1~5 Following action effect is also realized beyond effect.
As described above, depth is set to be more than or equal to by the surface of the packaging part 61 included in control with semiconductor element 6 500 μm of recess 63, so as to which compared with not forming the situation of above-mentioned recess 63, the surface area of packaging part 61 increases.Therefore, it is possible to Improve the thermal diffusivity from control with the surface radiating of semiconductor element 6.
Embodiment 7
Reference picture 14, it is container-like being made up of base plate 1 and housing 3 for the semiconductor device 600 of present embodiment Inside, the especially downside of control circuit substrate 9 the region of part, substitutes resin material 35 and is configured with high-cooling property resin 36.High-cooling property resin 36 is configured in the same manner as Fig. 1 etc. resin material 35, by power semiconductor substrate 8 and power half The surface of conductor element 5, another main surface 9B of control circuit substrate 9, housing wall portion 3A inner side surface a part, The part on the surface of main electrode terminal 15 etc. covers.As described above, high-cooling property resin 36 is with to power half in housing 3 What the mode that conductor element 5 is packaged was filled.
High-cooling property resin 36 is made up of in the same manner as resin material 35 resins such as Silica hydrogel or epoxy resin.It is but high scattered The thermal diffusivity compared with resin material 35 of thermal resin 36 is higher.Specifically, the thermal conductivity of high-cooling property resin 36 is more than or waited In 0.5W/ (mK).More preferably the thermal conductivity is more than or equal to 0.6W/ (mK).
In addition, in fig. 14, show to apply high-cooling property to the semiconductor device 200 of embodiment 2 as an example The example of resin 36.But not limited to this, the application first of high-cooling property resin 36 is stated to the arbitrary semiconductor of each embodiment Device 100~500.For the semiconductor device of present embodiment, due in addition to the surface of above-mentioned packaging part 61, base There is the identical structure of semiconductor device 100~500 with the respective embodiments described above in sheet, therefore the feature in its structure is saved Slightly illustrate.
Below, the action effect of present embodiment is illustrated.Present embodiment removes the effect of the respective embodiments described above 1~6 Following action effect is also realized beyond effect.
In the respective embodiments described above 1~6, transmitted from control semiconductor element 6 and control circuit substrate 9 to resin material 35 The radiating mode of heat may turn into problem.But in the present embodiment, can will be from control semiconductor element 6 And control circuit substrate 9 is transferred to the heat of high-cooling property resin 36 and efficiently radiated from such as side of base plate 1 to semiconductor and filled Put 600 outside.Therefore, compared with the respective embodiments described above 1~6, dissipating for control semiconductor element 6 can further be improved It is hot.
The feature described in the respective embodiments described above (each example included) can also be directed to, with technically reconcilable Mode that scope is suitably combined is applied.
It is illustrated for embodiments of the present invention, it will be understood that embodiment of disclosure is all in all respects Illustrate, be not restricted content.The scope of the present invention is shown by claims, it is intended that comprising being equal with claims Implication and scope in whole changes.

Claims (7)

1. a kind of semiconductor device, it has：
Base plate；
Housing, it is arranged on the base plate；
Power semiconductor, it is configured on the base plate in the housing；And
Control semiconductor element, it is configured at the inside of the housing,
In housing side opposite with the base plate formed with opening portion,
The semiconductor device also has the lid of the opening port blocking of the housing,
At the lid, when overlooking, at least a portion in the region overlapping with the control semiconductor element is formed with hole Portion.
2. semiconductor device according to claim 1, wherein,
Also there is heat sink on the main surface of the side opposite with the base plate of the control semiconductor element,
The heat sink is configured to the hole portion occlusion of the lid.
3. semiconductor device according to claim 2, wherein,
The heat sink includes：
The part of 1st heat sink, it is contained in the hole portion of the lid；And
The part of 2nd heat sink, it extends to the private side of the housing from the part of the 1st heat sink,
The part of 2nd heat sink is contacted to the main surface of the side opposite with the base plate of the control semiconductor element On.
4. semiconductor device according to claim 1, wherein,
Entirety of the hole portion when overlooking during vertical view with the control semiconductor element is overlapping,
The control is configured in the hole portion with semiconductor element,
The main surface configuration of the side opposite with the base plate of the lid is in the same base with the control semiconductor element The position of the main surface co-planar of the opposite side of seat board or side opposite with the same base plate of the control semiconductor element Main surface is compared to the position for more leaning on the base plate side.
5. the semiconductor device according to claim 3 or 4, wherein,
Also there is Peltier's element in the top on the main surface of the side opposite with the base plate of the lid.
6. semiconductor device according to any one of claim 1 to 4, wherein,
The control includes packaging part with semiconductor element,
At least a portion on the surface of the packaging part includes the recess that multiple depth are more than or equal to 500 μm.
7. semiconductor device according to any one of claim 1 to 4, wherein,
Also there is high-cooling property resin in the housing, the high-cooling property resin is to be carried out to the power semiconductor What the mode of encapsulation was filled, thermal conductivity is more than or equal to 0.5W/ (mK).
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