CN107437938B - Voltage controlled oscillator circuit - Google Patents
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Abstract
The embodiment of the invention discloses a voltage-controlled oscillator circuit, which comprises a control unit, a differential complementary unit and a resonant circuit unit which are electrically connected in sequence; the differential complementary unit comprises a plurality of basic units, and the control unit comprises switch units which are in one-to-one correspondence with the basic units; the basic units comprise a group of cross-coupled PMOS tubes and a group of cross-coupled NMOS tubes, the width-length ratios of the PMOS tubes in the adjacent basic units are arranged in an equal-ratio array by a first common ratio, the width-length ratios of the NMOS tubes in the adjacent basic units are arranged in an equal-ratio array by a second common ratio, and the first common ratio is the same as the second common ratio. The control unit controls the on-off of the switch unit according to a preset arrangement and combination rule, and further controls the basic unit to be in a working state or in a non-working state to form a plurality of continuous narrow frequency bands, and the resonant circuit unit tunes the continuous narrow frequency bands to enable the differential complementary unit to output a preset wide frequency. The embodiment of the invention has the characteristics of wide tuning range, stable tuning oscillation amplitude and low power consumption.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a voltage-controlled oscillator circuit.
Background
The voltage-controlled oscillator is a key component of the frequency synthesizer, and has direct influence on important performances of the phase-locked loop frequency synthesizer, such as frequency coverage, phase noise, power consumption, and transfer function, so that among all unit circuits of the wireless transceiver, a CMOS fully integrated inductor-capacitor voltage-controlled oscillator (LCVCO) is a radio frequency unit circuit which is widely concerned in the industry and academia. With the maturity of the on-chip inductance simulation technology and the improvement of theoretical analysis, the lc voltage-controlled oscillator has become the mainstream oscillator structure in the aspect of high-frequency application. For the performance index of the voltage-controlled oscillator, the following points need to be paid attention:
1. center frequency: the middle of the oscillator maximum and minimum frequencies.
2. Tuning range: the difference between the maximum frequency and the minimum frequency of the oscillator.
3. Tuning linearity: ideally, it is desirable that the gain of the voltage-controlled oscillator is kept constant in the whole tuning range, but the actual circuit is difficult to achieve, which requires that the voltage-controlled gain keeps a small fluctuation range in the whole tuning range, and good linearity of the frequency with the voltage is achieved.
4. Phase noise: i.e., the decibel representation of the ratio of the single sideband noise spectral density to the carrier power within 1Hz at the carrier frequency offset.
5. Output voltage amplitude: in view of reducing phase noise, it is desirable that the output voltage amplitude is large, and especially, as the CMOS process is advanced and the voltage is reduced, it is more important to increase the output voltage amplitude.
6. Power consumption: the power consumption of the voltage-controlled oscillator occupies most of the weight in the frequency synthesizer, and is particularly important for balancing and optimizing the power consumption, the phase noise and the output voltage amplitude.
For the performance indexes, voltage-controlled oscillators with different structures meet the performance required by products through reasonable design. The frequency tuning range of a commercial CDMA/WLAN/GSM wireless receiver is relatively small, generally about 20%, and the bandwidth of a signal channel can be completely covered by adopting a method of connecting a fixed capacitor and a variable capacitor in parallel. For wideband receiver systems such as digital trunked walkie-talkie rf chips and digital tv tuners, the tuning range is required to reach 50%, and this range is often further extended to reach sufficient design margin in order to compensate for process and temperature drift. In order to meet the broadband tuning range required by a broadband receiver system and the like, a broadband voltage controlled oscillator is available on the market, however, the broadband voltage controlled oscillator on the market often has the problems of not wide tuning range, unstable tuning oscillation amplitude and large power consumption, and is difficult to meet the use requirement of the broadband receiver system and the like.
Therefore, a voltage-controlled oscillator circuit with a wide tuning range, a stable tuning oscillation amplitude, and a small power consumption is urgently needed.
Disclosure of Invention
The embodiment of the invention provides a voltage-controlled oscillator circuit which has the characteristics of wide tuning range, stable tuning oscillation amplitude and low power consumption.
The embodiment of the invention provides a voltage-controlled oscillator circuit, which is used for generating a preset broadband and is characterized by comprising a control unit, a differential complementary unit and a resonant circuit unit which are electrically connected in sequence; the differential complementary unit comprises a plurality of basic units, and the control unit comprises switch units which control the working states of the basic units and correspond to the basic units one by one; the basic units comprise a group of cross-coupled PMOS tubes and a group of cross-coupled NMOS tubes, the width-length ratios of the PMOS tubes in the adjacent basic units are arranged in an equal-ratio array by a first common ratio, the width-length ratios of the NMOS tubes in the adjacent basic units are arranged in an equal-ratio array by a second common ratio, and the first common ratio is the same as the second common ratio; the control unit controls the on-off of the switch unit according to a preset permutation and combination rule to control the basic unit corresponding to the switch unit to be in a working state or in a non-working state to form a plurality of continuous narrow frequency bands, and the resonant circuit unit tunes the continuous narrow frequency bands to enable the differential complementary unit to output the preset broadband.
Preferably, the number of the basic units is n, n is larger than or equal to 1, the number of the switch units is n, and the preset permutation and combination rule is that 2 is generated by the on-off of the n switch unitsn-1 state combination, and the control unit controls the on-off of the switch unit according to the gradually increasing manner of the binary numerical value to divide the preset wide frequency into 2n-1 state combination corresponding to a contiguous narrowband.
Preferably, the basic unit is connected between a power supply unit and a switch unit, the group of cross-coupled PMOS transistors includes a first PMOS transistor and a second PMOS transistor, the group of cross-coupled NMOS transistors includes a first NMOS transistor and a second NMOS transistor, the power supply unit is connected to a source of the first PMOS transistor and a source of the second PMOS transistor at the same time, a gate of the first PMOS transistor is connected to a drain of the second PMOS transistor, a gate of the second PMOS transistor is connected to a drain of the first PMOS transistor, the switch unit is connected to a source of the first NMOS transistor and a source of the second NMOS transistor at the same time, a gate of the first NMOS transistor is connected to a drain of the second NMOS transistor, a gate of the second NMOS transistor is connected to a drain of the first NMOS transistor, and a drain of the first PMOS transistor is connected to a drain of the first NMOS transistor and serves as a first common drain terminal of the basic unit, and a first common drain terminal of each basic unit is connected to form a first output terminal of the differential complementary unit, and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube and is used as a second common drain electrode end of the basic unit, the second common drain electrode end of each basic unit is connected to form a second output end of the differential complementary unit, and the resonant loop unit is connected between the first output end and the second output end.
Preferably, the switch unit includes a third NMOS transistor, a drain of the third NMOS transistor is connected to a source of the first NMOS transistor and a source of the second NMOS transistor at the same time, a source of the third NMOS transistor is grounded, a gate of the third NMOS transistor is connected to the first digital control signal, when the first digital control signal is at a high level, the switch unit is turned on to control the basic unit corresponding to the switch unit to be in an operating state, and when the first digital control signal is at a low level, the switch unit is turned off to control the basic unit corresponding to the switch unit to be in an inoperative state.
Preferably, the resonant tank unit includes a first switched capacitor array, a second switched capacitor array, and an LC resonant tank unit, the first switched capacitor array and the second switched capacitor array are arranged on two sides of the differential complementary unit in a mirror image manner, the first switched capacitor array is connected to the first output end, the second switched capacitor array is connected to the second output end, one end of the LC resonant tank unit is connected to the first output end, and the other end of the LC resonant tank unit is connected to the second output end; the first switched capacitor array comprises a plurality of switched capacitor units connected in parallel, each switched capacitor unit comprises a capacitor and a fourth NMOS (N-channel metal oxide semiconductor) tube, one end of each capacitor is connected with the first output end, the other end of each capacitor is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fourth NMOS tube is connected with a second digital control signal, and the source electrode of the fourth NMOS tube is grounded; the LC resonance circuit unit comprises an inductor, a first adjustable capacitor and a second adjustable capacitor, one end of the inductor is connected with the first output end, the other end of the inductor is connected with the second output end, one end of the first adjustable capacitor is connected with the first output end, the other end of the first adjustable capacitor is connected with one end of the second adjustable capacitor, and the other end of the second adjustable capacitor is connected with the second output end.
Preferably, the capacitance values of the capacitors in the adjacent switched capacitor units in the first switched capacitor array are arranged in an equal-ratio array with a first common ratio, and the width-to-length ratios of the fourth NMOS transistors in the adjacent switched capacitor units are arranged in an equal-ratio array with the first common ratio.
Preferably, the first switched capacitor array comprises m parallel switched capacitor units, m is larger than or equal to 1, and divides the continuous narrow frequency band into 2mAnd (4) each interval. The drain parasitic capacitance of the fourth NMOS tube with the minimum width-length ratio is CdWhen all the m fourth NMOS transistors are turned on and the first variable capacitor and the second variable capacitor have the maximum value CmaxAnd then, obtaining the minimum working frequency of the voltage-controlled oscillator as follows:
when all the m fourth NMOS transistors are turned off, the first variable capacitor and the second variable capacitor have the minimum value CminThen, the maximum frequency of the voltage-controlled oscillator is obtained:
in order to ensure that adjacent frequency intervals have a certain frequency overlap, the maximum capacitance value C of the variable capacitormaxAnd minimum capacitance CminIt must satisfy:
the basic units comprise a group of cross-coupled PMOS tubes and a group of cross-coupled NMOS tubes, the width-length ratios of the PMOS tubes in adjacent basic units are arrayed in an equal ratio array by a first common ratio, the width-length ratios of the NMOS tubes in adjacent basic units are arrayed in an equal ratio array by a second common ratio, the first common ratio is the same as the second common ratio, the control unit comprises switch units which control the working states of the basic units and are in one-to-one correspondence with the basic units, the control unit controls the on-off of the switch units according to a preset array combination rule to control the basic units corresponding to the switch units to be in the working state or in the non-working state to form a plurality of continuous narrow frequency bands, and the resonant circuit unit tunes the plurality of continuous narrow frequency bands to enable the broadband complementary unit to output the preset broadband. The embodiment of the invention has the characteristics of wide tuning range, stable tuning oscillation amplitude and low power consumption.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a voltage-controlled oscillator circuit according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a basic unit and a switch unit according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a first switched capacitor array provided by an embodiment of the invention;
FIG. 4 is a schematic circuit diagram of an LC tank unit provided by an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a differential complementary unit and a control unit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 5, the voltage-controlled oscillator circuit according to an embodiment of the present invention is configured to generate a predetermined wideband, and includes a control unit 10, a differential complementary unit 11, and a resonant tank unit 12, which are electrically connected in sequence.
The differential complementary unit 11 includes a basic unit 1 to a basic unit n, where n is 1 or more. The basic units 1 to n respectively comprise a group of cross-coupled PMOS tubes and a group of cross-coupled NMOS tubes, the width-length ratios of the PMOS tubes in the adjacent basic units are arrayed in an equal ratio array according to a first common ratio, the width-length ratios of the NMOS tubes in the adjacent basic units are arrayed in an equal ratio array according to a second common ratio, and the first common ratio is the same as the second common ratio. In the embodiment of the invention, the width-to-length ratio of the PMOS tube is set as (W/L)pThe first common ratio and the second common ratio are both set to be 2, and the width and the length of the PMOS tube in the basic unit 1 to the basic unit n are respectively (W/L)p、2(W/L)p、22(W/L)pAnd 2n(W/L)pThe width and length of the NMOS tubes in the basic units 1 to n are (W/L)n、2(W/L)n、22(W/L)nAnd 2n(W/L)n。
The control unit 10 includes switching units Pwr <1> to Pwr < n > that control the operating states of the basic units 1 to n and correspond one-to-one to the basic units 1 to n.
Specifically, taking the basic unit 1 as an example, the set of cross-coupled PMOS transistors in the basic unit 1 includes a first PMOS transistor Q1 and a second PMOS transistor Q2, and the set of cross-coupled NMOS transistors includes a first NMOS transistor Q3 and a second NMOS transistor Q4. It can be understood that the first PMOS transistor Q1 and the second PMOS transistor Q2 are identical, and the first NMOS transistor Q3 and the second NMOS transistor Q4 are identical, so as to implement cross coupling. Referring to fig. 2, the source of the first PMOS transistor Q1 and the source of the second PMOS transistor Q2 are connected to the power supply unit VDD, the gate of the first PMOS transistor Q1 is connected to the drain of the second PMOS transistor Q2, the gate of the second PMOS transistor Q2 is connected to the drain of the first PMOS transistor Q1, the switch unit Pwr <1> is connected to the source of the first NMOS transistor Q3 and the source of the second NMOS transistor Q4, the gate of the first NMOS transistor Q3 is connected to the drain of the second NMOS transistor Q4, the gate of the second NMOS transistor Q4 is connected to the drain of the first NMOS transistor Q3, and the drain of the first PMOS transistor Q1 is connected to the drain of the first NMOS transistor Q3 as the first common drain terminal SINP of the basic cell 1, and the drain of the basic cell Q2 is connected to the first common drain terminal SINP of the basic cell n to form the first output terminal OUT1 of the differential complementary cell 11, the drain of the second PMOS transistor Q2 is connected to the second common drain of the second NMOS transistor Q4 as the common drain of the basic cell SINN, and connects the basic cell 2 to the second common drain terminal SINN of the basic cell n to form the second output terminal OUT2 of the differential complementary cell 11.
Preferably, the structures of the switching units Pwr <1> to Pwr < n > are the same, and the switching unit Pwr <1> is taken as an example for explanation. The switch unit Pwr <1> comprises a third NMOS transistor Q5, the drain electrode of the third NMOS transistor Q5 is simultaneously connected with the source electrode of the first NMOS transistor Q3 and the source electrode of the second NMOS transistor Q4, the source electrode of the third NMOS transistor Q5 is grounded, and the grid electrode of the third NMOS transistor Q5 is connected with a first digital control signal. The first digital control signal may be an output signal of any digital circuit/device, and is not limited herein. When the first digital control signal is at high level, the switch unit Pwr <1> is turned on to control the base unit 1 to be in working state, and when the first digital control signal is at low level, the switch unit Pwr <1> is turned off to control the base unit 1 to be in non-working state.
The resonant tank unit 12 includes a first switched capacitor array 121, a second switched capacitor array 122 and an LC resonant tank unit 123, the first switched capacitor array 121 and the second switched capacitor array 122 are arranged on two sides of the differential complementary unit 11 in a mirror image manner, the first switched capacitor array 121 is connected to the first output terminal OUT1, the second switched capacitor array 122 is connected to the second output terminal OUT2, one end of the LC resonant tank unit 123 is connected to the first output terminal OUT1, and the other end of the LC resonant tank unit 123 is connected to the second output terminal OUT 2. In this embodiment of the present invention, the first switched capacitor array 121 includes a plurality of switched capacitor units a connected in parallel, where the switched capacitor unit a includes a capacitor C1 and a fourth NMOS transistor Q6, one end of the capacitor C1 is connected to the first output terminal OUT1, the other end is connected to the drain of the fourth NMOS transistor Q6, the gate of the fourth NMOS transistor Q6 is connected to the second digital control signal B1, and the source of the fourth NMOS transistor Q6 is grounded. Wherein the second digital controlThe signal is independent of the first digital control signal. Since the second switched capacitor array 122 and the first switched capacitor array 121 are arranged on two sides of the differential complementary unit 11 in a mirror image manner, that is, the second switched capacitor array 122 and the first switched capacitor array 121 have the same structure, and are not described herein again. Referring to fig. 4, the LC resonant tank unit 123 includes an inductor L, a first adjustable capacitor CV1, and a second adjustable capacitor CV2, wherein one end of the inductor L is connected to the first output terminal OUT1, the other end is connected to the second output terminal OUT2, one end of the first adjustable capacitor CV1 is connected to the first output terminal OUT1, and the other end is simultaneously connected to the control voltage VtAnd one end of a second adjustable capacitor CV2, and the other end of the second adjustable capacitor CV2 is connected to a second output terminal OUT2, wherein the first adjustable capacitor CV1 is the same as the second adjustable capacitor CV 2.
In the embodiment of the present invention, the capacitance values of the capacitors C1 in the adjacent switched capacitor units a in the first switched capacitor array 121 are arranged in an equal-ratio array with a first common ratio, and the width-to-length ratios of the fourth NMOS transistors Q6 in the adjacent switched capacitor units a are arranged in an equal-ratio array with a first common ratio. For example, the first switched capacitor array 121 comprises m parallel switched capacitor units A, and divides the continuous narrow frequency band into 2mAnd (4) each interval. The drain parasitic capacitance of the fourth NMOS transistor Q6 with the minimum width-to-length ratio is CdThen, when all the m fourth NMOS transistors Q6 are turned on and the first adjustable capacitor CV1 and the second adjustable capacitor CV2 have the maximum value CmaxAnd then, obtaining the lowest frequency output by the voltage-controlled oscillator as follows:
when all the m fourth NMOS transistors Q6 are turned off, the first adjustable capacitor CV1 and the second adjustable capacitor CV2 have the minimum value CminAnd then, obtaining the highest frequency output by the voltage-controlled oscillator as follows:
to ensure a certain frequency overlap between adjacent frequency bins, the maximum capacitance C of the first and second adjustable capacitors CV1 and CV2maxAnd minimum capacitance CminIt must satisfy:
in the embodiment of the present invention, the control unit 10 controls the switch units Pwr according to the preset permutation and combination rule<1>To the switching unit Pwr<n>On/off of (2), and thus control and switch unit Pwr<1>To the switching unit Pwr<n>The corresponding basic units 1 to n are in an operating state or an inoperative state to form a plurality of continuous narrow bands Δ H, the plurality of continuous narrow bands Δ H form a preset wideband Δ F, and the differential complementary unit 11 outputs the preset wideband Δ F by adjusting the resonant circuit unit 12. Wherein the preset permutation and combination rule is that the switch unit Pwr<1>To the switching unit Pwr<n>On-off generation 2n1 state combination, and the control unit 10 controls the switching unit Pwr in a gradually increasing manner according to the binary value<1>To the switching unit Pwr<n>The on-off of the predetermined wide band Δ F is divided into 2n1 state combination corresponding to a contiguous narrowband Δ H.
Referring to fig. 5, in the embodiment of the present invention, n is 3, that is, the differential complementary unit 11 includes the basic units 1 to 3, and the control unit 10 includes the switching unit Pwr<1>To the switching unit Pwr<3>. The choice of n depends on the performance requirement of the phase noise, the size of the cross-coupled tube transconductance required for the high and low frequency oscillation starting, and the consideration of the overall power consumption budget and the required oscillation amplitude. Switch unit Pwr<1>A group of cross-coupled PMOS tubes Q1 and Q2 and a group of cross-coupled NMOS tubes Q3 and Q4 are controlled, and the width-to-length ratio of the PMOS tubes Q1 and Q2 is (W/L)pThe width-to-length ratio of the NMOS tubes Q3 and Q4 is (W/L)n(ii) a Switch unit Pwr<2>A group of cross-coupled PMOS tubes Q11 and Q12 and a group of cross-coupled NMOS tubes Q13 and Q14 are controlled, and the width-to-length ratio of the PMOS tubes Q11 and Q12 is 2(W/L)pThe width-to-length ratio of the NMOS tubes Q13 and Q14 is 2(W/L)n(ii) a Switch unit Pwr<3>A group of cross-coupled PMOS tubes Q21 and Q22 and a group of cross-coupled NMOS tubes Q23 and Q24 are controlled, and the width-to-length ratio of the PMOS tubes Q21 and Q22 is 4(W/L)pThe width-to-length ratio of the NMOS tubes Q23 and Q24 is 4(W/L)n。
The on-off of the switch units Pwr <1> to Pwr <3> generates seven state combinations, namely, the states of the switch units Pwr <1> to Pwr <3> when the switch units are conducted are set as binary high level 1, the states of the switch units Pwr <1> to Pwr <3> when the switch units are not conducted are set as binary low level 0, and the corresponding binary bits of the switch units Pwr <1> to Pwr <3> are sequentially set as low bit and high bit. If the switch unit Pwr <1> is conducted and the switch unit Pwr <2> and the switch unit Pwr <3> are not conducted, the corresponding binary bit is: 001, only the basic unit 1 is in an operating state at this time, the basic unit 2 and the basic unit 3 are both in a non-operating state, and the state of the control unit 10 at this time is taken as a first state; if the switch unit Pwr <2> is conducted and the switch unit Pwr <1> and the switch unit Pwr <3> are not conducted, the corresponding binary bit is: 010, only the basic unit 2 is in working state, the basic unit 1 and the basic unit 3 are in non-working state, and the state of the control unit 10 is taken as the second state; if the switching unit Pwr <3> is not conducted and the switching unit Pwr <1> and the switching unit Pwr <2> are both conducted, the corresponding binary bit is: 011, the basic unit 1 and the basic unit 2 are in working state, the basic unit 3 is in non-working state, and the state of the control unit 10 is taken as the third state; by analogy, binary permutation and combination are carried out on the switch units Pwr <1> to the switch units Pwr <3> in the conducting state, and the corresponding states are named according to the decimal sizes corresponding to the corresponding binary bits, for example, when the switch units Pwr <1> are conducted, and the switch units Pwr <2> and the switch units Pwr <3> are both conducted, the corresponding binary bits are as follows: 111, the basic units 1 to 3 are all in working state, and the state of the control unit 10 is the seventh state. It should be noted that, when the switch unit Pwr <1> is not turned on, and the switch unit Pwr <2> and the switch unit Pwr <3> are not turned on, the corresponding binary bits are: 000, since the basic units 1 to 3 are not in the operating state and the frequency tuning is not possible, the states of the switching units Pwr <1> to Pwr <3> that are not on are not counted.
The preset wideband Δ F can be divided into seven consecutive narrowband Δ H with equal frequency spacing according to the preset wideband Δ F and the seven states controlled by the control unit 10, and the frequency spacing is equal to the preset wideband Δ F/7. If a 1.4GHz bandwidth preset between 1.0GHz and 2.4GHz is to be implemented, the corresponding frequency interval is 1.4GHz/7 is 0.2 GHz. Therefore, the first state to the seventh state correspond to the continuous narrow band with the bandwidth of 0.2GHz in sequence, specifically:
the first state 001 corresponds to the highest continuous narrow band, the continuous narrow band Δ H is 2.2GHz-2.4GHz, and the total number of the width-to-length ratios of the PMOS transistors or the NMOS transistors in the working state is 1; the second state 010 corresponds to a higher continuous narrow band, the continuous narrow band Δ H is 2.0GHz-2.2GHz, and the total number of the width-to-length ratios of the PMOS transistors or the NMOS transistors in the working state is 2; the continuous narrow band Δ H corresponding to the third state 011 is 1.8GHz-2.0GHz, and the total number of the width-to-length ratios of the PMOS transistors or the NMOS transistors in the working state is 3; the continuous narrow band Δ H corresponding to the fourth state 100 is 1.6GHz-1.8GHz, and the total number of the width-to-length ratios of the PMOS transistors or the NMOS transistors in the operating state is 4; the continuous narrow band Δ H corresponding to the fifth state 101 is 1.4GHz-1.6GHz, and the total number of the width-to-length ratios of the PMOS transistors or the NMOS transistors in the working state is 5; the sixth state 110 corresponds to a lower continuous narrow band, and the continuous narrow band Δ H is 1.2GHz-1.4GHz, and the total number of the width-to-length ratios of the PMOS transistors or the NMOS transistors in the operating state is 6; the seventh state 111 corresponds to the lowest continuous narrow band, and the continuous narrow band Δ H is 1.0GHz-1.2GHz, and the total number of the width-to-length ratios of the PMOS transistors or the NMOS transistors in the operating state is 7. In the embodiment of the invention, the preset broadband delta F is divided into 2 by the number n of the basic units in the differential complementary unit 11 and the binary permutation and combination mode n1 successive narrow bands Δ H and 2 of control unit 10nThe 1 state corresponds to the total number of PMOS tubes or NMOS tubes in the working state in a linear mode.
In the embodiment of the present invention, the first switched capacitor array 121 in the resonant tank unit 12 includes 4 switched capacitor units a connected in parallel, that is, m is 4, and the continuous narrowband Δ H is divided into 16 sections, and the interval distance is continuous narrowband Δ H/16. The second control signals are respectively B1, B2, B3 and B4, the second control signals are respectively B1 to control the capacitor C1 and the fourth NMOS Q6, the second control signals are respectively B2 to control the capacitor C2 and the fourth NMOS Q7, the third control signals are respectively B3 to control the capacitor C3 and the fourth NMOS Q8, and the fourth control signals are respectively B4 to control the capacitor C4 and the fourth NMOS Q9. In addition, the capacitance values of the capacitors C1, C2, C3 and C4 are arranged in an equal-ratio array with a first common ratio, and the width-to-length ratios of the fourth NMOS transistors Q6, Q7, Q8 and Q9 are arranged in an equal-ratio array with the first common ratio.
In addition, the control voltage V in the LC tank unit 123tFor automatic continuous adjustable voltage in phase-locked loop, by adjusting control voltage VtTo change the capacitance values of the first adjustable capacitor CV1 and the second adjustable capacitor CV2 to achieve further adjustment of the output frequency. In the embodiment of the present invention, the first switched capacitor array 121 of the resonant tank unit 12 divides the continuous narrow frequency band Δ H into 2mIn each interval, and adjusting the control voltage VtThe capacitance values of the first adjustable capacitor CV1 and the second adjustable capacitor CV2 are changed to realize continuous fine tuning of the continuous narrow frequency band Δ H, so as to realize frequency coverage of the preset wide frequency band.
In the embodiment of the present invention, when the control unit 10 is in the first state 001, the corresponding continuous narrow band is the highest continuous narrow band, and only the basic unit 1 corresponding to the switch unit Pwr <1> is in the operating state and provides a negative resistance for the voltage-controlled oscillator circuit, at this time, the power consumption of the entire voltage-controlled oscillator circuit is small. With the control unit 10 controlling the conduction of different switch units according to binary bits, the switch units 1 to 3 are sequentially set to 010, 011, 100 … … to 111, so that the output frequency of the voltage controlled oscillator circuit is reduced to reach the lowest continuous narrow band, thereby outputting the preset bandwidth.
The voltage-controlled oscillator circuit has the characteristic of low power consumption during high-frequency output, can meet the requirement of normal oscillation starting of the oscillator during low-frequency output, and has stable output oscillation amplitude in a high-low frequency range. The embodiment of the invention can output the frequency band according to the preset frequency width, and has the characteristics of wide tuning range, stable tuning oscillation amplitude and low power consumption.
The above are preferred embodiments of the invention and are not intended to limit the invention in any way. Various equivalent changes and modifications can be made by those skilled in the art based on the above-described embodiments, and all equivalent changes and modifications within the scope of the claims should be considered as falling within the scope of the present invention.
Claims (2)
1. A voltage-controlled oscillator circuit is used for generating a preset broadband and is characterized by comprising a control unit, a differential complementary unit and a resonant circuit unit which are electrically connected in sequence; the differential complementary unit comprises a plurality of basic units, and the control unit comprises switch units which control the working states of the basic units and correspond to the basic units one by one; the basic units comprise a group of cross-coupled PMOS tubes and a group of cross-coupled NMOS tubes, the width-length ratios of the PMOS tubes in the adjacent basic units are arranged in an equal-ratio array by a first common ratio, the width-length ratios of the NMOS tubes in the adjacent basic units are arranged in an equal-ratio array by a second common ratio, and the first common ratio is the same as the second common ratio; the control unit controls the on-off of the switch unit according to a preset permutation and combination rule to control the basic unit corresponding to the switch unit to be in a working state or in a non-working state to form a plurality of continuous narrow frequency bands, and the resonant circuit unit tunes the continuous narrow frequency bands to enable the differential complementary unit to output the preset broadband;
the number of the basic units is n, n is more than or equal to 1, the number of the switch units is n, the preset arrangement and combination rule is that 2n-1 state combinations are generated by the on-off of the n switch units, and the control unit controls the on-off of the switch units according to a gradually increasing binary value mode to divide a preset broadband into continuous narrow frequency bands corresponding to the 2n-1 state combinations;
the basic unit is connected between a power supply unit and a switch unit, the group of cross-coupled PMOS tubes comprises a first PMOS tube and a second PMOS tube, the group of cross-coupled NMOS tubes comprises a first NMOS tube and a second NMOS tube, the power supply unit is simultaneously connected with a source electrode of the first PMOS tube and a source electrode of the second PMOS tube, a grid electrode of the first PMOS tube is connected with a drain electrode of the second PMOS tube, a grid electrode of the second PMOS tube is connected with a drain electrode of the first PMOS tube, the switch unit is simultaneously connected with a source electrode of the first NMOS tube and a source electrode of the second NMOS tube, a grid electrode of the first NMOS tube is connected with a drain electrode of the second NMOS tube, a grid electrode of the second NMOS tube is connected with a drain electrode of the first NMOS tube, a drain electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube and serves as a first common drain electrode terminal of the basic unit, and a first common drain electrode terminal of each basic unit is connected to form a first output end of the differential complementation unit, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and is used as a second common drain electrode end of the basic unit and connected with the second common drain electrode end of each basic unit to form a second output end of the differential complementary unit;
the resonant circuit unit comprises a first switch capacitor array, a second switch capacitor array and an LC resonant circuit unit, the first switch capacitor array and the second switch capacitor array are arranged on two sides of the differential complementary unit in a mirror image mode, the first switch capacitor array is connected with the first output end, the second switch capacitor array is connected with the second output end, one end of the LC resonant circuit unit is connected with the first output end, and the other end of the LC resonant circuit unit is connected with the second output end; the first switched capacitor array comprises a plurality of switched capacitor units connected in parallel, each switched capacitor unit comprises a capacitor and a fourth NMOS (N-channel metal oxide semiconductor) tube, one end of each capacitor is connected with the first output end, the other end of each capacitor is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fourth NMOS tube is connected with a second digital control signal, and the source electrode of the fourth NMOS tube is grounded; the LC resonance circuit unit comprises an inductor, a first adjustable capacitor and a second adjustable capacitor, one end of the inductor is connected with the first output end, the other end of the inductor is connected with the second output end, one end of the first adjustable capacitor is connected with the first output end, the other end of the first adjustable capacitor is simultaneously connected with a control voltage and one end of the second adjustable capacitor, and the other end of the second adjustable capacitor is connected with the second output end;
the capacitance values of the capacitors in the adjacent switch capacitor units in the first switch capacitor array are arranged in an equal-ratio array according to a first common ratio, and the width-length ratios of the fourth NMOS tubes in the adjacent switch capacitor units are arranged in an equal-ratio array according to the first common ratio;
the first switched capacitor array comprises m switched capacitor units connected in parallel, wherein m is more than or equal to 1, the continuous narrow frequency band is divided into 2m intervals, the drain parasitic capacitance of the fourth NMOS tube with the minimum width-length ratio is Cd, and when the m fourth NMOS tubes are all switched on and the first variable capacitor and the second variable capacitor have the maximum value Cmax, the minimum working frequency of the voltage-controlled oscillator is obtained as follows:
when all the m fourth NMOS transistors are turned off and the first variable capacitor and the second variable capacitor have the minimum value Cmin, the maximum frequency of the voltage-controlled oscillator is obtained:
in order to ensure that adjacent frequency intervals have certain frequency overlap, the maximum capacitance Cmax and the minimum capacitance Cmin of the variable capacitor must satisfy:
2. the circuit of claim 1, wherein the switch unit includes a third NMOS transistor, a drain of the third NMOS transistor is connected to a source of the first NMOS transistor and a source of the second NMOS transistor, a source of the third NMOS transistor is grounded, a gate of the third NMOS transistor is connected to the first digital control signal, the switch unit is turned on to control the basic unit corresponding to the switch unit to be in the operating state when the first digital control signal is at a high level, and the switch unit is turned off to control the basic unit corresponding to the switch unit to be in the non-operating state when the first digital control signal is at a low level.
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| CN108365830A (en) * | 2018-01-26 | 2018-08-03 | 深圳骏通微集成电路设计有限公司 | A kind of power-sensing circuit |
| EP4156506A4 (en) * | 2020-06-19 | 2023-07-26 | Huawei Technologies Co., Ltd. | Oscillator circuit |
| TWI790867B (en) | 2021-12-21 | 2023-01-21 | 財團法人工業技術研究院 | Voltage-controlled oscillator device |
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