A kind of digital optimal control method and its system of the synchronous rectification of LLC full-bridge converter
Technical field
The present invention relates to the LLC resonant full bridge switch converters more particularly to a kind of LLC full-bridge using synchronous rectification mode
The digital optimal control method and its system of transducer synchronous rectification.
Background technique
Currently, the switching frequency in LLC power converter is higher and higher, switching frequency to increase the advantages of bringing as follows:
1. energy storage device (inductance, transformer, capacitor etc.) volume in circuit reduces accordingly.2. the power density of entire circuit is into one
Step increases.But the increase of switching frequency also brings the increase of various switching losses and conduction loss, thus synchronous rectification quilt
The rectification to replace diode is widely applied, especially in the case where exporting high current.
Currently, being applied to the synchronous rectification control method of LLC topological circuit has 3 classes: electric current testing;The quasi- electricity of self-powered dynamic model
Press detection method;It is leading digital detecting technique with microcontroller or FPGA.Wherein, current detection technology is more accurate, but
The energy loss for being resistance brought by current detecting is efficiency that is comparable big, therefore will affect whole topology.Detection
Synchronous rectifier drain terminal voltage becomes the efficient synchronous rectification control program of only one, based on detection synchronous rectifier hourglass source electrode
The analog voltage detection technique of voltage has sufficiently complex circuit structure, is just unable to satisfy the requirement of high power density in this way, together
When, such technology will lead to parasitic gate concussion.It is leading digital detecting technique with microcontroller or FPGA is to compare at present
Preferable source-drain voltage detection technique, currently, a kind of more common synchronous rectification control program mainly detect synchronize it is whole
Whether the body diode of flow tube is connected, adaptive rapidly if conducting to close synchronous rectifier, but this scheme mainly by
The influence that body diode conducting and reverse-conducting switch between the two, can be such that entire LLC circuit efficiency reduces, while corresponding
The ratio that latency issue can highlight at high frequencies is more serious.
As present generation power supplies are towards high power density, efficient development, excellent simple digital synchronous rectifies controlling party
Very it is necessary to be particularly important LLC secondary synchronous rectifier in best shutdown point shutdown to method.
Summary of the invention
Object of the present invention is to be directed to the deficiency of existing LLC circuit pair side synchronous rectification control method, it is complete to provide a kind of LLC
The digital optimal control method and its system of bridge transducer synchronous rectification can be such that LLC secondary synchronous rectifier is most preferably turning off
Point shutdown.
To achieve the goals above, the technical solution taken is as follows by the present invention: a kind of LLC full-bridge converter synchronous rectification
Digital optimal control method is adaptively adjusted shutdown based on the drain terminal voltage for detecting full-bridge LLC secondary synchronous rectifier
The time of LLC secondary synchronous rectifier, it is characterised in that: to before the shutdown of the synchronous rectifier on full-bridge LLC pair side and shutdown
Drain terminal voltage afterwards is sampled respectively, double sampling result is carried out logical comparison by comparator, according to logical comparison knot
Fruit is adjusted by turn-off time of the microcontroller to full-bridge LLC secondary synchronous rectifier and the interruption of microcontroller is utilized to match
Close, realize the accurate sampling of LLC secondary synchronous rectifier shutdown front and back source and drain end voltage, by compare in real time by microcontroller to
The time order that needs out adjust, realizes that full-bridge LLC secondary synchronous rectifier is turned off in the best time, improves full-bridge LLC electricity
The whole efficiency on road.
The following steps are included:
1) first in one cycle, before the shutdown of full-bridge LLC secondary synchronous rectifier, synchronous rectification is detected for the first time
The voltage of pipe drain terminal, while being stored in microcontroller and exporting the reference threshold electricity to comparator as logical comparison
Pressure, after the shutdown of full-bridge LLC secondary synchronous rectifier, the voltage of second of detection synchronous rectifier drain terminal;
2) the drain voltage i.e. reference threshold voltage and of obtained full-bridge LLC secondary synchronous rectifier will be detected for the first time
The drain terminal voltage for the full-bridge LLC secondary synchronous rectifier that secondary detection obtains carries out logical comparison, same with what is detected for the first time
Step rectifying tube drain terminal voltage subtract the drain terminal voltage of the synchronous rectifier detected for the second time as logical comparison as a result, if
Logical comparison result is positive, and illustrates the body diode conducting of synchronous rectifier, is then denoted as logical one, is otherwise denoted as logical zero;
3) microcontroller is transferred to adjust the turn-off time of full-bridge LLC secondary synchronous rectifier logical comparison result
It is whole.If the logical comparison result of output is " 1 ", microcontroller postpones a period of time shutdown full-bridge LLC in next cycle
Synchronous rectifier, if output logical comparison result be " 0 ", show that synchronous rectifier turn-off criterion is substantially met at this time;
4) it needs to carry out next step judgement when logical comparison result is " 0 ", the full-bridge LLC pair side for judging at this time synchronizes whole
Whether the drain terminal voltage of flow tube meets within safe range, i.e., the synchronous rectifier leakage of second of detection in guarantee a cycle
End voltage is negative, if the synchronous rectifier drain terminal voltage of second of detection is that canonical is expressed as not within safe range, to prevent
Only the time of synchronous rectifier shutdown occurs excessively adjusting phenomenon too late, leads to the consequence for electric current reverse irrigation occur;
5) it is " 0 " in logical comparison result, while meets the leakage of the synchronous rectifier detected for the second time within this period
End voltage is negative within i.e. safe range, then microcontroller keeps output constant to the clock signal of synchronous rectifier, i.e., at this time
The shutdown moment of synchronous rectifier is more satisfactory;
6) above-mentioned steps are recycled in next cycle, so that synchronous rectifier is turned off in optimum time point.
Cooperated using the interruption of microcontroller, realizes the accurate of LLC secondary synchronous rectifier shutdown front and back source-drain voltage
The method of sampling is as follows:
1) in one cycle, internal clocking failing edge is broken as in the logic unit at the t0 moment using microcontroller
Mouthful;
2) in the failing edge of t1 instance sample full-bridge LLC secondary synchronous rectifier drain voltage, microcontroller at this moment
Logic unit internal clocking generate interruption;
3) the t3 moment interrupts before full-bridge LLC secondary synchronous rectifier turns off, while sampling full-bridge LLC pair for the first time
The drain terminal voltage of synchronous rectifier;
4) the t4 moment interrupts after the shutdown of full-bridge LLC secondary synchronous rectifier, while second of sampling full-bridge LLC
The drain terminal voltage of secondary synchronous rectifier.
The control system of the digital optimal control method of above-mentioned LLC full-bridge converter synchronous rectification, it is characterised in that: including
Full-bridge LLC topological circuit, full-bridge LLC topological circuit secondary synchronous rectifier drain voltage detection circuit, using microcontroller as core
The control circuit and isolated drive circuit of the heart;
Full-bridge LLC topological circuit secondary synchronous rectifier drain voltage detection circuit includes full-bridge LLC topological circuit pair side
Drain terminal voltage sampling circuit, comparator CMP and the resistance R of synchronous rectifier0With capacitor C0The filter circuit of composition;Full-bridge LLC
The drain terminal voltage sampling circuit of topological circuit secondary synchronous rectifier includes resistance R1, resistance R2And diode Db, resistance R1's
One end connects power source voltage Vcc, resistance R1The other end connect resistance R2One end and diode DbAnode, diode Db's
Cathode connects the drain terminal of any one devices in the devices of two, side of full-bridge LLC topological circuit pair, electricity
Hinder R2The other end be the synchronous rectifier drain terminal voltage sample output end connect comparator CMP negative terminal, comparator CMP's
Output end connects resistance R0One end, resistance R0The other end connect capacitor C0One end and output end as filter circuit, electricity
Hold C0The other end ground connection;
It include digital analog converter DAC, analog-digital converter ADC0, logic control list by the control circuit of core of microcontroller
Member and two clock modules, the input terminal connection full-bridge LLC topological circuit secondary synchronous rectifier leakage of analog-digital converter ADC0
The output end of filter circuit in terminal voltage detecting circuit, output and the logic control element of analog-digital converter ADC0 are bi-directionally connected,
The output all the way of logic control element exports after a clock module is separately connected two, full-bridge LLC topological circuit pair side together
The grid of step rectification metal-oxide-semiconductor, another output connect after another clock module using isolated drive circuit output respectively
The grid of full-bridge LLC topological circuit four metal-oxide-semiconductors of primary side is connect, there are also export after digital analog converter DAC feedback link all the way extremely
The anode of comparator CMP in LLC topological circuit secondary synchronous rectifier drain voltage detection circuit;
When whole system start starting when, LLC topological circuit start to work, while the primary side metal-oxide-semiconductor of LLC topological circuit with
Secondary synchronous rectifier cooperating, secondary synchronous rectifier are turned off according to switching frequency is corresponding to the progress of the relationship of resonance frequency
The adjustment of time, LLC circuit secondary synchronous rectifier drain terminal detection circuit detects the drain terminal voltage of synchronous rectifier, in LLC pair
Detection detection synchronous rectifier drain terminal voltage, while the synchronous rectifier that will be detected for the first time for the first time before the shutdown of side rectifying tube
Drain terminal voltage the anode of comparator CMP is connected to as the reference threshold voltage of comparator, in LLC circuit pair side synchronous rectification
Second detection synchronous rectifier drain terminal voltage after pipe shutdown, and using the synchronous rectifier drain terminal voltage of second of detection as than
Negative terminal input signal compared with device CMP, the drain voltage detected twice are compared, when two pole of body of LLC secondary synchronous rectifier
When pipe is connected, the logic output of comparator CMP is " 1 ", controls LLC pair side by the control system that microcontroller is core at this time
Synchronous rectifier extends certain turn-on time in next cycle, while constantly judging that it compared patrols in the next period
Output is collected up to logic output is " 0 ", when it is " 0 " that comparator logic, which exports, while judging it in logic output for the week of " 0 "
In phase the drain terminal voltage of second of sampling guarantees that synchronizing for interior second of the detection of a cycle is whole whether within safe range
Flow tube drain terminal voltage is negative, and is expressed as not within safe range if the synchronous rectification tube voltage of second of detection is positive, with
The problem of overregulating is prevented, when the drain terminal voltage of second sampling meets in safe range, that is, the synchronous rectifier detected
After drain terminal voltage is negative, then the turn-off time of LLC secondary synchronous rectifier at this time is defaulted as the time most preferably turned off, at this time
The efficiency of entire LLC topological circuit has reached highest efficiency.
Advantages of the present invention and remarkable result:
1, using digital control, control more flexible compared to the application that traditional simulation controls digital control algorithm
Precision is more increased.
2, in same period, using the drain voltage of the LLC circuit secondary synchronous rectifier of first time sampling as this week
The comparator reference threshold value of phase has just obtained an exact references threshold value with periodic time self-adapting rather than in universal method in this way
A fixed threshold, thus its adaptive ability is stronger, and the time control of synchronous rectifier shutdown is more accurate.
3, in same period, the logic ratio of the drain voltage and the drain voltage of second of sampling of first time sampling is utilized
It is very concise and clear compared with the judgment criteria that value " 1 " or " 0 " adjust the turn-off time as the control system that microcontroller is core, have
Conducive to the more accurate turn-off time adjustment of realization.
4, in the mediation process of control system, while judging whether second of sampling is negative value i.e. safety in same period
It in range, is beneficial to prevent and overregulates, be achieved in accurate shutdown synchronous rectifier, improve efficiency.
Detailed description of the invention
Fig. 1 is control system block diagram of the present invention;
Fig. 2 is present system schematic diagram;
Fig. 3 is present invention control program flow diagram;
Fig. 4 is LLC circuit secondary synchronous rectifier source-drain voltage detection waveform figure;
Fig. 5 be the present invention under full load conditions with efficiency comparative's curve graph of universal control method.
Specific embodiment
The technical solution of invention is described in detail with reference to the accompanying drawing.
Such as Fig. 1,2, control system of the present invention includes full-bridge LLC topological circuit, full-bridge LLC topological circuit pair side synchronous rectification
Tube drain voltage detection circuit, using microcontroller as the control circuit of core and isolated drive circuit.Wherein, full-bridge LLC topology
Circuit secondary synchronous rectifier drain voltage detection circuit includes the drain terminal voltage of full-bridge LLC topological circuit secondary synchronous rectifier
Sample circuit, comparator CMP and resistance R0With capacitor C0The filter circuit of composition.Full-bridge LLC topological circuit pair side synchronous rectification
The drain terminal voltage sampling circuit of pipe includes resistance R1, resistance R2And diode Db, resistance R1One end connect power source voltage Vcc,
Resistance R1The other end connect resistance R2One end and diode DbAnode, diode DbCathode connection full-bridge LLC topology electricity
The drain terminal of devices M6 is (due to the drain terminal of any one in sampling two devices M6 or M5 in the pair side of road
Voltage is ok, and figure embodiment is by taking the drain terminal voltage for sampling M6 as an example, similarly hereinafter) resistance R1 and R2 carry out partial pressure sampling, resistance
R2The other end be devices M6 drain terminal voltage sample output end connect comparator CMP negative terminal, comparator CMP's
Output end connects resistance R0One end, resistance R0The other end connect capacitor C0One end and output end as filter circuit, electricity
Hold C0The other end ground connection.
It include digital analog converter DAC, analog-digital converter ADC0, logic control list by the control circuit of core of microcontroller
The input terminal connection topological circuit pair side full-bridge LLC of member and clock module 1 and clock module 2, analog-digital converter ADC0 is synchronous
The output end of filter circuit in tube drain voltage detection circuit is rectified, the output of analog-digital converter ADC0 and logic control element are double
To connection, the output all the way of logic control element exports after clock module 1 respectively drives full-bridge LLC topological circuit pair side two
The grid of a devices M5, M6, another output is after clock module 2, using isolated drive circuit output point
Not Qu Dong four metal-oxide-semiconductor M1- of full-bridge LLC topological circuit primary side M4 grid, it is anti-there are also exporting after digital analog converter DAC all the way
Feedback is connected to the anode of comparator CMP in LLC topological circuit secondary synchronous rectifier drain voltage detection circuit, to store simultaneously
The result that output synchronous rectifier M6 drain voltage samples for the first time in one cycle.
In present system, full-bridge LLC topological circuit secondary synchronous rectifier source and drain end voltage sampling circuit is in full-bridge LLC
The front and back of secondary synchronous rectifier shutdown samples simultaneously, is adopted by subtracting the voltage after shutdown using the voltage sample value before shutdown
Sample value obtains a logic judgment number, and logic judgment number is conveyed to and is realized by the control system of core of microcontroller
The turn-off time adjustment of real-time full-bridge LLC secondary synchronous rectifier, microcontroller are the control system output signal control of core
Full-bridge LLC secondary synchronous rectifier M5 and M6 processed is turned off in the best time.
The course of work of control system: when whole system starts starting, LLC topological circuit is started to work, while LLC is opened up
The primary side metal-oxide-semiconductor and secondary synchronous rectifier cooperating of circuit are flutterred, secondary synchronous rectifier is according to switching frequency and resonance frequency
The relationship of rate carries out the adjustment of corresponding turn-off time, and LLC circuit secondary synchronous rectifier drain electrode detection circuit detects synchronous rectification
The drain voltage of pipe, the detection detection synchronous rectifier drain voltage for the first time before LLC pair side rectifying tube turns off, while by first
The drain voltage of the secondary synchronous rectifier detected is connected to the anode of comparator CMP as the reference threshold voltage of comparator,
Second of detection synchronous rectifier drain voltage after the shutdown of LLC circuit secondary synchronous rectifier, and it is same by what is detected for the second time
Negative terminal input signal of the rectifying tube drain voltage as comparator CMP is walked, the drain voltage detected twice is compared, and works as LLC
When the body diode conducting of secondary synchronous rectifier, the logic output of comparator CMP is " 1 ", is at this time core by microcontroller
The control system control LLC secondary synchronous rectifier of the heart extends certain turn-on time in next cycle, while following
Period constantly judge logic output that it compares until logic exports as " 0 ", when comparator logic exports as " 0 ", simultaneously
Judge its logic output be in the period of " 0 " second drain voltage sampled whether within safe range to prevent
The problem of overregulating, after the drain voltage of second of sampling meets in safe range, then LLC pair side synchronous rectification at this time
The turn-off time of pipe is defaulted as the time most preferably turned off, and the efficiency of entire LLC topological circuit at this time has reached highest efficiency.
Such as Fig. 3, the control method of control system of the present invention is before turning off to the synchronous rectifier on full-bridge LLC pair side and to close
Drain terminal voltage after disconnected is sampled respectively, double sampling result is carried out logical comparison by comparator, according to logic ratio
It is adjusted compared with result by turn-off time of the microcontroller to full-bridge LLC secondary synchronous rectifier and utilizes the interruption of microcontroller
Cooperation realizes the accurate sampling of LLC secondary synchronous rectifier shutdown front and back source-drain voltage, by comparing in real time by microcontroller
The time order that the needs provided adjust, realizes that full-bridge LLC secondary synchronous rectifier is turned off in the best time, improves full-bridge LLC
The whole efficiency of circuit.The following steps are included:
1) first in one cycle, full-bridge LLC secondary synchronous rectifier M6 shutdown before for the first time detection synchronize it is whole
The voltage VSR (1) of flow tube M6 drain electrode, while being stored to using microcontroller in the control system of core and to export to comparing
The anode of device CMP, the voltage of second of detection synchronous rectifier M6 drain electrode after full-bridge LLC secondary synchronous rectifier M6 shutdown
VSR (2) is simultaneously stored.
2) by first time detection full-bridge LLC secondary synchronous rectifier M6 drain electrode voltage VSR (1) with detect for the second time
The voltage VSR (2) of synchronous rectifier M6 is compared, and is subtracted with the drain voltage VSR (1) of the synchronous rectifier M6 of first time detection
The synchronous rectifier drain voltage VSR (2) detected for the second time is gone to be transported to as the output result of comparator CMP with microcontroller
Device is the digital logic unit of the control system of core, wherein output comparison result is positive, that is, the body of synchronous rectifier M6
Diode current flow is then denoted as logical one, is otherwise denoted as logical zero.
3) when according to the Digital Logic result of CMP output is compared to the shutdown of full-bridge LLC secondary synchronous rectifier M5 and M6
Between be adjusted.It wherein, is the control system of core under using microcontroller if the logical comparison result of output is " 1 "
A cycle delay a period of time turns off the synchronous rectifier M6 of full-bridge LLC, if the logical comparison result of output is " 0 ",
Show that synchronous rectifier M6 turn-off criterion is substantially met at this time.
4) it needs to carry out next step judgement when logic output result is " 0 ", the full-bridge LLC pair side for judging at this time synchronizes whole
Whether flow tube M6 drain voltage meets in certain safe range the (synchronous rectification of second of detection i.e. in guarantee a cycle
Pipe M6 drain terminal voltage VSR (2) storage value is negative, if synchronous rectifier M6 drain terminal voltage VSR (2) storage value of second of detection is
Regular representation be not within safe range) with prevent M6 turn off time too late, result in and the phenomenon that electric current reverse irrigation occur.
5) meet comparator CMP logic output be " 0 ", while meet detected for the second time within this period synchronize it is whole
Flow tube M6 drain voltage (M6 drain terminal voltage VSR (2) is negative) within safe range, then keep the arteries and veins of this synchronous rectifier M6
The wide period is constant.
6) above-mentioned steps are recycled in next cycle, so that synchronous rectifier is turned off in optimum time point.
For the accurate sampling for realizing LLC secondary synchronous rectifier shutdown front and back source-drain voltage, microcontroller is core
Time of control system interrupt process the following steps are included:
1) in one cycle, the t0 moment using controller be core control system internal clocking failing edge as in
Break mouth.
2) in the failing edge of t1 instance sample full-bridge LLC secondary synchronous rectifier M6 drain voltage, at this moment with micro-control
Device processed is that the clock inside the control system of core generates interruption.
3) the t3 moment interrupts before full-bridge LLC secondary synchronous rectifier M6 is turned off, while sampling full-bridge LLC for the first time
Secondary synchronous rectifier M6 drain voltage.
4) the t4 moment interrupts after full-bridge LLC secondary synchronous rectifier M6 shutdown, while second of this sampling is complete
Bridge LLC secondary synchronous rectifier M6 drain voltage.
As shown in figure 4, be LLC circuit secondary synchronous rectifier drain terminal voltage detecting waveform diagram, detection waveform be
Switching frequency is less than the waveform in the case of resonance frequency, it can be seen from the figure that the detection synchronous rectifier shutdown in Fig. 4 (a)
The drain terminal voltage of front and back simultaneously carries out logic judgment, if at this moment having VSR (1) > VSR (2), and two voltages are respectively less than zero at this time,
Then logic judgment is " 1 " at this time, then M6 is delayed to turn off a period of time.As shown in Fig. 4 (b), if next week after adjustment
Still there is VSR (1) > VSR (2) in phase, and there are still two voltages less than zero, then logic judgment is still " 1 " at this time, then M6 is still
It is old to continue to be delayed to turn off a period of time.If VSR (1) < VSR (2), devices M6 may be just in its electric current at this time
Zero crossing shutdown, then need further to be judged, if VSR (1) is negative and VSR (2) is also negative, as shown in Fig. 4 (d), then
The turn-off time of next switch periods synchronous rectifier M6 remains unchanged.If VSR (2) is positive, as shown in Fig. 4 (c), then micro-control
Device processed can control next switch periods devices M6 driving signal, by next switch periods devices M6
Turn-off time shift to an earlier date a period of time.
Fig. 5 is the corresponding efficiency curve diagram under full load conditions, and wherein the curve graph of origin is that the efficiency of universal method is bent
Line chart, peak efficiency reaches 97.5%, and corresponding triangle curve figure is the corresponding efficiency curve diagram of the present invention, compared to
Its efficiency on the whole of the efficiency curve diagram of universal method is higher by 0.5% or so.