CN107424988B

CN107424988B - ESD protection method and ESD protection circuit

Info

Publication number: CN107424988B
Application number: CN201610908014.2A
Authority: CN
Inventors: M.什里瓦斯塔瓦; C.拉斯; H.戈斯纳
Original assignee: Intel Mobile Communications GmbH
Current assignee: Intel Deutschland GmbH
Priority date: 2012-03-26
Filing date: 2013-03-26
Publication date: 2021-02-02
Anticipated expiration: 2033-03-26
Also published as: CN103368158B; CN103368158A; DE102013103076B4; CN107424988A; DE102013103076A1; CN103367357A; DE102013103082A1; CN103367357B

Abstract

Some embodiments relate to electrostatic discharge (ESD) protection devices for protecting circuits from ESD events. The ESD protection current includes first and second trigger elements. Upon detection of an ESD pulse, the first trigger element provides a first trigger signal having a first pulse length. The second trigger element provides a second trigger signal having a second pulse length when the ESD pulse is detected. The second pulse length is different from the first pulse length. The main splitter splits the power of the ESD pulse away from the ESD susceptible circuit based on the first trigger signal. The current steering element selectively pumps the current induced by the ESD pulse into the main pumped substrate based on the second trigger signal.

Description

ESD protection method and ESD protection circuit

The present application is a divisional application of the following applications:

the invention name is as follows: for enhancing selective current pumping of low voltage ESD clamps using high voltage devices,

application date: the year 2013, the month 3 and the day 26,

application No.: 201310099133.4.

background

Electrostatic discharge (ESD) pulses are sudden and unintended voltage and/or current discharges that transfer energy from an external body, such as a human body, for example, to an electronic device. ESD pulses can damage electronic devices, for example by "extinguishing" the gate oxide of the transistor in the case of high voltages or by "melting" the active area of the device in the case of high currents, causing contact failures.

As will be understood in greater detail below, the present disclosure relates to improved ESD protection techniques.

Drawings

Fig. 1 shows an ESD protection device which suffers from some drawbacks.

Fig. 2 shows an exemplary embodiment of an ESD protection device comprising a current control element.

Fig. 3 shows an exemplary embodiment of an ESD protection device with a current control element implemented as a shunt.

Fig. 4 shows an exemplary embodiment of an ESD protection device with a current control element implemented as a current switching element.

Fig. 5A-5C illustrate an example embodiment of an ESD protection circuit including a current switching element as it protects against ESD pulses having a pulse length of about 150 nanoseconds.

Fig. 6A-6C illustrate an example embodiment of an ESD protection circuit including a shunt, as it protects against ESD pulses having a pulse length of about 150 nanoseconds.

Fig. 7 illustrates an example embodiment of an ESD protection circuit that includes an additional capacitor for facilitating substrate pumping.

Fig. 8 illustrates an example embodiment of an ESD protection device including a voltage adder.

FIG. 9 illustrates a method in flowchart format, in accordance with some embodiments.

Fig. 10 shows an exemplary embodiment of an ESD protection device comprising a single trigger element.

Detailed Description

The present invention will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale.

Fig. 1 shows a circuit 100 that uses less than ideal ESD protection techniques. The circuit 100 includes an ESD-susceptible circuit 102 and an ESD protection circuit 104, both of which are electrically coupled to first and

second circuit nodes

106A, 106B (e.g., a DC supply voltage pin and a ground pin, respectively, of an integrated circuit). The ESD protection circuit 104 includes first and second

electrical paths

108, 110 that extend in parallel between the first and

second circuit nodes

106A, 106B. The first electrical path 108 includes a trigger element 111 disposed thereon, and the second electrical path 110 includes a splitter 112. Substrate pump 114 is arranged to pump the substrate of splitter 112 to enhance its gain during an ESD event.

During operation, the trigger element 116 detects voltage and/or current spikes indicative of the ESD pulse 124 and thereby increases the voltage of the trigger signal at its output 118. This increased voltage places shunt 112 and substrate pump 114 into a conductive state. Substrate pump 114 thus diverts some of the current of ESD pulse 123 to the substrate of splitter 112 via path 120, which helps to increase the gain of splitter 112. Due to the high voltage trigger signal, the shunt 112 now represents a low impedance (relative to the ESD-susceptible circuit 102) and the power of the ESD pulse 124 flows through the shunt 112 and away from the ESD-susceptible circuit 102, as indicated by arrow 122.

While this technique is adequate in some respects, the ESD protection circuit 104 suffers from the following disadvantages: splitter 112 may not be able to adequately split large ESD pulses, especially when low voltage devices are used for

circuits

102 and 104. Thus, if a large ESD pulse is harmful, the rapid inflow of ESD current may "overwhelm" the shunt 122, such that some power from the ESD pulse may reach the ESD-susceptible circuit 102 and cause damage. Furthermore, if too much current is directed through the shunt 112 for each unit area, the shunt 112 itself may also be damaged.

Accordingly, aspects of the present disclosure relate to ESD protection techniques that still provide substrate pumping to increase the gain of the splitter while also allowing increased current splitting relative to conventional approaches. Thus, these techniques provide reliable protection against ESD pulses, thereby helping to achieve good manufacturing yield and reliable customer performance.

Fig. 2 shows an example ESD protection circuit 200. The ESD protection circuit 200 includes first, second, third and fourth

electrical paths

202, 204, 206, 208, respectively, that extend in parallel between the first and

second circuit nodes

106A, 106B. The first electrical path 202 includes a first trigger element 210, the second electrical path 204 includes a second trigger element 212, and the third electrical path 206 includes a primary shunt 214. The fourth electrical path 208 includes a current control element 216. During operation, the low impedance state of the main shunt 214 is triggered by the first trigger signal from the first trigger element 210. The current control element 216 is arranged to selectively act as a substrate pump for the main shunt 214 based on a second trigger signal from the second trigger element 212 and to selectively act as a secondary shunt in parallel with the main shunt 214 based on the second trigger signal. The first and second trigger signals typically have different pulse lengths and/or have offset edges.

In some embodiments, such as the example embodiment shown in fig. 3, the current control element (e.g., 216 in fig. 2) may be implemented as a shunt 302 having a control terminal 304. When no ESD pulse is present, the first and

second trigger elements

210, 212 are off, such that the main shunt 214 and the shunt 302 both represent a high impedance state between the first and

second circuit nodes

106A, 106B. Thus, in the absence of an ESD pulse, normal operating power flows to the circuit 102 via the first and

second circuit nodes

106A, 106B. However, when the ESD pulse 124 is compromised, the first and

second trigger elements

210, 212 activate the first and second trigger signals, which in turn simultaneously activate the main shunt 214 and the shunt 302, respectively. In this state, the shunt 302 diverts ESD current flowing into the terminal 302A out of 302B to pump the substrate of the main shunt 214 (thereby increasing the gain of the main shunt 214), and at the same time diverts current flowing into the terminal 302A out of 302C to act as a secondary shunt.

In other embodiments, such as the one shown in fig. 4, the current control element (e.g., 216 in fig. 2) may be implemented as a current switch 402 that either acts as a substrate pump for the primary shunt 214 or acts as a secondary shunt at any given time, but not both. When no ESD pulse is present, the first and

second trigger elements

210, 212 are also off, such that the main shunt 214 represents a high impedance state and the current switch 402 is set to position 402B. Due to the high impedance when no ESD pulse is present, normal operating power flows to the circuit 102 via the first and

second circuit nodes

106A, 106B. However, the first trigger element 210 activates the main shunt 214 when the ESD pulse 124 is compromised. For a portion of this hazardous ESD pulse 124, the second trigger element 212 remains off, causing the current switch 402 to be set to position 402B, and thus pumping the current caused by the ESD pulse 124 into the substrate of the main shunt 214. At some later time in the ESD pulse, the second trigger element 212 is activated and the current switch 402 changes its state to divert current to 402C, thereby acting as a secondary shunt working in parallel with the primary shunt 214 and stopping the substrate pumping of the primary shunt 214.

Fig. 5A-5C illustrate examples of ESD devices 500 with current switches 502 protected from ESD pulses having a duration of approximately 150 ns. As shown in fig. 5A, in the absence of the ESD pulse 124, the first and

second trigger elements

210, 212 remain off and provide a low voltage at the

respective outputs

220, 222, respectively. These low voltages are less than the threshold voltage V of the drain extended MOS (DeMOS)

transistors

504, 506, 508_THAnd these low voltages cause the

DeMOS transistors

504, 506, 508 to be in a non-conductive, high impedance state. Thus, as long as no ESD pulse is present, the first-fourth paths 202-208 represent a high impedance state and the normal operating voltages at the first and

second circuit nodes

106A, 106B flow substantially unimpeded to the ESD-susceptible circuit 102. For example, if the first circuit node 106A carries a 5 volt DC supply voltage and the second current node 106B carries a 0 volt DC supply voltage, the ESD-susceptible circuit 102 would see a bias voltage of 5V without the ESD pulse 124.

Fig. 5B shows the ESD protection circuit 500 shortly after the ESD pulse 124 has been detected by the first and

second trigger elements

210, 212. In response to detection of the ESD pulse 124, the first trigger element 210 asserts a first trigger signal on a first output 220. When asserted, the first trigger signal has a voltage level higher than the respective threshold voltages of the main pump 504 (e.g., DeNMOS) and the main splitter 508 (e.g., DeNMOS). Thus, the first trigger signal places the main pump 504 and the main shunt 508 in a conductive state, which tends to shunt ESD current as shown by current path 512. The second trigger signal remains deasserted for a first time interval when the first trigger signal is asserted. Because of this, the secondary pump 510 is conductive and current due to the ESD pulse is pumped to the substrate of the primary shunt 508 to increase its gain.

In fig. 5C, at some later time during the ESD pulse 124, the second trigger element 212 is activated such that the second trigger signal at 222 has a voltage level higher than the threshold voltage of the secondary shunt 506. Thus, the second trigger signal places the secondary shunt 506 in a conducting state and simultaneously turns off the secondary pump 510. Since the secondary shunt 506 is now conductive, some ESD hazard current is also shunted through the secondary shunt 506, as shown by current path 514. In this manner, substrate pumping occurs during a first portion of the ESD pulse (e.g., the first approximately 20ns in this example) when the second trigger signal is asserted (fig. 5B), and additional current shunting occurs during a second portion of the ESD pulse (fig. 5C).

Fig. 6A-6C illustrate an ESD protection circuit 600 in which a shunt 602 (e.g., shunt 216 in fig. 2) includes a secondary shunt 604 (e.g., DeNMOS) and a secondary pump 606 (e.g., DePMOS) operatively coupled as shown. In fig. 6A-6C, an inverter 608 is also included in the shunt 602. However, it will be understood that in other embodiments, a DePMOS transistor (or other switching element, such as a MOSFET, BJT, etc.) may be substituted for the illustrated DePMOS transistor in secondary splitter 604, a DePMOS transistor (or other switching element, such as a MOSFET, BJT, etc.) may be substituted for the illustrated DePMOS transistor in secondary pump 606, and inverter 608 need not be present in all embodiments. The same is true for the previous embodiments illustrated in fig. 5A-5C. An example of the harmfulness of the ESD pulse 124 is now described below with reference to fig. 6A-6C.

Fig. 6A shows ESD protection circuit 600 prior to the start of an ESD pulse. Since no ESD pulse is present, the first and

second trigger elements

210, 212 remain offOff and correspondingly provide a low voltage at their

respective outputs

220, 222. These low voltages are less than the threshold voltage V of the main shunt 610 and the main pump 612_THAnd these voltages place the main shunt 610 and the main pump 612, respectively, in a non-conductive high impedance state. Thus, as long as no ESD pulse is present, the main shunt 610 maintains a high impedance ("off") state and normal operating voltages on the first and

second circuit nodes

106A, 106B flow substantially unimpeded to the ESD-susceptible circuit 102. For example, if the first circuit node 106A carries a 5 volt DC supply voltage and the second current node 106B carries a 0 volt DC supply voltage, the ESD-susceptible circuit 102 would see a bias voltage of 5V without an ESD pulse.

Fig. 6B shows the ESD protection circuit 600 shortly after the ESD pulse 124 has been detected by the first and

second trigger elements

210, 212. In response to detection of the ESD pulse 124, the first and

second trigger elements

210, 212 assert first and second trigger signals on first and

second outputs

220, 222, respectively. When asserted, the first trigger signal at the output 220 has a voltage level higher than the respective threshold voltages of the main pump 612 (e.g., DeNMOS) and the main splitter 610 (e.g., DeNMOS). Thus, the first trigger signal places the main pump 612 and the main shunt 610 in a conductive state, which tends to shunt ESD current as shown by the current path 614.

Similarly, the second trigger signal at output 222 has a voltage level higher than the threshold voltage of secondary shunt 604, inverter 608, and secondary pump 606 when asserted by second trigger element 212. Thus, the second trigger signal places the secondary shunt 604 and the secondary pump 606 in a conductive state. In fig. 6B, some of the harmful ESD current flows into the substrate of the main splitter 610 through the primary pump 612 and the secondary pump 606, thereby increasing the gain of the main splitter 610 and facilitating dissipation of the ESD current along the current path 614. Furthermore, when the secondary shunt 604 is also conductive, some of the ESD hazard current is also shunted through the secondary shunt 604 as shown by current path 616. In this manner, during a first portion of the ESD pulse (e.g., the first approximately 20ns in this example) when the second trigger signal is asserted, current dissipation is enabled to increase relative to conventional approaches. For example, this embodiment may provide about 50% more current handling than the conventional substrate pumping proposal in some implementations, assuming equal sized transistors.

The second trigger signal at output 222 typically has a different pulse length than the first trigger signal at output 220. For example, the pulse length of the second trigger signal is generally shorter than the first pulse signal length. In the example of fig. 6C (which represents 20-100ns as measured from the beginning of the ESD pulse), the second trigger signal at output 222 has been deasserted because its voltage level has now dropped below the threshold voltage of secondary shunt 604 and secondary pump 606. Thus, for this second period in the ESD pulse, the secondary shunt 604 and the secondary pump 606 are now "off. Thus, current is no longer injected into the substrate of the primary splitter 610 by the secondary pump 606, and the circuit is no longer split by the secondary splitter 604 as previously illustrated in fig. 6B. However, ESD current is conducted through the main shunt element 610 during this time period.

Fig. 7 shows an exemplary illustration of an ESD protection circuit 700 in which a capacitor 702 has been added to help pump the substrate of the main shunt 214. For example, capacitor 702 may be a discrete off-chip capacitor or an on-chip capacitor formed adjacent to a metal or polyethylene layer of the IC. The capacitor 702 gets charged during the first 20ns and will provide the pumping current even after this trigger element times out after 20 ns. In other words, it contributes to the charge for pumping over a period of time and supplies the charge to the main shunt.

Fig. 8 illustrates an example embodiment of an ESD protection circuit 800 that utilizes a voltage adder 802. In some embodiments, the voltage adder 802 may be implemented as an operational amplifier that adds two voltages at the

voltage adder inputs

808, 810 and that is coupled to the first and

second circuit nodes

106A, 106B. The voltage adder 802 limits the increase in potential due to the impedance of the substrate on both the substrate of the main shunt 214 and the source of the main pump 806. If left unresolved, this undesirable potential coalescence may be for the main pumpThe pump transistor 806 causes bias problems (e.g., too little bias). To limit this potential increase, during operation, when a voltage or current spike indicative of the ESD pulse 124 is detected, the trigger element 210 asserts a trigger signal at 804. In order to maintain a substantially constant gate-source voltage V for the main shunt 806_GSThe voltage adder 802 adds the voltages on the

voltage adder inputs

808, 810 to increase the adder output voltage provided to the gate of the main shunt 806. In this manner, the output voltage of the voltage summer 802 acts as an enhanced trigger signal having a dynamic voltage level that maintains a substantially constant gate-source voltage for the pump transistor 806 throughout the period of the detrimental ESD pulse. In other words, the voltage adder 802 compensates for any loss of current in the main shunt 806, as is the case for the increased source potential.

Fig. 9 illustrates an example method 900 of ESD protection in accordance with an aspect of the present disclosure.

At step 902, the method 900 begins with the first trigger element selectively activating a first trigger signal based on detection of an ESD pulse. For example, if an ESD pulse is detected, the voltage of the first trigger signal is increased for approximately 100ns to correspond to activation of the first trigger signal. The time at which the first trigger signal is asserted may depend on the size of the ESD pulse and may vary widely according to design constraints. The first trigger signal is in no way limited to a pulse length of 100ns, but may be significantly longer or shorter depending on the implementation.

At step 904, the method 900 continues with the second trigger element to selectively activate the second trigger signal based on the detection of the ESD pulse. For example, if an ESD pulse is detected, the voltage of the second trigger signal may be increased for approximately 20ns to correspond to activation of the second trigger signal. The time at which the second trigger signal is asserted may depend on the size of the ESD pulse and may vary widely according to design constraints. The second trigger signal is in no way limited to a pulse length of 20ns, but may be significantly longer or shorter depending on the implementation. The pulse length of the second trigger signal is typically different from the first pulse length.

At step 906, the main splitter splits power of the ESD signal away from the ESD-susceptible circuit based on the first trigger signal.

At step 908, the main pump selectively pumps the ESD pulse induced current into the substrate of the main shunt based on the second trigger signal.

At step 910, the secondary splitter diverts power caused by the ESD pulse away from the ESD-susceptible circuit based on the second trigger signal.

While several embodiments have been described in connection with the accompanying drawings, it will be understood that nothing in this specification or in these drawings should limit the scope of this disclosure in any way. Other embodiments are also contemplated as falling within the scope of the present disclosure. For example, although the illustrated circuits may be implemented as integrated circuits in some embodiments, they may also be implemented as a combination of discrete components in other embodiments. Furthermore, although some embodiments may describe elements coupled between first and second circuit nodes (e.g., 106A, 106B in fig. 1-5), second circuit node 106B may, in some instances, comprise a plurality of physically separate nodes that are legally equivalent to a single second circuit node. For example, in the embodiment of fig. 2, the second circuit node may correspond to a single IC ground pin that is commonly coupled to the first trigger element, the second trigger element, the shunt element, and the current control element. However, in other embodiments, the first trigger element may be coupled to a first IC ground pin, the second trigger element may be coupled to a second IC ground pin that is physically separate from the first IC ground pin, the shunt element may be coupled to a third IC ground pin, and the shunt may be coupled to a fourth IC ground pin.

Moreover, not all illustrated elements may be required for all implementations. Fig. 10 shows an example embodiment in which only one trigger element is applied instead of applying the first and second trigger elements. In this example, the substrate pump includes a DeNMOS 1002 and a DePMOS device 1004, which are operatively coupled as shown. The selective current pumping is based only on the first trigger signal.

Accordingly, it will be appreciated that some embodiments relate to an electrostatic discharge (ESD) protection device to protect circuitry susceptible to ESD from ESD pulses. The ESD protection device comprises a first trigger element for providing a first trigger signal having a first pulse length upon detection of an ESD pulse. The ESD protection circuit further comprises a second trigger element for providing a second trigger signal having a second pulse length different from the first pulse length upon detection of an ESD pulse. The shunt element is adapted to shunt power of the ESD pulse away from a circuit susceptible to ESD based on the first trigger signal. The shunt is adapted to selectively pump current caused by the ESD pulse into a substrate of the shunt based on a second trigger.

Other embodiments relate to an ESD protection device for protecting a circuit susceptible to ESD events from ESD events, electrically connected to first and second circuit nodes. The ESD protection device includes a first electrical path extending between first and second circuit nodes and including a first trigger element disposed thereon. A second electrical path including a second trigger element extends between the first and second circuit nodes and is parallel to the first electrical path. A third electrical path also extends between the first and second circuit nodes and is parallel to the first and second electrical paths. The third electrical path includes a shunt for selectively shunting energy of the ESD event from the first circuit node to the second circuit node based on the first trigger signal from the first trigger element. A fourth electrical path extends between the first and second circuit nodes and is parallel to the first and second electrical paths. The fourth electrical path includes a shunt to selectively shunt current from the first circuit node to the second circuit node based on a second trigger signal from the second trigger element.

Further embodiments relate to an ESD protection circuit comprising a trigger element configured to assert a trigger signal when an ESD pulse is detected. The shunt element is arranged to shunt the power of the harmful ESD pulse based on the trigger signal. The voltage adder provides an enhanced trigger signal based on the trigger signal. The pump transistor provides current to the substrate of the shunt based on an enhanced trigger signal, wherein the enhanced trigger signal has a dynamic voltage level to maintain a gate-source voltage applied to the pump transistor substantially constant throughout the ESD pulse.

Another embodiment relates to a method for ESD protection. In the method, a first trigger signal is selectively asserted for a first pulse length based on whether an ESD pulse is detected. A second trigger signal is selectively asserted for a second pulse length based on whether the ESD pulse is detected. The second pulse length is different from the first pulse length. The power of the ESD pulse is shunted away from the ESD-susceptible circuit via the main shunt based on the first trigger signal. Selectively pumping current caused by the ESD pulse into a substrate of the primary pump based on a second trigger signal.

In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a "means") used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "includes," including, "" has, "" having, "" with, "or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising.

Claims

1. An ESD protection circuit, comprising:

a first trigger element configured to provide a first trigger signal when an ESD pulse is detected;

a second trigger element configured to provide a second trigger signal when the ESD pulse is detected;

a main shunt element configured to shunt power of the ESD pulse based on the first trigger signal; and

A current control element configured to selectively act as a substrate pump of the main shunt element to pump current caused by the ESD pulse to the main shunt element based on the second trigger signal In the substrate and selectively based on the second trigger signal as a secondary shunt element in parallel with the primary shunt element.

2. The ESD protection circuit of claim 1, wherein the current control element comprises a current switch configured to switch between a first position and a second position, wherein the current switch is set to the first position position to selectively pump current caused by the ESD pulse into the substrate of the main shunt element when the second trigger signal is de-asserted, and is set to a second position to selectively pump current caused by the ESD pulse into the substrate of the main shunt element when the second trigger signal is de-asserted and selectively shunts current when the second trigger signal is asserted, wherein the current switch is set to the first position when no ESD pulse is present.

3. The ESD protection circuit of claim 1, wherein a pulse length of the first trigger signal is different from a pulse length of the second trigger signal.

4. The ESD protection circuit of claim 1, wherein a pulse length of the first trigger signal is the same as a pulse length of the second trigger signal.

5. The ESD protection circuit of claim 1, further comprising: a main pump in series with the current control element.

6. The ESD protection circuit of claim 5, wherein the main pump comprises a drain extended MOS (DeMOS) transistor having a gate coupled to the output of the first trigger element pole.

7. The ESD protection circuit of claim 1, wherein the current control element comprises a shunt configured to selectively shunt current induced by the ESD pulse based on the second trigger signal.

8. The ESD protection circuit of claim 7, wherein the shunt comprises:

a sub-pump element having a control terminal coupled to an output of the second trigger element, wherein the sub-pump element is configured to selectively divert the current induced by the ESD pulse based on the second trigger signal pumped into the substrate of the main shunt element.

9. The ESD protection circuit of claim 8, wherein the shunt further comprises:

a secondary shunt element having a control terminal coupled to an output of the second trigger element, wherein the secondary shunt element is configured to selectively shunt through the second trigger signal based on the second trigger signal Current due to ESD pulses.

10. The ESD protection circuit of claim 9, wherein the sub-pumping element and the sub-shunt element each comprise a drain extended MOS transistor.

11. The ESD protection circuit of claim 7, wherein the shunt and the main shunt element are configured to simultaneously shunt current caused by the ESD pulse based on the first trigger signal and the second trigger signal.

12. The ESD protection circuit of claim 1, wherein the main shunt element comprises a drain extended transistor.

13. A method for ESD protection performed by an ESD protection circuit, comprising:

When an ESD pulse is detected, assert a first trigger signal of a first pulse length;

upon detecting the ESD pulse, asserting a second trigger signal of a second pulse length, the second pulse length being different from the first pulse length;

splitting power of the ESD pulse away from circuits susceptible to ESD by a main splitter of the ESD protection circuit based on a first trigger signal; and

selectively pumped by a current control element of the ESD protection circuit based on the second trigger signal as a substrate of the main splitter to pump current caused by the ESD pulse to the main splitter in the substrate of the splitter and selectively acted by the current control element as a secondary splitter in parallel with the primary splitter based on the second trigger signal.

14. The method of claim 13, wherein the main splitter comprises a drain extended MOS transistor.

15. An apparatus for ESD protection performed by an ESD protection circuit, comprising:

means for asserting a first trigger signal of a first pulse length upon detection of an ESD pulse;

means for asserting a second trigger signal of a second pulse length upon detection of the ESD pulse, the second pulse length being different from the first pulse length;

means for splitting power of the ESD pulse away from ESD susceptible circuits by a main splitter of the ESD protection circuit based on the first trigger signal; and

for pumping by the current control element of the ESD protection circuit selectively as a substrate of the main shunt based on the second trigger signal to pump the current caused by the ESD pulse to the A device in the substrate of the primary shunt and selectively acted upon by the current control element as a secondary shunt in parallel with the primary shunt based on the second trigger signal.

16. The apparatus of claim 15, further comprising:

Means for selectively splitting power of the ESD pulse away from circuits susceptible to ESD by the secondary splitter based on the second trigger signal.

17. The apparatus of claim 16, wherein the power of the ESD pulse is shunted away from circuits susceptible to ESD by the primary splitter and the secondary splitter simultaneously.

18. The apparatus of claim 15, wherein the main splitter comprises a drain extended MOS transistor.