CN107424923A - A kind of method from limitation accurate etching silicon - Google Patents
A kind of method from limitation accurate etching silicon Download PDFInfo
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- CN107424923A CN107424923A CN201710546763.XA CN201710546763A CN107424923A CN 107424923 A CN107424923 A CN 107424923A CN 201710546763 A CN201710546763 A CN 201710546763A CN 107424923 A CN107424923 A CN 107424923A
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000005530 etching Methods 0.000 title claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 42
- 239000010703 silicon Substances 0.000 title claims abstract description 41
- 238000006243 chemical reaction Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000008569 process Effects 0.000 claims abstract description 13
- 239000007789 gas Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 11
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 11
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 11
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 11
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 9
- 238000003486 chemical etching Methods 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 58
- 230000004888 barrier function Effects 0.000 claims description 10
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000000284 extract Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 28
- 150000002500 ions Chemical class 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- 239000002070 nanowire Substances 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910008045 Si-Si Inorganic materials 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 3
- 229910006411 Si—Si Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910052593 corundum Inorganic materials 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- 229910018540 Si C Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000002242 deionisation method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- XLYOFNOQVPJJNP-ZSJDYOACSA-N heavy water Substances [2H]O[2H] XLYOFNOQVPJJNP-ZSJDYOACSA-N 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007736 thin film deposition technique Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32105—Oxidation of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention discloses a kind of method from limitation accurate etching silicon, comprises the following steps：Si surfaces are passed through oxygen from oxide layer forming step is limited to vacuum reaction intracavitary, and oxidation processes are carried out to the Si layer surfaces to be etched formed on a semiconductor substrate, are formed from limitation SiO2Layer, then the remnant oxygen of vacuum reaction intracavitary is extracted out；Selective chemical etching is passed through HF gases, to limitation SiO certainly from limitation oxide layer step2Layer carries out selective etch, then extracts the remaining HF of vacuum reaction intracavitary and generation gas out；Above steps is repeated, until reaching predetermined Si etch amounts.The present invention has self limitation capability of atomic level, need not be so high as prior art to the requirement of equipment control ability itself, advantageously reduces the popularization of production cost and technology.In addition, the method from limitation accurate etching silicon of the present invention is not related to ion orientation etching process, there is the characteristics of obvious isotropism, it is possible to achieve Three-dimension process.
Description
Technical field
The present invention relates to integrated circuit fields, and in particular to a kind of from the method for limiting accurate etching silicon.
Background technology
With the continuous development of integrated circuit technique, the characteristic size of transistor constantly reduces, currently from 5nm to more
Small technology strides forward, and raceway groove is also by planar development to fin-shaped (FinFet) again to nano wire (nanowire), so being manufactured to it
Technology proposes higher requirement, especially Three-dimension process ability.
Atomic layer lithographic technique (Atomic layer etching) is an emerging lithographic technique, there is instrument factory at present
Business and research institution release a kind of atomic layer lithographic technique for etching silicon, and general principle and process are as follows：
(1) Cl is used2(modification) is modified to silicon face, Si-Si dangling bonds are modified to Si-C keys, table
It is shown as, Cl2(gas)+Si (Gu) → SiClx (Gu).Because the material of formation is at normal temperatures solid, so the step has self
Limited characteristic, only influence about atomic layer；
(2) unnecessary Cl is removed2
(3) the Ar ion remaval solid-state SiClx of appropriate energy are used and Si can not be caused to damage.Si-Si bond can be
3.4eV, Si-Cl bond energy are 4.2eV, and the bond energy between Si and lower floor Si can be reduced to 2.3eV by Cl introducing.Therefore, Ar from
The energy threshold of son needs that accurately Si-C materials can be being tapped without tapping Si-Si, you can etches away to self limitation
SiClx；
Then repeat above procedure and complete etching.
There is mechanism to report the technology crossing in etching available for fin-shaped grid etching at present, can be with more compared with conventional etch
Small quarter amount (25%) of crossing reaches the purpose for removing silicon residual.
Above-mentioned technology proposes high requirement to ion energy, only when ion energy could suitably be realized, if from
Sub- energy is too low, can not realize and remove modified layer purpose, if ion energy is too high, can cause Si surface damages or etching
Fall silicon and do not reach the purpose (self limited etching) of self limitation etching of atomic layer, therefore also equipment is controlled and proposed
High requirement.
In addition, this method because going deionization to have directionality, can not realize horizontal processing, Three-dimension process will be needed to lead in future
Domain such as nano wire manufacture field will be limited to.
The content of the invention
In order to solve the above problems, the present invention discloses a kind of method from limitation accurate etching silicon, comprises the following steps：Si
Surface is passed through oxygen from oxide layer forming step is limited to vacuum reaction intracavitary, to forming on a semiconductor substrate to be etched
Si layer surfaces carry out oxidation processes, are formed from limitation SiO2Layer, then the remnant oxygen of vacuum reaction intracavitary is evacuated；Selectivity
Chemical etching is passed through HF gases from oxide layer step is limited, to limitation SiO certainly2Layer carries out selective etch, then that vacuum is anti-
The remaining HF and generation gas for answering intracavitary are extracted out, above steps are repeated, until reaching predetermined Si etch amounts.
In the method for the accurate etching silicon of limitation certainly of the present invention, it is preferably, is formed on the Si surfaces from oxide layer is limited
Underlayer temperature is controlled in step.
It is preferably that the underlayer temperature is 0 DEG C~200 DEG C in the method for the accurate etching silicon of limitation certainly of the present invention.
In the method for the accurate etching silicon of limitation certainly of the present invention, it is preferably, the SiO2Thickness is 1~5 atomic layer.
In the method for the accurate etching silicon of limitation certainly of the present invention, it is preferably, the oxidation treatment time is 1s~10s.
The present invention from the method for limitation accurate etching silicon, be preferably be passed through time of the HF gases for 1s~
10s。
In the method for the accurate etching silicon of limitation certainly of the present invention, it is preferably to form the limitation SiO certainly2Before layer, formed
Al2O3As mask layer.
It is preferably that the Semiconductor substrate is on Si or insulator in the method for the accurate etching silicon of limitation certainly of the present invention
Si。
The present invention from limitation accurate etching silicon method in, be preferably, the Semiconductor substrate with it is described to be etched
Si interlayers form barrier layer.
In the method for the accurate etching silicon of limitation certainly of the present invention, it is preferably, the barrier layer is HfO2。
The method from limitation accurate etching silicon of the present invention has self limitation capability of atomic level, and equipment is controlled in itself
Capability Requirement processed need not be so high as prior art, advantageously reduces the popularization of production cost and technology.In addition, this
The method from limitation accurate etching silicon of invention is not related to ion orientation etching process, has the characteristics of obvious isotropism,
Three-dimensional (laterally and longitudinally processing) processing can be realized.
Brief description of the drawings
Fig. 1 is the flow chart of the method from limitation accurate etching silicon of the present invention.
Fig. 2 is sample structure schematic diagram to be etched.
Fig. 3 is to form the sample structure schematic diagram from after limitation oxide layer.
Fig. 4 is sample structure schematic diagram of the selective chemical etching from after limiting oxide layer.
Fig. 5 is the sample structure schematic diagram for reaching predetermined etch amount.
Fig. 6 is the structural representation for removing the nano wire formed after mask layer.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it will be appreciated that described herein
Specific embodiment only to explain the present invention, is not intended to limit the present invention.Described embodiment is only the present invention one
Divide embodiment, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making
The all other embodiment obtained under the premise of creative work, belongs to the scope of protection of the invention.
It describe hereinafter many specific details of the present invention, such as the structure of device, material, size, processing work
Skill and technology, to be more clearly understood that the present invention.But just as the skilled person will understand, it can not press
The present invention is realized according to these specific details.Unless hereinafter particularly point out, the various pieces in semiconductor devices can be with
It is made up of material well known to those skilled in the art, or the material with similar functions of exploitation in the future can be used.
Fig. 1 is the flow chart of the method from limitation accurate etching silicon of the present invention.As shown in figure 1, accurate etching is limited certainly
The method of silicon comprises the following steps：On Si surfaces from limiting oxide layer forming step S1, oxygen is passed through to vacuum reaction intracavitary,
Oxidation processes are carried out to the Si layer surfaces to be etched formed on a semiconductor substrate, formed from limitation SiO2Layer, then by vacuum
Remnant oxygen in reaction chamber is extracted out.It is well known that Si-O keys are easily created, and its thickness easily controls.Si is normal
Warm lower and O2It is easily formed SiO2And with self good limited characteristic, thickness is only an extremely several atomic layers, generally
In 1~5 atomic layer or so.Technique involved by this step requires relatively low to equipment and process conditions, but can be well
Realize self limited characteristic.
In selective chemical etching from limitation oxide layer step S2, HF gases are passed through, to limitation SiO certainly2Layer is selected
Selecting property etches, then by the remaining HF of vacuum reaction intracavitary and generation evacuating air.Gaseous hydrogen fluoride can etch SiO2And
And do not reacted with Si.Specific reaction represents as follows
SiO2+ 4HF (gaseous state)=SiF4(gaseous state)+2H2O (gaseous state),
So this step also has self good limited characteristic.
By above-mentioned Si surfaces from oxide layer forming step S1 and selective chemical etching is limited from limitation oxide layer step
S2, it is possible to achieve the Si etchings of several atomic layers, above steps is repeated, until reaching predetermined Si etch amounts.
The method from limitation accurate etching silicon of the present invention has self limitation capability of atomic level, and equipment is controlled in itself
Capability Requirement processed need not be so high as prior art, advantageously reduces the popularization of production cost and technology.In addition, this
The method from limitation accurate etching silicon of invention is not related to ion orientation etching process, has the characteristics of obvious isotropism,
Three-dimensional (laterally and longitudinally processing) processing can be realized.
In order to which the present invention is expanded on further, silicon is manufactured below for using the method from limitation accurate etching silicon of the present invention
One specific embodiment of nano wire illustrates.In the present embodiment, sample to be etched is prepared first.On Si substrates 100
Barrier layer 101 is formed, Si layers 102 are formed on barrier layer 101, and mask layer 103, resulting structures are formed on Si layers 102
As shown in Figure 2.Wherein, barrier layer 101 is HfO2, thickness is 1~10nm.The thickness of Si layers 102 is 50~100nm.Mask layer
103 be Al2O3, thickness is 1~10nm.Above-mentioned barrier layer, Si layers and mask layer can use electron beam evaporation, chemical gaseous phase
The conventional thin-film deposition method such as deposition, physical vapour deposition (PVD), ald, sputtering is formed.Then, revolved on said structure
Resist coating, using the line or post that photoresist is formed to 45nm~90nm including exposed and developed photoetching process, by molten
Dissolve or be ashed in agent and remove photoresist.
Next, sample to be etched is performed etching using the method from limitation accurate etching silicon of the present invention.
First, underlayer temperature is controlled at 0~200 DEG C in vacuum reaction intracavitary, is passed through oxygen and carries out 1~10s of thermal response,
Form thickness about 0.3nm SiO2Layer 104, resulting structures are as shown in Figure 3.Then, from vacuum reaction chamber pumping, evacuate in cavity
Remaining O2。
Then, HF gases are passed through, the time limits SiO certainly between 1~10s, to being formed2Sample after layer 104 is carved
Erosion, by the SiO2Selective corrosion is fallen, and resulting structures are as shown in Figure 4.Because Hf and Al fluoride has very high boiling
Point, so under the self-passivation of its fluoride, HF will not etching mask layer and barrier layer.Then evacuate remaining HF and life in cavity
Into gas.
Above step is repeated and according to the etch amount of single cycle, by the wide control of the silicon column finally left (line) in about 3nm
~10nm, resulting structures are as shown in Figure 5.
Finally, using dilution HCl can selective removal fall Al2O3Mask, obtain the silicon column (line) of nanoscale, institute
It is as shown in Figure 6 to obtain structure.
Specific one is these are only, but the present invention is not limited to this.For example, Semiconductor substrate can be various forms
Suitable substrate, such as body Semiconductor substrate such as Si, Ge etc. and compound semiconductor substrate such as SiGe, GaAs, GaSb, AlAs,
InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb etc., semiconductor-on-insulator substrate (SOI) etc..Mask layer, barrier layer
Can also be that other will not be by HF materials corroded etc..
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, the change or replacement that can readily occur in, all should
It is included within the scope of the present invention.
Claims (10)
- It is 1. a kind of from the method for limiting accurate etching silicon, it is characterised in thatComprise the following steps：Si surfaces are passed through oxygen from oxide layer forming step is limited to vacuum reaction intracavitary, to being formed on a semiconductor substrate Si layer surfaces to be etched carry out oxidation processes, are formed from limitation SiO2Layer, then the remnant oxygen of vacuum reaction intracavitary is extracted out；Selective chemical etching is passed through HF gases, to limitation SiO certainly from limitation oxide layer step2Layer carries out selective etch, so The remaining HF of vacuum reaction intracavitary and generation gas are extracted out afterwards,Above steps is repeated, until reaching predetermined Si etch amounts.
- It is 2. according to claim 1 from the method for limiting accurate etching silicon, it is characterised in thatUnderlayer temperature is controlled from limiting oxide layer forming step on the Si surfaces.
- It is 3. according to claim 2 from the method for limiting accurate etching silicon, it is characterised in thatThe underlayer temperature is 0 DEG C~200 DEG C.
- It is 4. according to claim 1 from the method for limiting accurate etching silicon, it is characterised in thatCertainly the limitation SiO2Thickness degree is 1~5 atomic layer.
- It is 5. according to claim 1 from the method for limiting accurate etching silicon, it is characterised in thatThe oxidation treatment time is 1s~10s.
- It is 6. according to claim 1 from the method for limiting accurate etching silicon, it is characterised in thatThe time for being passed through the HF gases is 1s~10s.
- It is 7. according to claim 1 from the method for limiting accurate etching silicon, it is characterised in thatIt is described from limitation SiO being formed2Before layer, Al is formed2O3As mask layer.
- It is 8. according to claim 1 from the method for limiting accurate etching silicon, it is characterised in thatThe Semiconductor substrate is Si on Si or insulator.
- It is 9. according to claim 8 from the method for limiting accurate etching silicon, it is characterised in thatBarrier layer is formed in the Semiconductor substrate and the Si interlayers to be etched.
- It is 10. according to claim 9 from the method for limiting accurate etching silicon, it is characterised in thatThe barrier layer is HfO2。
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110010460A (en) * | 2019-03-26 | 2019-07-12 | 贵阳学院 | A kind of low-dimensional material formation method |
| CN110867373A (en) * | 2018-08-28 | 2020-03-06 | 中国科学院微电子研究所 | A high-precision etching method |
| CN112366135A (en) * | 2020-10-26 | 2021-02-12 | 北京北方华创微电子装备有限公司 | Silicon atomic layer etching method |
| US11447876B2 (en) | 2018-08-28 | 2022-09-20 | Institute of Microelectronics, Chinese Academy of Sciences | High-precision etching method |
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| CN110867373A (en) * | 2018-08-28 | 2020-03-06 | 中国科学院微电子研究所 | A high-precision etching method |
| US11447876B2 (en) | 2018-08-28 | 2022-09-20 | Institute of Microelectronics, Chinese Academy of Sciences | High-precision etching method |
| CN110867373B (en) * | 2018-08-28 | 2023-02-17 | 中国科学院微电子研究所 | A high-precision etching method |
| US11827988B2 (en) | 2018-08-28 | 2023-11-28 | Institute of Microelectronics, Chinese Academy of Sciences | High-precision etching method |
| CN110010460A (en) * | 2019-03-26 | 2019-07-12 | 贵阳学院 | A kind of low-dimensional material formation method |
| CN110010460B (en) * | 2019-03-26 | 2021-03-16 | 贵阳学院 | A kind of low-dimensional material formation method |
| CN112366135A (en) * | 2020-10-26 | 2021-02-12 | 北京北方华创微电子装备有限公司 | Silicon atomic layer etching method |
| CN112366135B (en) * | 2020-10-26 | 2024-06-21 | 北京北方华创微电子装备有限公司 | Silicon atomic layer etching method |
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