CN107423054B - Self-defined graphical algorithm configuration device, system and method based on FPGA - Google Patents
Self-defined graphical algorithm configuration device, system and method based on FPGA Download PDFInfo
- Publication number
- CN107423054B CN107423054B CN201710512792.4A CN201710512792A CN107423054B CN 107423054 B CN107423054 B CN 107423054B CN 201710512792 A CN201710512792 A CN 201710512792A CN 107423054 B CN107423054 B CN 107423054B
- Authority
- CN
- China
- Prior art keywords
- algorithm
- graphic
- block
- configuration
- library
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000006870 function Effects 0.000 claims description 5
- 238000012512 characterization method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 8
- 238000011161 development Methods 0.000 description 7
- 230000000007 visual effect Effects 0.000 description 5
- 230000008676 import Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/34—Graphical or visual programming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Stored Programmes (AREA)
Abstract
The invention belongs to the technical field of automatic control, and aims to provide a self-defined graphical algorithm configuration device, a self-defined graphical algorithm configuration system and a self-defined graphical algorithm configuration method which can be independently controlled and are not limited by a third party and are based on an FPGA (field programmable gate array); the device comprises: the self-defined graph library is set to comprise a graph block for representing the FPGA logical operation; a customized algorithm library configured to include algorithm blocks corresponding to each graphic block in the customized graphic library; the graphic configuration module is set to be capable of calling the graphic blocks in the customized graphic library to perform customized algorithm configuration; the graphic logic relationship identification module is configured to analyze the relationship of the user-defined graphic algorithm configuration in the graphic configuration module and acquire the logic relationship of the algorithm; and the code generation module is used for calling the algorithm blocks in the self-defined algorithm library to generate machine language codes based on the logic relation of the algorithm acquired by the graphic logic relation identification module.
Description
Technical Field
The invention relates to the technical field of automatic control, in particular to a user-defined graphical algorithm configuration device, a user-defined graphical algorithm configuration system and a user-defined graphical algorithm configuration method based on an FPGA (field programmable gate array), and more particularly to a graphical algorithm configuration device, a graphical algorithm configuration system and a graphical algorithm configuration method applied to a DCS (distributed control system) based on an FPGA of a nuclear power station.
Background
DCS is an english abbreviation (Distributed Control System) of Distributed Control System, is also called as Distributed Control System in the domestic automatic Control industry, and is a novel computer Control System relative to a centralized Control System. With the rapid development of the FPGA technology, it is a future development trend to apply the FPGA technology based on parallel processing to the DCS field.
However, the inventor finds that in the prior art, the FPGA technology is limited in that a third-party interface of a supplier is not open, and the graphic configuration design of the FPGA system is complicated, for example, in a Libero integrated development environment in the prior art, only the schematic diagram based input design mode can adopt the graphic configuration.
And has the following problems:
1) the configuration mode is not friendly, and a clock and a reset signal need to be configured for synchronizing the algorithm;
2) and the configuration data display is not visual, and decimal display cannot be supported.
Disclosure of Invention
The invention aims to provide a self-defined graphical algorithm configuration device, a self-defined graphical algorithm configuration system and a self-defined graphical algorithm configuration method based on an FPGA, which can be controlled independently and are not limited by a third party, and can realize the content of the self-defined graphical algorithm configuration.
In order to achieve the above object, the technical solution provided by the present invention comprises:
on the one hand, a customized graphical algorithm configuration device based on FPGA is provided, which is characterized by comprising:
the self-defined graph library is set to comprise a graph block for representing the FPGA logical operation;
a customized algorithm library configured to include algorithm blocks corresponding to each graphic block in the customized graphic library;
the graphic configuration module is set to be capable of calling the graphic blocks in the customized graphic library to perform customized algorithm configuration;
the graphic logic relationship identification module is configured to analyze the relationship of the user-defined graphic algorithm configuration in the graphic configuration module and acquire the logic relationship of the algorithm;
and the code generation module is used for calling the algorithm blocks in the self-defined algorithm library to generate machine language codes based on the logic relation of the algorithm acquired by the graphic logic relation identification module.
Preferably, in the embodiment of the present invention, the customized graphic library, the customized algorithm library, the graphic configuration module, the graphic logical relationship identification module, and the code generation module are disposed in a DCS system based on an FPGA.
Preferably, the input, output and parameters of the graphic block and the algorithm block are consistent; the algorithm block includes a clock and reset signal that need to be automatically assigned by the code generation module.
Preferably, in the embodiment of the present invention, when the graphic logical relationship identification module identifies that there is a certain type of graphic block in the graphic configuration module, a header file of an algorithm block corresponding to the graphic block is added to the code file to be generated.
Preferably, in the embodiment of the present invention, the customized graphic library includes a graphic block name, a graphic block input port name, an input port type, a graphic block output port name, an output port type, a parameter type, an I/O input variable, an I/O output variable, a network input variable, and a network output variable.
Preferably, in the embodiment of the present invention, the code generation module generates Verilog HDL code according to hardware language rules and code conversion rules.
Preferably, in the embodiment of the present invention, the file stored by the graphic configuration module includes: the names and the numbers of the input and output variables and the network variables, the numbers and the names of the graphic blocks, and the connection relations among the input and output variables and/or the network variables and/or the graphic blocks.
Preferably, in the embodiment of the present invention, the custom algorithm library includes an algorithm block name, a clock port, a reset signal port, an input port, an output port, a parameter port, and an operation logic.
On the other hand, the invention also provides a self-defined graphical algorithm configuration system based on the FPGA, which comprises an engineering application algorithm module and a configuration output module; the system is characterized by further comprising an algorithm configuration device located between the engineering application algorithm module and the configuration output module, wherein the algorithm configuration device is any one of the FPGA-based customized graphical algorithm configuration devices.
In a third aspect, the present invention further provides a method for configuring a custom graphical algorithm based on an FPGA, which is characterized by comprising:
defining a graph library comprising characterization of the FPGA logical operation by a graph block;
customizing algorithm blocks to comprise an algorithm library corresponding to each graphic block in the customized graphic library;
calling the graphic blocks in the customized graphic library to perform customized algorithm configuration;
analyzing the relationship of the user-defined graphic algorithm configuration to obtain the logical relationship of the algorithm;
and calling the algorithm block in the self-defined algorithm library based on the logic relation of the algorithm to generate a machine language code.
Preferably, the input, output and parameters of the graphic block and the algorithm block are consistent; the algorithm block includes a clock and reset signal that need to be automatically assigned by the code generation module.
Preferably, in the embodiment of the present invention, when the graphic logical relationship identification module identifies that there is a certain type of graphic block in the graphic configuration module, a header file of an algorithm block corresponding to the graphic block is added to the code file to be generated.
Preferably, in the embodiment of the present invention, the code generation module generates Verilog HDL code according to hardware language rules and code conversion rules.
By adopting the technical scheme provided by the invention, at least one of the following beneficial effects can be obtained:
1. compared with a traditional schematic diagram input mode based on an FPGA development tool, the advantages of the FPGA are fully utilized through customizing the graphic blocks and the algorithm blocks corresponding to the graphic blocks and through an autonomous definition mode, and meanwhile the problems that algorithm configuration is unfriendly, display is not visual and graphical import is not supported in the prior art are solved.
2. The algorithm block comprises a clock and a reset signal, and the clock and the reset signal need to be automatically assigned by the code generation module, so that the technical problem that the clock and the reset signal need to be configured in the prior art is solved.
3. The generated Verilog HDL code can be more automatically matched with the requirements of industrial control automation equipment.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure and/or process particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
Fig. 1 is a schematic structural diagram of a custom graphical algorithm configuration system based on an FPGA according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a custom graphical algorithm configuration device based on an FPGA according to an embodiment of the present invention.
Fig. 3 is a flowchart of a method for configuring a custom graphical algorithm based on an FPGA according to an embodiment of the present invention.
Fig. 4 is a flowchart of a method for configuring a customized graphic algorithm based on an FPGA according to another embodiment of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that the detailed description is only for the purpose of making the invention easier and clearer for those skilled in the art, and is not intended to be a limiting explanation of the invention; moreover, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are all within the scope of the present invention.
Additionally, the steps illustrated in the flow charts of the drawings may be performed in a control system such as a set of controller-executable instructions and, although a logical ordering is illustrated in the flow charts, in some cases, the steps illustrated or described may be performed in an order different than that illustrated herein.
The technical scheme of the invention is described in detail by the figures and the specific embodiments as follows:
examples
As shown in fig. 1, the embodiment provides a customized graphical algorithm configuration system based on FPGA, which includes an engineering application algorithm module 100, i.e., an input module of the system, through which a subsequent module can execute specific contents of an engineering application algorithm that is desired to be implemented; a configuration output module 300, namely an output end of the system, obtains a specific result output by the engineering algorithm; and a custom algorithm configuration device 200 located between the engineering application algorithm module and the configuration output module, where the custom algorithm configuration device 200 is a custom graphical algorithm configuration device based on an FPGA (Field-Programmable Gate Array), and a specific structure of the device 200 is shown in fig. 2; in addition, the customization mentioned in this embodiment is preferably a technical scheme of recreating a graphical configuration according to the requirement in the DCS without being limited by the FPGA port itself.
As shown in fig. 2, the present embodiment provides a custom graphic algorithm configuration device based on FPGA, which includes:
a customized graph library 2010 configured to include graph blocks representing FPGA logical operations; the graphic blocks in the customized graphic library 2010 can be customized graphics stored in a hardware memory;
a custom algorithm library 2020 configured to include an algorithm block corresponding to each graphic block in the custom graphic library; that is, each algorithm block in the customized algorithm library 2020 can correspond to an algorithm block representing the graph through a predetermined mapping relationship, so that a user can realize a configuration algorithm in a graphical manner;
the graphic configuration module 2030, configured to call a graphic block in the customized graphic library 2010 to perform customized algorithm configuration; analyzing the algorithm configuration to be called according to the engineering application algorithm module 100, calling corresponding graphic blocks from the customized graphic library 2010, and combining the graphic blocks to form the graphic algorithm configuration;
the graphic logical relationship identification module 2040 is configured to analyze the relationship of the user-defined graphic algorithm configuration in the graphic configuration module to obtain the logical relationship of the algorithm; the graphic logical relationship recognition module 2040 analyzes the inputted configuration relationship in the algorithm configuration, and then obtains the actual algorithm to be processed corresponding to the engineering application algorithm module 100 to be actually inputted, wherein the analysis is performed in such a way that the actual algorithm logical relationship is obtained through the connection relationship between the graphic blocks;
the code generation module 2050 calls the algorithm blocks in the customized algorithm library based on the logic relationship of the algorithm obtained by the graphic logic relationship identification module to generate machine language codes; namely, the code generating module 2050 calls the actual algorithm block corresponding to each graph block in the customized algorithm library 2020 according to the logical relationship identified by the graph logical relationship identifying module 2040, and then obtains the logical graph corresponding to the actual algorithm logical operation block according to the graph algorithm configuration, so that the user can automatically output the corresponding algorithm logic by inputting a simple graph configuration algorithm, and the graph algorithm configuration device generates the budget code which can be identified by the machine, and then outputs the budget code to the configuration output module 300.
Therefore, compared with the traditional schematic diagram input mode based on an FPGA development tool, the device solves the problems that the algorithm configuration is not friendly, the display is not visual and the graphical import is not supported through self-defining the graph block and the algorithm block corresponding to the graph block by self-defining the graph block and through an independent definition mode.
Preferably, in this embodiment, the customized graphic library, the customized algorithm library, the graphical configuration module, the graphic logic relationship identification module, and the code generation module are disposed in the FPGA-based DCS system, that is, the FPGA-based DCS system can customize a graphical algorithm configuration device in the system without calling a graphical algorithm configuration function with limited functions in the FPGA, so that the FPGA-based DCS system configuration mode is more flexible, and can be defined and edited by a user according to the user's own needs.
In the embodiment, preferably, the input, output and parameters of the graphic block and the algorithm block are consistent; the algorithm block includes a clock and reset signal, and the clock and reset signal need to be automatically assigned by the code generation module.
Preferably, in this embodiment, when the graphic logical relationship identification module identifies that there is a certain type of graphic block in the graphic configuration module, a header file of an algorithm block corresponding to the graphic block is added to the code file to be generated, so that the graphic block and the algorithm block can be better corresponded.
Preferably, in this embodiment, the customized graphics library 2010 includes a name of a graphics block, a name of an input port of the graphics block, a type of the input port, a name of an output port of the graphics block, a type of the output port, a parameter, a type of the parameter, an I/O input variable, an I/O output variable, a network input variable, and a network output variable.
Preferably, the code generation module 2050 generates Verilog HDL code according to hardware language rules and code conversion rules, so that the output result can more automatically match the requirements of the industrial control automation equipment.
As shown in fig. 3, this embodiment further provides a method for configuring a custom graphic algorithm based on an FPGA, where the method includes:
s310, defining a graph library comprising representation FPGA logical operation by using a graph block; the graphic blocks in the customized graphic library 2010 may be customized graphics stored in hardware memory
S320, customizing an algorithm library comprising an algorithm corresponding to each graphic block in the customized graphic library by using an algorithm block; each graphic block can correspond to one algorithm block representing the graphic through a preset mapping relation, so that a user can realize a configuration algorithm in a graphical mode;
s330, calling a customized graphic block in the graphic library to perform customized algorithm configuration; analyzing the algorithm configuration to be called according to the engineering application algorithm module 100, calling corresponding graphic blocks from a customized graphic library, and combining the graphic blocks to form the graphic algorithm configuration;
s340, analyzing the relationship of the user-defined graphic algorithm configuration to obtain the logical relationship of the algorithm; analyzing the inputted configuration relationship in the algorithm configuration, and then acquiring the actual algorithm to be processed corresponding to the engineering application algorithm module 100 to be actually inputted, wherein the analyzing mode is to obtain the actual algorithm logical relationship through the connection relationship between the graphic blocks;
s350, calling a self-defined algorithm block in an algorithm library based on the logic relation of the algorithm obtained by the graphic logic relation recognition module to generate a machine language code; the method comprises the steps of calling actual algorithm blocks corresponding to each graph block in a self-defined algorithm library according to the identified logical relationship of the algorithm, and then obtaining a logical graph corresponding to the actual algorithm logical operation blocks according to the graph algorithm configuration, so that a user can automatically output corresponding algorithm logics by inputting a simple graph configuration algorithm through a graph algorithm configuration device, and budget codes which can be identified by a machine are generated.
Therefore, compared with the traditional schematic diagram input mode based on an FPGA development tool, the method has the advantages that the advantages of the FPGA are fully utilized through customizing the graphic blocks and the algorithm blocks corresponding to the graphic blocks and through the self-defining mode, and meanwhile the problems that algorithm configuration is not friendly, display is not visual and graphical import is not supported in the prior art are solved.
In this embodiment, preferably, in the method, the input, output and parameters of the graphic block and the algorithm block are consistent; the algorithm block includes a clock and reset signal, and the clock and reset signal need to be automatically assigned by the code generation module.
In this embodiment, preferably, in the above method, when the graphic logical relationship identification module identifies that there is a certain type of graphic block in the graphic configuration module, a header file of an algorithm block corresponding to the graphic block is added to the code file to be generated.
Preferably, in the above method, the Verilog HDL code is generated according to the hardware language rule and the code conversion rule.
More specifically, as shown in fig. 4, a method for configuring a customized graphic algorithm based on an FPGA according to another embodiment of the present invention includes:
and S410, defining the graphic block, and defining the required graphic block according to the type of the algorithm in the engineering application algorithm module.
The graphic blocks are stored in a user-defined graphic library, and the user-defined graphic library comprises the graphic blocks, I/O input variables, I/O output variables, network input variables and network output variables.
Wherein, the content corresponding to the graphic block comprises: the name of a graphic block, the name of an input port of the graphic block, the type of the input port (including real type and Boolean type), the name of an output port of the graphic block, and the type of the output port (including real type and Boolean type);
wherein, the I/O input variable comprises a variable name, a variable type (comprising a real type and a Boolean type);
the I/O output variables include: quantity name, variable type (including true, boolean);
the network input variables include: variable name, variable type (including real type, boolean type);
the network output variables include: name of variable, type of variable (including true, Boolean)
Each graph block in the graph library is provided with an algorithm block corresponding to the graph block in the algorithm library; each algorithm block includes the following information: the method comprises the following steps that (1) the name of an algorithm block, a clock port, a reset signal port, an input port, an output port, a parameter port and operation logic are different, and the logic is also different according to different functions of the algorithm block; and the input, output and parameters of the graphic block and the algorithm block are consistent, but a clock and a reset signal exist in the algorithm block, and the clock and the reset signal need to be automatically assigned by the code generation module.
S420, after the graphic block is defined (S410), the graphic configuration module performs the configuration.
The graphical configuration storage file comprises: I/O (input/output) and network variable names and numbers, and the number and names of the graphic blocks, and the connection relation among the graphic blocks.
S430, checking a configuration file:
the graphic logic relationship identification module is used for checking the graphic configuration file and mainly comprises the following steps: detecting whether the ports are connected or not; and detecting whether the data types of the connected ports are consistent.
S440, graphic logic relationship identification, namely identifying the name and the connection relationship of the configured graphic block.
And S450, combining the identified graphical logic relationship with the prestored hardware description language and code conversion rule (S460), and generating codes, namely, according to the file stored by the graphical configuration, finishing the generation of the logic operation machine codes. The method specifically comprises the following steps:
1) when a certain type of graphic block is identified, adding a header file of an algorithm library corresponding to the code file to be generated;
2) and the input port is defined, the input declares the input port, the bit width of the [ X:0] port is X +1 bit, and the in _ put XXX is the port name. Automatically defining input signals according to the I/O and the name and the number of the network variables;
input[X:0]in_put XXX
3) and the output port is defined, the output declares the output port, the bit width of the [ X:0] port is X +1 bit, and the port XXX is the port name. Automatically defining output signals according to the I/O and the name and the number of the network variables;
output[X:0]out_put XXX
4) module (machine language) is the key word for module start, followed by module name, in parenthesis is the list of input and output ports, and the following is added automatically in the program:
module FB0XX(XX，XX)
5) the definition of the connection line, the declaration type of wire (machine language) is wire net type, the bit width of [ X:0] line is X +1 bit, and wire XXX is the name of line. The real type bit width is defined as 40 bits and the boolean type as 2 bits. Defining the input and output of all algorithm blocks in the configuration file as line types;
wire[X:0]wire_XXX
6) constant parameter assignment, wherein the parameters are generally defined as connecting lines, assign the parameter values to the algorithm ports by adopting assign as an assignment statement;
assign wire_XXX＝XXX
7) all input and output ports are assigned with values, and the rule is that a line is assigned to another line first and then another line is assigned to an output port; the purpose of this is that some lines are 1 to a plurality of output ports, in order to distinguish every 1 output port line, each output port line is named automatically;
assign wire_XXX＝wire_XXX
8) calling the algorithm block, taking D2V3_ T1 as an example, wherein D2V3_ T1 is the name of the algorithm block, D2V3_ T1_0 or D2V3_ T1_1 is the name of the algorithm block in the configuration diagram, ". the red word behind" represents the port name of the algorithm block, and the content given in "()" represents the name of the line; and automatically completing instantiation of the algorithm block according to the name of the algorithm block, wherein the clock and the reset signal are automatically assigned through a system clock and a reset clock, and the input and output ports are automatically assigned by adopting a connecting line.
And S460, outputting the Verilog HDL file, namely finishing the automatic generation of Verilog codes by graphics.
It should be noted that the method for configuring the customized graphic algorithm based on the FPGA in the embodiment corresponding to fig. 4 is also applicable to the apparatus for configuring the customized graphic algorithm based on the FPGA in fig. 2.
By adopting the technical scheme, at least one of the following beneficial effects can be obtained:
1. compared with a traditional schematic diagram input mode based on an FPGA development tool, the advantages of the FPGA are fully utilized through customizing the graphic blocks and the algorithm blocks corresponding to the graphic blocks and through an autonomous definition mode, and meanwhile the problems that algorithm configuration is unfriendly, display is not visual and graphical import is not supported in the prior art are solved.
2. The algorithm block comprises a clock and a reset signal, and the clock and the reset signal need to be automatically assigned by the code generation module, so that the technical problem that the clock and the reset signal need to be configured in the prior art is solved.
3. The generated Verilog HDL code can be more automatically matched with the requirements of industrial control automation equipment.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be understood that the above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Those skilled in the art can make many changes and simple substitutions to the technical solution of the present invention without departing from the technical solution of the present invention, and the technical solution of the present invention is protected by the following claims.
Claims (9)
1. A self-defined graphical algorithm configuration device based on FPGA is characterized by comprising:
the self-defined graph library is set to comprise a graph block for representing the FPGA logical operation;
a customized algorithm library configured to include algorithm blocks corresponding to each graphic block in the customized graphic library;
the graphic configuration module is set to be capable of calling the graphic blocks in the customized graphic library to perform customized algorithm configuration;
the graphic logic relationship identification module is configured to analyze the relationship of the user-defined graphic algorithm configuration in the graphic configuration module and acquire the logic relationship of the algorithm;
the code generation module is used for calling the algorithm blocks in the self-defined algorithm library to generate machine language codes based on the logic relation of the algorithm obtained by the graphic logic relation recognition module;
each graph block in the graph library is provided with an algorithm block corresponding to the graph block in the algorithm library; each algorithm block includes the following information: the method comprises the following steps that (1) the name of an algorithm block, a clock port, a reset signal port, an input port, an output port, a parameter port and operation logic are different, and the logic is also different according to different functions of the algorithm block; the input, output and parameters of the graphic block and the algorithm block are consistent; the algorithm block comprises a clock and a reset signal, and the clock and the reset signal need to be automatically assigned by a code generation module;
the rule of all I/O port assignment is that a line is assigned to another line first, and then another line is assigned to an output port; this is done so that some lines are 1 for multiple output ports, and to distinguish every 1 output port line, each output port line is automatically named.
2. The apparatus of claim 1, wherein when the graphic logical relationship identification module identifies a certain type of graphic blocks in the graphic configuration module, a header file of corresponding algorithm blocks is added to the code file to be generated.
3. The apparatus of claim 1, wherein the custom graphics library comprises a graphics block name, a graphics block input port name, an input port type, a graphics block output port name, an output port type, a parameter type, an I/O input variable, an I/O output variable, a network input variable, and a network output variable.
4. The apparatus of claim 1, wherein the file stored by the graphic configuration module comprises: the names and the numbers of the input and output variables and the network variables, the numbers and the names of the graphic blocks, and the connection relations among the input and output variables and/or the network variables and/or the graphic blocks.
5. The apparatus according to any one of claims 1 to 4, wherein the code generation module generates Verilog HDL code according to hardware language rules and code conversion rules.
6. A self-defined graphical algorithm configuration system based on FPGA comprises an engineering application algorithm module and a configuration output module; the system is characterized by further comprising an algorithm configuration device positioned between the engineering application algorithm module and the configuration output module, wherein the algorithm configuration device is the FPGA-based customized graphical algorithm configuration device of any one of claims 1 to 5.
7. A self-defined graphical algorithm configuration method based on FPGA is characterized by comprising the following steps:
defining a graph library comprising characterization of the FPGA logical operation by a graph block;
customizing algorithm blocks to comprise an algorithm library corresponding to each graphic block in the customized graphic library;
calling the graphic blocks in the customized graphic library to perform customized algorithm configuration;
analyzing the relationship of the user-defined graphic algorithm configuration to obtain the logical relationship of the algorithm;
calling the algorithm block in the self-defined algorithm library based on the logic relation of the algorithm to generate a machine language code;
each graph block in the graph library is provided with an algorithm block corresponding to the graph block in the algorithm library; each algorithm block includes the following information: the method comprises the following steps that (1) the name of an algorithm block, a clock port, a reset signal port, an input port, an output port, a parameter port and operation logic are different, and the logic is also different according to different functions of the algorithm block; the input, output and parameters of the graphic block and the algorithm block are consistent; the algorithm block comprises a clock and a reset signal, and the clock and the reset signal need to be automatically assigned by a code generation module;
the rule of all I/O port assignment is that a line is assigned to another line first, and then another line is assigned to an output port; this is done so that some lines are 1 for multiple output ports, and to distinguish every 1 output port line, each output port line is automatically named.
8. The method of claim 7, wherein when the graphic logical relationship identification module identifies a certain type of graphic blocks in the graphic configuration module, a header file of the corresponding algorithm blocks is added to the code file to be generated.
9. The method of claim 7 or 8, wherein the code generation module generates Verilog HDL code according to hardware language rules and code conversion rules.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710512792.4A CN107423054B (en) | 2017-06-29 | 2017-06-29 | Self-defined graphical algorithm configuration device, system and method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710512792.4A CN107423054B (en) | 2017-06-29 | 2017-06-29 | Self-defined graphical algorithm configuration device, system and method based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107423054A CN107423054A (en) | 2017-12-01 |
| CN107423054B true CN107423054B (en) | 2021-03-19 |
Family
ID=60427847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710512792.4A Active CN107423054B (en) | 2017-06-29 | 2017-06-29 | Self-defined graphical algorithm configuration device, system and method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107423054B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108319453A (en) * | 2017-12-20 | 2018-07-24 | 中核控制系统工程有限公司 | A kind of algorithm configuration software design approach based on FPGA control logics |
| US20200210869A1 (en) * | 2018-12-28 | 2020-07-02 | Siemens Aktiengesellschaft | Gateway and method for transforming a description of an industrial process equipment into a data information model |
| CN109976723B (en) * | 2019-03-12 | 2022-08-12 | 北京国电智深控制技术有限公司 | Algorithm development platform, algorithm development method and computer readable storage medium |
| CN110244936B (en) * | 2019-04-28 | 2022-11-08 | 北京广利核系统工程有限公司 | Method and device for supporting VISIO flow chart to automatically import DCS algorithm configuration software |
| CN113534682B (en) * | 2020-04-16 | 2024-09-03 | 北京国电智深控制技术有限公司 | Method and apparatus for managing logic blocks in an industrial controller |
| CN111552238A (en) * | 2020-04-17 | 2020-08-18 | 达闼科技（北京）有限公司 | Robot control method, device, computing equipment and computer storage medium |
| CN112363975B (en) * | 2020-10-27 | 2024-02-06 | 国核自仪系统工程有限公司 | Interaction method and interaction system for configuration software and FPGA |
| CN112965794B (en) * | 2021-02-19 | 2024-03-22 | 西安智周深鉴信息科技集团有限公司 | Algorithm calling method, electronic equipment and storage medium |
| CN113703405B (en) * | 2021-08-27 | 2024-06-04 | 中国核动力研究设计院 | Nuclear power DCS algorithm configuration logic diagram drawing system |
| CN113987785B (en) * | 2021-10-26 | 2023-09-26 | 中国核动力研究设计院 | Management method and device for complete information of algorithm block of nuclear power station DCS system |
| CN119166389A (en) * | 2024-09-23 | 2024-12-20 | 东北大学 | A data processing and interaction system and method based on algorithm modular encapsulation |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101135965A (en) * | 2006-08-29 | 2008-03-05 | 深圳达实智能股份有限公司 | Realization method of configuration control |
| CN101566839A (en) * | 2009-06-01 | 2009-10-28 | 杭州电子科技大学 | Realizing method of trapezoidal pattern embedded configuration algorithm |
| CN104182590A (en) * | 2014-08-29 | 2014-12-03 | 国家电网公司 | Method for converting algorithm model of PSCAD (power system computer aided design) simulation system to source code |
| CN106528082A (en) * | 2016-09-27 | 2017-03-22 | 北京广利核系统工程有限公司 | FPGA (Field Programmable Gate Array)-based graphical configuration method and device |
| CN106708510A (en) * | 2016-11-28 | 2017-05-24 | 华南理工大学 | Graphical configuration-based industrial intelligent camera software system structure and method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9052891B2 (en) * | 2013-05-14 | 2015-06-09 | International Business Machines Corporation | Declarative configuration and execution of card content management operations for trusted service manager |
| CN106201462B (en) * | 2016-06-28 | 2019-04-16 | 南京国电南自电网自动化有限公司 | Protective relaying device configuration method based on component library |
-
2017
- 2017-06-29 CN CN201710512792.4A patent/CN107423054B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101135965A (en) * | 2006-08-29 | 2008-03-05 | 深圳达实智能股份有限公司 | Realization method of configuration control |
| CN101566839A (en) * | 2009-06-01 | 2009-10-28 | 杭州电子科技大学 | Realizing method of trapezoidal pattern embedded configuration algorithm |
| CN104182590A (en) * | 2014-08-29 | 2014-12-03 | 国家电网公司 | Method for converting algorithm model of PSCAD (power system computer aided design) simulation system to source code |
| CN106528082A (en) * | 2016-09-27 | 2017-03-22 | 北京广利核系统工程有限公司 | FPGA (Field Programmable Gate Array)-based graphical configuration method and device |
| CN106708510A (en) * | 2016-11-28 | 2017-05-24 | 华南理工大学 | Graphical configuration-based industrial intelligent camera software system structure and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107423054A (en) | 2017-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107423054B (en) | Self-defined graphical algorithm configuration device, system and method based on FPGA | |
| JP6351869B2 (en) | Engineering tools, systems and modules | |
| CN107220064B (en) | A kind of digital control system interface configuration development approach | |
| US9412193B2 (en) | Run-time optimized shader program | |
| CN107203473A (en) | The automatization test system and method for automatic expansion interface test case | |
| KR101627769B1 (en) | Apparatus and method of transforming text type of plc control program into common type of plc control program | |
| JP4302146B2 (en) | Program creation support device | |
| CN109976723B (en) | Algorithm development platform, algorithm development method and computer readable storage medium | |
| CN110532447A (en) | A kind of business data processing method, device, medium and equipment | |
| CN117032536B (en) | A method and device for quickly constructing an OTX diagnostic sequence | |
| CN105117404B (en) | Based on the chart display defect optimization method under subtype and data feature scene | |
| CN112527286A (en) | Service code generation method and device, computer equipment and storage medium | |
| CN113238746A (en) | Hybrid programming control method, device, equipment and storage medium | |
| US12140936B2 (en) | Configuring modular industrial plants | |
| CN102306109A (en) | Method for realizing logic programming in communication management machine | |
| CN117216135A (en) | ETL execution template generation method | |
| CN104460532A (en) | Non-programming controller | |
| CN115495362A (en) | Method, device, storage medium and computer equipment for generating test code | |
| CN111401020A (en) | Interface loading method and system and computing equipment | |
| CN111352381B (en) | Programmable logic controller programming method, programmable logic controller and system | |
| CN114064027B (en) | WINCC upper computer calling variable method | |
| JP2003223204A (en) | Programming method of programmable controller, system thereof and recording medium thereof | |
| CN116009851B (en) | Method, device, computer equipment and storage medium for integrating and publishing target model | |
| CN117992065A (en) | Data stream analysis method, device, storage medium and terminal | |
| KR100423742B1 (en) | Exclusive control system by sequential function chart |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |